AN-877

One Technology Way P.O. Box 9106 Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 www.analog.com

SPI ADC

CSB 0

SCLK

SCLK

SDIO

SDIO

CSB

SPICONTROLLER

CONVERTERINTERFACE

0573

9-00

1

1.

CSB 0 CSB

CSB 1 SCLK CONVERTER

SPI INTERFACECONTROLLER SCLK DEVICE 1

SDIO

SDIO

CSB

SCLK CONVERTERINTERFACE

SDIO DEVICE 2

0573

9--0

13

2.

Rev. A | Page 1 of 20

ADI SPI

SPI

SPI (SCLK)/ (SDIO) (CSB)

(SDO)

AN-877

12/05— Revision 0: Initial Version

Rev. A | Page 2 of 20

..................................................................................................... 1 ..................................................................................................... 1

SPI ....................................................................................... 3 (SCLK) ........................................................................ 3 / (SDIO) ....................................................... 3 (CSB) ........................................................................... 3 (SDO) .................................................................. 4

..................................................................................................... 5 .................................................................................... 5 READ/WRITE ............................................................................. 5 ............................................................................................ 5 ........................................................................................ 6 ........................................................................................ 6 ........................................................................... 6 ................................................................................... 6SPI ............................................................... 7 .................................................................................... 7

............................................................................................ 8 (0x000) ..................................................................... 8 7—SDO .................................................................. 8 6—LSB .................................................................... 8 5— .............................................................. 8 4— .......................................................................... 8 (0x0FF) ............................................ 8 0— .................................................................. 9 7— .......................................................... 9 ID(0x001) .................................................................... 9 (0x002) ................................................................ 9 (0x004 0x005 .................................................... 9 7 4— ....................................................... 9

....................................................... 9 ........................................................................................ 9

........................................................................................ 9 ............................................................................. 10

..................................................................... 10 ..................................................................... 10 ............................................................. 11

......................................................... 11 ............................................................ 11 (0x00D) ..................................................... 11 ............................................................. 13 ............................................................. 13 ............................................................. 13 ............................................................. 13

............................................................. 14 (0x015) .............................................................. 14 ................................................. 14

..................................................... 14 ..................................................... 15 ....................................... 15 ............................................. 15 ..................................................... 15 .......................................... 15 .................................................................... 15 .................................................................... 16 ............................................................ 16 ............................................................ 16

.......................................................................................... 17 ...................................................................................... 18

2007 4 — A

...................................................................................... ................................................................ 8

........................................................................................... 10 ............................................................................................. 11

...................................................... 118 ............................................................................................. 12

AN-877

Rev. A | Page 3 of 20

SPISPI

ADC

(SCLK)

SCLK

50 kΩ

SCLK

SCLK 25 MHz (tCLK 40 ns)(tDH) 0 ns SCLK SDIO 5 ns

(tDS)

SCLK SDIOSDIO

ADC SPI

/ (SDIO)

SDIO

(SDIO)1 tEN_SDIO

tDIS_SDIO SDOSDO SDIO

SDOSDIO

(CSB)

CSB CSB

CSBSCLK SDIO

SCLKSDIO SPI

CSBCSB

CSBSPI

“SPI ” CSB50 kΩ

CSB5

CSBCSB

CSB

SPI

CSB CSB SPI

SPI

SPI SPISPI

SCLK SDIO SDO

“SPI ”

AN-877

CSB CSB

SCLK

SCLK

SDO SDO

SDI

SDIOSPI

HIGH-Z WHENCONTROLLER

CONVERTERINTERFACE

NOT USED ORINACTIVE

0573

9-00

2

1 1

tDS SCLKtDH SCLKtCLKtS CSB SCLKtH CSB SCLKtHI SCLK

tLO SCLK

tEN_SDIO SDIOSCLK

tDIS_SDIO SDIOSCLK

1 关于最小和最大额定值，请参考数据手册。3.

CSB

SCLK DON'T CARE DON'T CARE

tS

tDStDH

tHItLO

tCLK tH

W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0R/W

0573

9-00

3

SDIO DON'T CARE DON'T CARE

4. CSB

SCLK

SDIO

DON'T CARE

W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0R/W W1 DON'T CARE DON'T CARE D6 D5 D4 D3 D2 D1 D0D7

DON'T CARE

D6 D5 D4 D3 D2 D1 D0D7D6 D5 D4 D3 D2 D1 D0D7

16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N–1) DATA REGISTER (N–2) DATA

MSB-FIRST 16-BIT INSTRUCTION, 3 BYTES DATA WITH STALLING

5. MSB

CSB

0573

9-01

105

739-

012

SCLK

SDIO

DON'T CARE

W0 A11 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0R/W W1 . . .DON'T CARE

16-BIT INSTRUCTION HEADER REGISTER (N – 1) DATA REGISTER (N – 2) DATA

R/W W1DRIVEN OUTPUT DATA STREAM

MSB FIRST 16-BIT READ INSTRUCTION, 4 BYTES DATA 4-WIRE

REGISTER (N) DATA REGISTER (N – 3) DATA

SCLK SCLK

OUTPUT DRIVER OFF OUTPUT DRIVER ON OUTPUT DRIVER ON OUTPUT DRIVER OFF

tEN_SDIO tDIS_SDIO

6. SDIO

Rev. A | Page 4 of 20

(SDO)

SDOSDO

SCLK

SCLK25 MHz

20 ns

AN-877

CSB

W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0R/W W1DON'T CARE

DON'T CARE

0573

9-00

4

CL

SDIO

16-BIT INSTRUCTION HEADER

7.

Rev. A | Page 5 of 20

CSB SCLK

168 CSB

SCLK

16 4 7

READ/WRITE

/ (R/W)16

SDIO

“ ” SDOSDO

SDO SDIO

SDIO

CSB0x000 0x0FF

0x000 0x0FF

W1 W0(W1:W0 + 1)

00 01 10 CSB

11 CSBCSB

CSB CSBCSB

CSB 8

AN-877

2W1:W0 CSB

00 101 210 311 4 CSB

CSB

CSB

SCLK

SDIO R/W W1DON'T CARE

16-BIT INSTRUCTION HEADER

MSB-FIRST 16-BIT INSTRUCTION, 2 BYTES DATA

REGISTER (N) DATA REGISTER (N–1) DATA

DON'T CARE

CSB

DON'T CAREDON'T CARE

W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D6 D5 D4 D3 D2 D1 D0D7D6 D5 D4 D3 D2 D1 D0D7

SCLK DON'T CAREDON'T CARE

SDIO DON'T CARE D1 D2 D3 D4 D5 D6 D7D0D1 D2 D3 D4 D5 D6 D7D0A0 A1 A2 A3 A4 A5 A6 A7 W0A12A11A10A9A8 DON'T CAREW1 R/W

16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N–1) DATA

0573

9-00

5

LSB-FIRST 16-BIT INSTRUCTION, 2 BYTES DATA

8. MSB LSB

Rev. A | Page 6 of 20

W0 W1 0 1W0 W1 1 2

W0 W1 2 3

W0 W1 3CSB

CSBCSB

CSB

CSB1 2 3

CSB

13

W0W1

8CSB

CSB

MSB LSB “(0X000)” MSB

MSBLSB LSB

16 2MSB LSB

16 8

AN-877

CSB CSB

SDO

SDIO

SCLK SLAVE SPIMEMORY

1 TO 3 CONTROL BITS

01

01

01

0/1

0573

9-00

6

SCLK ORALT 1

SDIO ORALT 2

SDO OPTIONALOR ALT 3

PINMUX

SPI STATEMACHINE

HI-Z WHENNOT USEDOR INACTIVE

FIRST SPI INSTRUCTION

9.

PIC 12F629

GP2 CSB

GP0 SCLK

GP1 SDIOCONVERTERINTERFACE

0573

9-00

7

10. PIC

CSB

SCLK SCLKCONVERTER

SPI SERIAL SDO SDIOINTERFACE

DEVICE 1 PROM

SDIO

ENABLE

SCLK CLOCKCONTROLLERGENERATOR

0573

9-00

8

11. PROM

Rev. A | Page 7 of 20

SPISPI

() SPI

( )

SPI

()

CSB SPI

SPI

CSBCSB

CSBSPI ( “

” ) CSBCSB SPI

SPICSB SPI

SPI

CSB SCLK 9( )

CSB SPI9 CSB

SPICSB

SPISPI SPI

CSB SPI

SPI

( )

SPISPI

PICPROMS 10 11 PIC

AN-812 “ (SPI) ”

AN-877

3

7 SDO SDOSDO

SDIO

0SDIO

6 LSBLSB

MSB

0 MSB

5 0

4 1

Rev. A | Page 8 of 20

SPI

8

(0X000)

0x000

0x000

7 0 SDOSDO

SDO SDIOSDO

SDO

6 1MSB

LSB6

MSBLSB

MSB

5 2

(0x000)

7—SDO

6—LSB

5—

4 3 1

4—

(0x0FF)

0x000 0x004 0x0050x0FF

SPI

SPI

AN-877

CSB

SCLK

SDIO

DATA

MSB-FIRST WRITE INSTRUCTION

CSB

0573

9-00

9

SCLK

SDIO

DATA

LSB-FIRST WRITE INSTRUCTION

12.

DON'T CARE

A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE

DON'T CARE

INTERNAL TRANSFERSIGNAL (MASTER-SLAVE)

DON'T CARE

DON'T CARE D0 D1 D2 D3 D4 D5 D6 D7R/WW1

DON'T CARE

Rev. A | Page 9 of 20

0 10

CSB

77

13

0x001 ID

IDdie

ID

0x002

0x004 0x0050x005 ADC0

ADC3 0x004 ADC4 ADC7ADC

ADCADC

ADCADC

ADC

ADCADC

ADC0 3

0x0040x005

ADC(0 7)

ID (0x001)

7—

0—

0x004 0x005

(0x002)

7 4—

3 0—

AN-877

OPTIONALEXTERNAL

SYNC

ENCODECLOCK

0573

9-01

0

SLAVE SPIMEMORY

0x0FFBIT 0

MASTER SPIMEMORY

0x0FFBIT 7

BIT 0 RESET

QCLR

QSETD

0

1

13.

46 5

00h 01h 10h 11h

(0x008)

52 0

000h ( )001h 010h 011h (

000h )100h ADC ( AFE )101h AFE ( AFE )110h 111h

(0x009)

Rev. A | Page 10 of 20

0x004 0x005(

)

0x008

7—

7 ( ) ()

( 0 2)6 5

7[6:5] 7

7 5

6 5—

6 5

00

01

10

11

4—

3—

3

2 0—

2 0

000

001

010

011

100 ADC

(AFE)

101 AFE

110 111

0x009

7 3—

2— (PLL)

PLL

1—

1

0—

0 (DCS) 01 DCS 0x01

DCS

AN-877

PLL (0x00A)

62 0

00h 01h 110h 211h 3

71 0

00h 01h 10h 11h

123

(0x00D)

Rev. A | Page 11 of 20

0x00A PLL

7—PLL

PLL 1

6—PLL

1 PLL PLL

5 0

PLL 1

0x00B0

1

0x00C

7 4—

3 2—

DC DC 3 2

00

01 1

10 2

11 3

(0x00B)

(0x00C)

1 0—

ADC

1 0

00

01 1

10 2

11 3

0x00D0x00

ADC 1 2 3 5 60x014

0x014

7 6—

3 0 8

00 0x019 0x01A

01 1 0x019 0x01A2 0x01B 0x01C

10 10

11 12 0

5—PN23

5 PN (PN23) 1 PNPN

0x003AFF

4—PN9

4 PN (PN9) 1 PNPN

0x000092

3 0—

0000 ADC

0001

0010 +FS

0011 −FS

Table 8.

1 12 22

0000 N/A N/A 0001 1000000000000000 N/A 0010 +FS 1111111111111111 N/A 0011 −FS 0000000000000000 N/A 0100 1010101010101010 01010101010101010101 PN N/A N/A PN233

ITU 0.150 X23 + X18 + 1

0110 PN N/A N/A PN93 ITU 0.150 X9 + X5 + 1

0111 1/0 1111111111111111 0000 000000000000 1000 19 1A 1B 1C1001 1/0 1010101010101010 N/A 1010 1× 0000000011111111 N/A

1011 1 1000000000000000 N/A 1100 101000110011 12

1001100011 1010100001100111 1410100011 8

N/A

1101 1110 1111

1 2 3

Rev. A | Page 12 of 20

0010

0101 PN23 ITU 0.150X23 + X18 + 1 0x003AFF

0110 PN9 ITU 0.150X9 + X5 + 1 0x000092

0111 1 0

1000 7 60x08 7 6 00

01 1 0x0190x01A 2 0x01B 0x01C

10 1

011 1 2

0

1001 1/01/0

1010 01 ( 8 )

1011

1100 8

1101 1110 1111

AN-877

(0x00E)

97 4

0000h001h 1111h

Rev. A | Page 13 of 20

0x00E (BIST) BIST

BIST “ / ”BIST (MISR)

0x024 0x025

BIST PN

BISTPN

MISR 0x024 0x025

7 3—

2—BIST

2 BIST BISTMISR BISTMISR

1 0—BIST

00 BIST

01 BIST 1

BIST 1 ADCMISR 24h 25h

256 BIST2

10 11 BIST

(0x011)

(0x010)

(0x00F)

0x00F

7 4— ( )

7 4 00000001

1111

3—

2—

2 ADC1

1—

1 ADC

0—

0 1

0x010

0x000x7F 0x80

+1 0x01 -1 0xFF

0x011

AN-877

107 6

00h 001h 110h 211h 3

111 0

00h 01h 10h 11h

(0x015)

(0x016)

Rev. A | Page 14 of 20

7 6—

7 60

3 LVDS0x015

CMOS 0x015

5—

5 1ADC

4—

4CMOS/TTL

“ (0x008)”

3—

31

2—

2 1

1 0—

1 0

• 00

• 01

• 10

11

0x00

0x015 CMOS LVDS

7 4—

7 4 LVDS

3 0—

3 0 CMOS LVDS

0x0160x00B PLL

0x00

7—

7

6 4—

3 0—

3 0

0x017

ADC

7—

7

6—DLL

6 DLL DLL

DLL 7 5 0

(0x017)

(0x014)

AN-877

(0x018)

122 0

000h 001h / 8010h / 10011h / 12100h / 14101h / 16110h 111h

Rev. A | Page 15 of 20

5 0—

5 0 0x003F

0x018 /

7 6—VREF

[7:6] VREF

00 VREF

01 VREF

1×

5 0

5 0 VREF

0x019 0x01A0x01B 0x01C 0x01D 0x01E 0x01F

0x020 “(0x00)”

0x0212 0

7—LSB

1LSB MSB

6 4—

3—PLL

3 PLL

2 0

000

3 001 12 80 12

16

0x019 0x020

(0x021)

7 2—

1—

1 (ch_output_reset) 1LVDS

0—

0(ch_power_down) 1 ADCLVDS

0(ch_power_down) 1LVDS

0x024 (MISR)0x025 MISR MISR BIST (0x00E) MISR

7 1—

0—

0 1

MISR 0x024 0x025

(0x022)

(0x02A)

AN-877

137 4

0000h (DC)001h 1111h

Rev. A | Page 16 of 20

0x02B

7 5 3—

6—

6 1

2 0—

2 0 000001 111

(0x02C)

(0x02D)

(0x02B)

7 1—

0—

0

ADC

AN-877

Rev. A | Page 17 of 20

SPISPI SPI

AN-812

www.analog.com/FIFO

C

SPI

AN-812AN-812

AN-878

write(0, 18); //configure serial interface for MSB first

write(5, 3); //set Devices-Index to program ADC Channels 0 and 1

write(18, 80); //set vref to option 2 and adjustment to all zeros

write(14, 10); //set output_mode to level option 0, disable output MUX, enable output and offset binary

write(17, 83); //set output_delay to enable and set to delay value of 3

write(FF, 1); //write transfer bit (for configurations that require a manual transfer)

write(10, 3); //set offset to 3 (for Channel 1 only)

write(5, 2); //set Device-Index to program ADC Channel 1

write(FF, 1); //write transfer bit (for configurations that require a manual transfer)

Write(5, 4); //set Devices Index to program ADC Channel 2

write(10, 9); //set offset to 9 (for Channel 2 only)

write(FF, 1); //write transfer bit (for configurations that require a manual transfer)

“ ADC SPI ”

AN-877

14

1 7 (MSB) 6 5 4 3 2 1 0 (LSB) 1

00–chip_port_config SDO 2 LSB 18h

LSBMSB

01–chip_id 8 ID [7:0] ID

02–chip_grade 8 ID ID

04–device_index_B Aux 7 Aux 6 Aux 5 Aux 4 ADC 7 ADC 6 ADC 5 ADC 7 FFh

05–device_index_A Aux 3 Aux 2 Aux 1 Aux 0 ADC 3 ADC 2 ADC 1 ADC 0 FFh

08–modes 00h01h 10h 11h

0: 1: 2: 3: 4: ADC 5: 6: 7:

00h

09–clock PLL 01h

0A–PLL control PLL PLL PLL [5:0] 00h PLL PLL

MSB 1

0B–clock_divide [7:0] 00h 1

0C–enhance 0: 1: 1 2: 3:

0: 1: 1 2: 3:

DC

0D–tes t_io 00h 01h10h 11h

PN PN

0: 1: 2: +FS 3: −FS 4: 5: PN23 6: PN9 7: 1/08: 9: 1/0 10: 1× 11: 1 12: output_mode

00h 1

0E–test_bist BIST BIST 00h BIST

0F–adc_input 0: 1 15: ( )

00h

10–offset 8 [7:0] 80h

11–gain 8 [7:0] 00h

Rev. A | Page 18 of 20

AN-877

14–output_mode 0: 0 1: 1 2: 2 3: 3

( )

DDR 0: 1: 2: 3:

15–output_adjust [7:4] [3:0] LVDS

LVDS

16–output_phase [3:0] 00h

17–out put_delay DLL 6 [5:0] 00h

18–vref VREF 0: (0) 1: (1) 2: 2 3: 3

6 VREF [5:0] 20h / VREF

19–use r_patt1_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h 1 LSB

1A–user_patt1_ msb B15 B14 B13 B12 B11 B10 B9 B8 00h 1 MSB

1B–user_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h 2 LSB

1C–user_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 00h 2 MSB

1D–user_patt3_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h 3 LSB

1E–user_patt3_ msb B15 B14 B13 B12 B11 B10 B9 B8 00h 3 MSB

1F–user_patt4_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h 4 LSB

20–user_patt4_msb B15 B14 B13 B12 B11 B10 B9 B8 00h 4 MSB

21–se rial_control LSB PLL 000: 001: 8 010: 10011: 12 100: 14 101: 16

00h MSB

22–se rial_ch_stat 00h

24–misr_lsb B7 B6 B5 B4 B3 B2 B1 B0 00h MISR

25–misr_msb B15 B14 B13 B12 B11 B10 B9 B8 00h MISR

2A–fea tures OVR OVR 00h

2B–high pass 0 DC 1 7

00h

2C–ain 00h

2D–cross_point 00h

FF–device_update HW SW 00h

1 2

Rev. A | Page 19 of 20

1 7 (MSB) 6 5 4 3 2 1 0 (LSB) 1

AN-877

©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

AN05739-0-4/07(A)

Rev. A | Page 20 of 20