an 8-bit analog -to-digital converter based on the...

Symposia on VLSI Technology and Circuits

An 8-bit Analog-to-Digital Converter based on the Voltage-Dependent Switching

Probability of a Magnetic Tunnel Junction

Won Ho Choi*, Yang Lv*, Hoonki Kim, Jian-Ping Wang, and Chris H. Kim

*equal contribution

University of Minnesota, Minneapolis, MN

Outline• Background

– Analog-to-Digital Converter (ADC)– Magnetic Tunnel Junction (MTJ)

• Proposed MTJ-based “Probabilistic” ADC• Techniques for Improving Linearity and Input

Voltage Range• Summary

Slide 1

Analog-to-Digital Converter (ADC)

Slide 2

VIN DOUT

time

Ana

log

Am

plitu

de

time

Dig

ital

Valu

e

Resolution: N bits (=2N quantization steps)

Analog Digital

• ADC converts an analog input voltage to a digital code

• An N-bit ADC quantizes an analog voltage into 2N

discrete levels

Traditional ADC Architectures

Slide 3

• Flash ADC– Fast conversion rate (up to several Gs/s)– High power consumption– Low resolution (2 ~ 8 bit)

• Successive Approximation Register (SAR) ADC– High resolution (10 ~ 16 bit)– Low power consumption– Slow conversion rate (1Ks/s ~ several 100Ms/s)

VIN

DACDout

SAR logic Vref/4Vref/2

3Vref/4Vref VIN

Dout: 1 0 0 1 0 1

Vref

VIN

Ther

mom

eter

to

Bina

ry C

onve

rter

Dout

Magnetic Tunnel Junction (MTJ)

Slide 4

• Basic storage element of STT-MRAM memory• Spin polarized electrons rotate the magnetization

of free layer using spin transfer torque

IC

e-

STT switching

IC

e-

STT switching

Anti-parallel: High R

Anti-parallel

Parallel: Low R

Parallel

Free layerTunnel barrierPinned layer





Slide 5

Switching Probability of an MTJ

Slide 6

• Switching probability depends on the applied analog voltage (VMTJ)

VMTJ (a.u.)-3 -2 -1 0 1 2 3

Switc

hing

pro

babi

lity

(%)

100

80

60

40

20

0

1000ns500ns100ns50ns10ns5ns

P-AP switching AP-P switching

tPERTURB

H. Zhao, et al., TMAG, 2012.

Proposed MTJ-Based “Probabilistic” ADC

Slide 7

• Analog voltage random bit streamcompute probability of ‘1’s digital code

VREF

Sense Amp.

Bit stream of 0's and 1's

Counter

Bidirectionalpulse generator

CountRegister

DOUT

VIN

MTJ

Sample / hold circuit

0001000011000100: P(1) = 25%VIN = 0.4V DOUT = 410

1011010110010010: P(1) = 50%VIN = 0.5V DOUT = 810

1111011111011010: P(1) = 75%VIN = 0.6V DOUT = 1210

= 01002

= 10002

= 11002

MTJ Device Used for Experiments

Slide 8

• CoFeB based in-plane MTJ device with a TMR of 88% and a thermal stability of 64

Experimental Setup

Slide 9

• MTJ measurement setup with 1mV voltage resolution and <1 ̊C temperature accuracy

Puls

e G

ener

ator

1(A

gile

nt 8

1160

ATM

)

Puls

e G

ener

ator

2(H

P 81

10A

TM)

Power Combiner(Picosecond 5331-104TM)

Bias-Tee(Picosecond 5542-229TM)

MTJ

DAQ Board (NI USB-6343TM)

LabViewTM Interface

ADC

Resistance

DOUT

ResetPerturb

Read10kOhm

Power Supply (Kepco BOP20-20TM)

Kapton HeaterK-type Thermocouple Cable

Current Control

VIN

Measured Switching Probability Curve

Slide 10

0102030405060708090

Prob

abili

ty (%

)

30 °C85 °C

0102030405060708090

370

390

410

430

450

470

490

510

530

550

VIN (mV)

Prob

abili

ty (%

)

128 bits / sample 2,048 bits / sample

30 °C85 °C

tPERTURB = 5ns tPERTURB = 5ns

370

390

410

430

450

470

490

510

530

550

VIN (mV)

• A short 5ns tPERTURB used for suppressing thermal activation switching

• Averaging more bits gives a smoother and more accurate probability curve (128 bits vs. 2,048 bits)

• Temperature sensitivity is acceptably low

ADC Non-Linearity Metrics: Differential Non-Linearity (DNL)

Integral Non-Linearity (INL)

Slide 11

Analog Input

Dig

ital O

utpu

t

000001

010

011

101

110

1111 LSB

Input range

Analog Input

Dig

ital O

utpu

t000001

010

011

101

110

111

INLDNL+1LSB

Ideal ADC Real ADC

Measured Worst Case DNL and INL

Slide 12

0

0.5

1

1.5

2

2.5

64 512 4096# of bits / sample

30 °C85 °C

0

0.5

1

1.5

2

2.5

64 512 4096# of bits / sample

Wor

st c

ase

INL

(LSB

)

30 °C85 °C

tPERTURB = 5ns1LSB = 4mV

tPERTURB = 5ns1LSB = 4mV

Wor

st c

ase

DN

L (L

SB)

Our target

• A 5-bit ADC resolution is assumed (i.e. 1LSB = 4mV)• DNL of 1 LSB can be achieved by averaging more

random bits (e.g. 2,048 bits)• INL cannot be improved by simply averaging more bits





Slide 13

One-time Digital Calibration for Improving INL

Slide 14

• Basic idea: Pre-calibrate MTJ transfer curve and store the inverse function in a look-up table to compensate for inherent non-linearity

VINMTJ-based

ADC1bit Accumul-ator + DAC

Moving Average Filter

Look Up TableDOUT

DOUT_CAL

VIN

Prob

abili

ty (%

)

MTJ

Counter + Register

DO

UT Linearizer

DOUT_CAL

J. Kim, et al., TCAS-I, 2010, J. Daniels, et al., VLSI Circuits Symposium, 2010.

Measured DNL and INL @ 85 ̊C

Slide 15

-2

-1

0

1

2

DN

L (L

SB)

2,048 bits / sample @ 85ºC

Before digital calibration

DNLMAX = -0.75 / +0.73

-2

-1

0

12

INL

(LSB

)

Digital Out

INLMAX = -1.50 / +1.53

After digital calibration

DNLMAX = -1.00 / +0.82

Digital Out

INLMAX = -0.71 / +0.72

tPERTURB = 5ns tPERTURB = 5ns2,048 bits / sample @ 85ºC

3 7 11 15 19 23 27 31 35 393 7 11 15 19 23 27 31 35 39

0.81 LSB

• Target DNL / INL of 1 LSB can be met after one-time calibration

• ADC resolution limited to 5-bit due to narrow input voltage range

Proposed Input Range Enhancement Technique

Slide 16

VIN

Prob

abili

ty (%

)

2X Input range (2∙VIN,DYN)

Proposed scheme

VINPr

obab

ility

(%)

1X Input range (VIN,DYN)

VMTJ

MTJ

0V

VMTJ

MTJ

VOFFSET

Original scheme

VOFFSET = 0VVOFFSET = VIN,DYN

Implementation of Input Range Enhancement Technique

Slide 17

Volt. dividerfor 2M VOFFSETs

VOFFSETVREF

Sense Amp.

Bit stream of 0's and 1's

Counter

Bidirectionalpulse generator

CountRegister

DOUT

VIN

MTJ

Sample / hold circuit

Analog buffer

Input range enhancement technique

• A voltage divider and an analog buffer control the MTJ bottom node voltage

Measured Probability and Corresponding Digital Output

Slide 18

• 8x wider input voltage range 3 additional bits


0102030405060708090

-100 0 100 200 300 400 500 600 700 800 900 1000 1100

Prob

abili

ty (%

)

VIN (mV)0

50

100

150

200

250

300

Dig

ital O

utpu

t

000 001 010 011 100 101MSB: 110 111

tPERTURB = 5ns

Voffset = -384mV -256mV -128mV 0V 128mV 256mV 384mV 512mV

Measured DNL and INL @ 85 ̊C

Slide 19

• Target DNL / INL of 1 LSB can be met after calibration • 8-bit ADC resolution with good linearity is achieved


Before digital calibration

INLMAX = -1.52 / +1.55

After digital calibration

-2

-1

0

1

2

DN

L (L

SB)

DNLMAX = -1.00 / +1.00

tPERTURB = 5ns

Digital Out

-2

-1

0

1

2

INL

(LSB

)

DNLMAX = -1.00 / +1.00

tPERTURB = 5ns

INLMAX = -0.88 / +0.87

Digital Out

2,048 bits / sample@ 85ºC

0 28 56 84 112 140 168 196 224 252 0 28 56 84 112 140 168 196 224 252

0.68 LSB

ADC Performance Summary

Slide 20

Original MTJ-based ADC

+ Digital calibration

+ Digital calibration + Input range enhancement

DNLMAX (LSB)

0.74 1.32

1.00 0.76

1.00 0.84

Bits

5

5

8

0.75 1.53

1.00 0.72

1.00 0.88

Bits

5

5

8

30 ºC 85 ºC2,048 bits / sample

Input range

128mV(X1)

128mV(X1)

1024mV(X8)

DNLMAX (LSB)

INLMAX (LSB)

INLMAX (LSB)

• ADC resolution (=8 bit) was limited by the minimum voltage step (=1mV) of pulse generator. Actual resolution could be as high as 14 bits.

Summary• An 8-bit resolution MTJ-based ADC with

excellent linearity demonstrated for the first time– 2,048 bits averaged to generate one ADC sample– Insensitive to temperature using a 5ns pulse width– Digital calibration and input range enhancement

techniques

• This work was supported in part by C-SPIN, one of six centers of STARnet, a Semiconductor Research Corporation program, sponsored by MARCO and DARPA

Slide 21

Acknowledgement

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