AMS Working Group November 11, 2015

SanDisk, Milpitas, CA

Agenda

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Time Item 2:00 p.m. Opening Remarks

Dr. Abhijit Gupta, SanDisk 2:10 p.m. GSA Overview

Kole Giles, GSA 2:20 p.m. Thermal and Color-aware Reliability Verification

for Sub-16nm FinFET Designs Norman Chang, Ansys

3:00 p.m. Case Study of 16FF+ Half Power, Multi-Protocol SERDES Mahesh Tirupattur, Analog Bits

3:40 p.m. Working Group Deliverables Discussion 4:45 p.m. Logistics & Wrap-up

GSA OVERVIEW

GSA Mission

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Thermal and Color-aware Reliability Verification for Sub-16nm FinFET Designs

Norman Chang, Ansys Emerging FinFET designs at 10nm and below demand

advanced reliability verification including color-aware R/EM/ESD checking and the impact of device/wire selfheat on SoC/IPs. The transition from planar MOS to FinFET transistors typically increases the current density by 25% or more. The combination of higher current density, lower thermal conductivity of substrate and the 3-D narrow fin structure traps local heat causing thermally induced EM/ESD issues.

This presentation will discuss the newly developed color-aware, thermal reliability analysis platform based on RedHawk, Totem and PathFinder. The analysis uses measurement-based self-heat look-up and fast thermal coupling among wires. The talk will also describe thermal-aware reliability check applications for addressing upcoming challenges in sub-16nm FinFET designs.

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Case Study of 16FF+ Half Power, Multi-Protocol SERDES

Mahesh Tirupattur, Analog Bits 16nm enables complex SOCs with a lot of different

interface requirements. Providing concurrent support for multiple types of SERDES interfaces on the same device can save on design time and cost. Achieving low-power while also supporting these multiple standards can be a significant point of differentiation.

Moreover, proving layout flexibility with a variety of silicon orientations enables greater control of cost. This presentation will provide a case study of concurrently supporting PCIe Gen4 and HMC with the same multi-standard SERDES while enabling complete flexibility in orientation and cutting power in half.

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Project Ideas 1 of 3

Low Power Design Challenges - Proposal for a Whitepaper

Identify Power Hogs in IoT / Wearables application

Sensor Integration and Analog to Digital Conversion Challenges

Sub-Threshold Design Capability

Perspectives from: Foundry, OSAT, Fabless, IDM

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Project Ideas 2 of 3

PMIC and RF integration in IoT / Wearable designs - Proposal

Low Power, Low Voltage, Low Leakage requirements

Energy Harvesting Landscape

Advanced Packaging Requirements

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Project Ideas 3 of 3

Mixed Signal Model Transition – Proposal from previous meetings Seeing move away from BSIM models (predictive MOSFET

SPICE model)

HiSIM (HiSIM (Hiroshima-university STARC IGFET Model Family) one example Are there others gaining traction?

What other models exist, are in development, are in use

Generate overview and guidelines

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Meeting Theme and Project Ideas

Culture Clash In Analog (article excerpt) The analog/mixed signal world is being shaken up by a mix of new tools, an influx of younger engineers with new and broader approaches, and an emphasis on changing methodologies to improve time to market. Analog and digital engineers have never quite seen eye-to-eye. Analog teams leverage techniques that have been around, in some cases, for decades, while digital teams rely heavily on the latest technology available. While they have co-existed in mixed-signal environments, they have largely gone about their jobs independently. That is changing as a new generation of engineers enter the market, offering new approaches to design and creating disruptions within semiconductors and tool providers alike. “It’s the changing of the guard of the people who are designing electronics,” said Darrell Teegarden, mechatronics project manager in the SLE systemvision.com team at Mentor Graphics. He said there is a step-function changing happening now as a number of changes converge on design teams. “Engineers graduating today are a different breed than when we graduated,” Teegarden said. “What they expect, the way they work — all of these things are very very different, and that’s changing a lot of the dynamics both of the tool companies but also maybe more importantly for semiconductor companies. They have to be system engineers. The courses they are taking [in college] now are holistic. You don’t just focus on transistor design. The senior projects they are doing are entire systems of hardware and software and sensors and actuators. It’s stuff that connects with the Internet. They want to make self-driving cars as a senior project. Their ambitions are almost as ridiculous. They plot these amazing things because they don’t know any better and they have expectations to go with that. It’s that design perspective of whole systems, and then it’s also the expectation of how the world works, like stuff should be free. This is a challenge for companies. But that’s part of the disruption, and with disruption comes opportunity.” To understand where this is headed, and how it impacts analog modeling, it helps to look at where analog modeling is today.

http://semiengineering.com/culture-clash-in-analog/

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Analog / Mixed Signal Modeling Landscape

Propose a presentation on current modeling landscape, followed by a panel discussion based on below thoughts: Pure analog Verification, analog modeling refers very often to Verilog-A,

That was strictly for analog or RF — in the context of analog verification—and not meant for mixed signal.”

Extend the concept of analog modeling to mixed-signal, where you have a need to create a behavioral model for speed and accuracy, different standards were created. Verilog-AMS, which is a language including a mix of constructs from analog and digital.

Verilog-AMS model is parsed by a mixed-signal simulator, the design code is split internally into a digital portion to be handled by a digital event-driven simulator, and an analog portion to be handled by an analog circuit simulator. The result is typically performance speed-up with reasonable accuracy. Verilog-AMS has,

however, several limitations … Real Number Modeling provided the second generation of behavioral modeling - end result is a

considerable speed-up, but lower accuracy. This approach has been adopted for functional verification only but not for modeling high-

precision analog blocks. System Verilog nettype was created: it provides the required enhancements for modern mixed-signal

SoC verification (for example user-defined types that can hold one or more real values) so provides the same performance gain with more accuracy. However for all of those models, there is still a crucial need to validate those models versus their SPICE counterparts.”

Tool vendors have been working to understand these interactions and provide solutions. Mentor Graphics has its systemvision.com, which has analog/mixed signal sensors and actuators to leverage VHDL AMS. For Synopsys, it’s VCS-AMS. And for Cadence, it’s Virtuoso AMS Designer.

Along with the new standards work currently underway, the analog/mixed-signal design space is changing rapidly. Old is meeting new across the digital-analog divide, whether they want to or not.

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Meeting Theme and Project Ideas

Other possible meeting themes: PMIC and RF integration in IoT / Wearable designs

PMIC-RF, Wireless Charging, Wireless IP AMS / RF Tutorials targeted at future designers Foundry Trends, Node Usage; Applications Connectivity Trends HV-CMOS; III-V Compounds Integrated Voltage Regulator, Multiple Power Domain

Applications Memory Architectures: OTP, MTP, Flash Tutorials; NVM

Programmability

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2016 Planning

1Q16 Working Group Meeting Wednesday February 17th; 2pm – 5pm

Hosted by TBD

Theme: TBD

2Q16 Working Group Meeting

Wednesday May 18th; 2pm – 5pm

Hosted by TBD

Theme: TBD

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GSA Working Groups

Supply Chain – November 12th, ASE New Product Introduction; Big Data Analytics

GSA Annual Awards Dinner Thursday December 10th Quality – December 9th, SanDisk, Milpitas Quality Maturity Model – Supplier Change Management

MEMS - December 10th, Qualcomm MEMS Testing in a CMOS Environment

3D-IC – January 20th, Zuken Milpitas Modeling, Cooling, and Thermal Analysis

IP – January 21st, Rambus, Mountain View Advanced packaging impact on IP development

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