xilinx/exemplar logic fpga synthesis solution. leonardospectrum powerful integrated modular asic...
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Leonardo Spectrum Bundles
LeonardoInsight
FPGA OptimizationSingle Vendor
FPGA OptimizationMulti-Vendor
AdvancedOptimization
Control
Level 1
Level 2
Level 3
Giving you a choice!
Leonardo Spectrum User Interface
FlowTabs provide a step by step process
When the run button isn’t enough!
• PowerTabs offer easy access to advanced functionality
Leonardo Spectrum GUI
Synthesis Place and Route
Netlist
Timing
Scripts
Xilinx Alliance SeriesXilinx Alliance Series
LeonardoSpectrum
Automatically:• Transfers Constraints• Creates P & R Script File• Runs P & R
Xilinx Place and Route Integration
Part of FPGA Advantage
Includes all EDA Design Tools
Pushbutton Simulation, Synthesis and Place and Route
Provides Design Management
Cross probes to everything
One source for customer support
Pipeline Multipliers New in 1999.1G (now on ftp site)
Supported for Virtex
wait until clk'event and clk = '1';
temp1 <= a * b;
c <= temp1;
Multiplier Area Delay
Non-Pipelined 156 23.353
Pipelined 192 11.268
• area in slices• area and delay after place and route
Block RAM Inference (RAMB4_S1)
synchronous RAM is inferred as Block
ROMs are not inferred into Block RAM
Both single and Dual port RAMs are supported
Block RAMs include Timing arcs
Can be instantiated
Can infer distributed RAM blocks
1 Mega-bit Block RAM inferred in 20 seconds
Verilog Coding Example
module new_ram (clk, we, din, addr, dout);
input clk, we;
input [7:0] din;
input [4:0] addr;
output [7:0] dout;
reg [4:0] addri;
reg [7:0] data[0:31];
always @(posedge clk)
begin
if (we == 1’b1)
data[addr] = din;
addri = addr;
end
assign dout = data[addri];
endmodule
Coding Style requires both registered address and data signals
New in v1999.1F
Controlling Block RAM Inference
Disable RAM Inference Globally > set extract_ram FALSE
Prevent RAM inference on a single instance > Set_attribute i5 –name block_ram –value false Will not be implemented in slice RAM
RTL Verilog Comment Example
Reg [7:0] mem[63:0]//Exemplar attribute mem block_ram FALSE
Attribute must be set on the memory storage signal
Slice RAM Inference
Asynchronous RAMs use the CLB RAM element Subtracts from Logic resources Library cells include timing arcs
DLL Cell
Inserted through instantiation
CLK_DIVIDE and DUTY_CYCLE_CORRECTION attributes are propagated to Alliance Series as EDIF properties
DLL cell does not contain timing arcs Clock constraints must be set on internal nets
Set_attribute clk_internal –name clock_cycle –value 20 –net
BUFGDLL & BUFGDLLH Cells
Special configurations of DLL
Included in the library as a special type of clock buffer
Use PAD command PAD clk BUFGDLL (Appears on wrong pull-down list)
SRL Inference
New in 1999.1f release Turned on by Default
LUT can be used in place of registers to balance pipeline stages
Area Efficient Optimization
Controlled by 2 variables Set virtex_map_srl TRUE
– enables mapping Set virtex_map_srl_pack TRUE
– Packs SRL into single slice
SRL Example
Area (slices) Delay (Mhz)
previous flow 110 160
srl flow 16 185
% improvement 85% 16%
Area (slices) Delay (Mhz)
previous flow 110 160
srl flow 16 185
% improvement 85% 16%
begin
process (clk)
begin
if clk'event and clk = '1' then
int_sig <= input & int_sig(0 to cycle - 2);
end if;
end process;
output <= int_sig(cycle -1);
end behav;
Priority Encoders using MUXCY
Used for implementing fast priority encoders up to 10 levels
Available through a variable called map_muxcy (default:true) To disable issue the following command from the tcl window
> Set map_muxcy false
Also used for wide address decoders, wide AND gates with bubbled inputs.
Use for Alliance Series 2.1 and later
IOB Support
• Global IOB Register Inference
Set virtex_map_iob_registers variable to TRUE
Can be done through GUI on Technology form
Tristate Enable Register : Replicates registers for the Tristate pins of IO Bus for fast Tcko.
Replicates internal registers driving multiple output ports.
• Port by Port IOB Register Implementation
• Set the attribute “IOB” = true on a specific port
> set_attribute out_a –name IOB –value TRUE -port
Virtex Optimization - F5MUX & F6MUX
module mux81 (a, sel, o);input [0:7] a;input [0:2] sel;output o;assign o = a[sel];endmodule
Advanced Opt Settings F5 MUX Any function of 5 inputs or some decomposable
functions of upto 9 inputs.
F6 MUX Any function of 6 inputs or some decomposable
functions of upto 17 inputs Implements upto 8x1 Mux in one CLB.
MULTAND
Any multiplier with non-constant operands uses the MULTAND
module mult8x8 (a,b,prod);input [0:7] a;input [0:7] b;output [0:15] prod;assign prod = a * b;endmodule
Registers
Now inferring negative edge registers “_1” versions of cells, FD_1
Inferring synchronous set/reset flops
Inferring asynchronous set/reset flops > Set include_gates FDRS
Counters
All flavors of counters are implemented using 1 LUT per Bit.
Loadable Synchronous Set/Reset Up/Down Count enable and clock enables
Exception include Counter with “both” asynchronous and synchronous reset and load signals.
Hierarchy Schematics
Shows Entire Hierarchical Schematic at once
Default Schematic Hierarchy Schematic
Critical Path Highlighting
Both Filtered and Unfiltered viewsBoth Filtered and Unfiltered views
Constraints and Timing info displayed on Schematic
Constraints and Timing info displayed on Schematic
Interactive to Database
View connected to active database
Issue interactive commands such as group or don’t_touch
View automatically updated
View connected to active database
Issue interactive commands such as group or don’t_touch
View automatically updated
Creating Design Hierarchy
Use the Group Command
Will create new level of hierarchy
Original hierarchy will exist at lower level
Use to group area critical or timing critical blocks together
Can also group from the design browser
CBA
CB
A New
Group {b c} –inst new
Removing Design Hierarchy
Use the “ungroup” command
Will dissolve all hierarchy
Can be done from the design browser
CB
A New
ungroup {b c}
A New
Hierarchy Manipulation from Schematics
Hierarchy commands can be executed from schematic viewer Schematic will automatically update
Moving Within Hierarchy
Present_design command can “Swap” any module into the Optimizer
Can be used for re-optimization
Can be used to Separate Blocks
All hierarchy blocks can be set to “present_design
Issue command from Design Browser or Schematic Viewer
> Present_design priority_encoder
B
C
Top
A
Optimization
Engine
Module Optimization
Cannot be done through Quicksetup
Disable IO Insertion during optimization
Hierarchy may be flattened
Save netlist as “XDB” Exemplar Binary Database No netlist processing is performed
Optimize Form
Output Form
PCI Core Flow
PCI_TOP
UserBlock
CFGPCIM _LC
Timing Constraints
U ser des ign op tim izedsepa ra tly w ith tim ingcons tra in ts
P C I C ore "w rapper" files .Ins tan tia ted Log ic is le ft
unm od ified
Best PCI Core flow in the industry
No code modifications
Extensive hierarchy & IO buffer control
Can be 100% scripted for single pass optimization
Best PCI Core flow in the industry
No code modifications
Extensive hierarchy & IO buffer control
Can be 100% scripted for single pass optimization
New Appnote available at www.exemplar.com/support/appnotes
Team Design
Blocks optimized separately
Assembly done by Synthesis tool
IO Insertion, Design Analysis and Final Optimization done during synthesis
Optimize Block A Optimize Block B Optimize Block C
Read OptimizedSub-Blocks
HDL File A HDL File B HDL File C
Read Top-LevelStructural HDL
HDL FileTop
Dont_touchOptimized sub-
blocks
Insert IO andTop-Level
Optimization
W rite top-levelNetlist
New Appnote available at www.exemplar.com/support/appnotes
Incremental Place and Route
Preserved Hierarchy for Incremental Place and Route
LeonardoSpectrum supports Re-opt at block level
Use Guide Files to preserve place and route timing
Top
C
B
A
Top LevelEDIF Nelit
1st P lace andRoute Pass
2nd P lace andRoute Pass
Guide F ile
Block baseddesign change and
re-optim ization
Top LevelEDIF Netlist
LeonardoSpectrum Alliance Series
Full p lace androute run tim e
T im ingpreservation andim proved runtim es
HDL Code Change
New Appnote available at www.exemplar.com/support/appnotes
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