what can fpga designers do with personal data centers?

Cloud Computing for Chip Design

“What Can FPGA Designers Do With Personal Data Centers?”

Harnhua Ng, Plunify Pte Ltd October 14, 2011

Agenda

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§ FPGA Design Data Center § Specific Areas of Note

§ FPGA Timing Closure § Current Approach § Demonstration § Cloud Approach

§ Going Forward

“Personal Data Center for FPGA Design”

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Simulation

Routing/ Synthesis

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Confidentiality, Ease of Use Precedents: Foundry <-> foundry customer interaction

•  Secure and Encrypted End-to-End Transfers •  Plugins to Existing Tools •  Distributed File Uploads / Downloads

Audited Security Standards §  AES encryption

§  SSL transmission §  Asymmetric keys

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FPGA Timing Closure

“Timing Experiments”

§  Case 1: Miss timing by a bit

§  Change a setting, repeat till successful

§  Case 2 : Timing is way off

§  Back to drawing board – path restructuring, pipelining etc.

Drawbacks -  Takes time to re-iterate one at a time -  Usually at a later design stage -  Randomness: *Fingers crossed* -  Requires communication between “tools

people” and “design people”

Costly Delays

N hrs per iteration M iterations

Total: N x M hours

≈ days, weeks…

Current Limitations

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§  Run iterations in parallel §  Save time wasted from waiting for

each iteration

§  Save time on re-engineering the design

§  Use generated results from iterations to troubleshoot better

Data Center Approach

N hrs per iteration Total: N hours

X servers

Cloud Closure

Design – OR1200 32-bit processor core

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§ 32-bit RISC § Harvard architecture § 5-stage pipeline § Virtual memory § Basic DSP capabilities § Implemented in various

commercial ASICs & FPGAs

Target Chip & Software

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§ Altera Stratix III L50 § 65-nm technology § Logic elements: 47.5K § Package: F780 § Speed Grade: Commercial 2

§ Altera Quartus II § Version 10.0 SP1

Timing Problem

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Timing Aspect Slack (ns) Worst Setup Time -0.519

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•  Calculate various parameters §  “Seeds”

§  Placement optimizations

§  Routing optimizations

§  Register-to-register timing

§  Effort levels

§  Schedule and run in parallel

Run in Parallel

Multiple parallel runs

Cloud Approach

Result: Timing Solutions Found

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Set Timing Aspect Slack (ns) 19 Worst Setup Time 0.093 26 Worst Setup Time 0.011

Cloud Compile - Cloud Collab

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EDAxtend Platform

•  Sigasi HDT •  TransEDA

Design Entry

Complete design tool flow

Simulate

•  Aldec Riviera Pro •  Mentor Graphics Modelsim

Synthesis

•  Altera Quartus II

Place and

Route

•  Altera Quartus II

Timing/ Power

Analysis

•  Altera Quartus II

Design Rule

Checking

•  Magma •  Simucad

Cloud Explore Cloud Closure

Cloud Test

IP Libraries

§  Support more FPGA processes § IP cores § Complementary tasks e.g. multi-vendor flows

§  Extend features to broader EDA tasks § E.g. Simulator,

DFM, Verification tools

Next Steps

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§  Web account: register at www.plunify.com

§  Desktop plugin: contact us at tellus@plunify.com

§  What would you like to see in the cloud?

Test Drive & Feedback

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§  Secure, easy to use § Demo: Timing closure

§  Shorten Time-To-Market

§  Reduce overheads and development costs

Cloud-Accelerated FPGA Design

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