wavelet technologies · 2014. 1. 9. · wt-diplab-1.0 wavelet technologies © 2014 #2 wt-diplab-1.0...

WAVELET TECHNOLOGIES © 2014 #1WT-DIPLAB-1.0

WAVELET TECHNOLOGIESUnit No. 10, Plot No. 59, Amchi Colony

1, N. D. A. Road, Bawdhan, PUNE 411 021.

Phone : +91-20-22951983, 22951984, 22951985

Fax : +91-20-22951904

URL : www.waveletgroup.com

Contact : Dr. Vishwas Udpikar, Ph.D.

<vishwas.udpikar@waveletgroup.com>

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WT-DIPLAB-1.0(Digital Image Processing Laboratory)

- Team Wavelet

Introducing,

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Agenda:

• Presentation on WT-DIPLAB-1.0 details and capabilities

• Demo – Video processing library

WT-DIPLAB-1.0

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WT-DIPLAB-1.0

Camera LCD MonitorRS232USB

VGA Converter

Video Processor

WT-DSPPORT-V.1

Pattern Generator

WT-DSPPORT-V.1

Host PC-Via Hyper Terminal

CRT monitor

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WT-DSPPORT-V.1 Kit

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BF561 DSP Video Input / Outputs

IR Receiver

Ethernet

RTCFPGAPTZ interface (RS422/RS232)

SDRAM USB 2.0

LEDs

Joystick

ADuC812

WT-DSPPORT-V.1 Board

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Operation Mode Stand Alone

DSP Processor BlackFin BF561 @ 500 / 600 MHz, Dual Core

Micro-Controller ADuC 812 (Optional)

FPGA XC3S100 FPGA (Optional)

Memory On Board 256 MB SDRAM

Flash Memory On Board 2 MB Flash (Optional up to 8 MB)

SRAM 4 MB (Optional)

Analog Inputs 4 Channels to ADuC812 (Optional)

Analog Outputs 2 Channels from ADuC812 (Optional)

Video Input 1 channel (NTSC/PAL)

Video Output 2 channel (NTSC/PAL)

Keypad interface 16 keys (Optional)

Specifications

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Ethernet Interface 10/100 mbps on RJ45 connector (Optional)

Host Interfaces RS-232C/RS422 interface from DSP (Optional ADuC812)

Remote Interface IR remote interface (Optional)

RTC Battery backed up RTC (Optional)

Relay output 2 Relay outputs (Optional)

Expansion bus BlackFin DSP Address/Data Control bus (Optional)

Power requirement 12 VDC @ 1.5 A

Board size 172 mm x 212 mm

Operating Temp. 0C to 50C (Industrial grade)

Note: The Optional features on the Unit may vary as per Customer’s requirement.

Specifications (Cont.)

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Block Diagram

ADSP – BF561

Black-Fin

Dual Core Processor

Video In Video outVideo loop-out

Video Amplifier

SDRAM

128 MB

FLASH

2 MB

Video Encoder

ETHERNET

(Optional)

RELAY – 2 (Optional)

FPGA

(Optional)

USB 2.0

(Optional)

Video Amplifier

Video Decoder

LED Indications

ADuC 812 (Optional)

IR Receiver (Optional)

Keypad (Optional)

RTC (Optional)

RS 232 T / R

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Overview Camera Interface

Analog Video Out interface

PTZ Camera Interface

Alarm and Alarm over IP Interface

IR Remote Interface

Keyboard/Joystick Interface

PC Interface Over Ethernet

Interfaces

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ADSP – BF561 Architecture

Functional Block Diagram

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The ADSP-BF561 processor is a high performance member

of the Blackfin family of products targeting a variety of

multimedia, industrial and Telecom applications.

Features:

a)Dual symmetric 600 MHz high performance Blackfin cores

b)328K bytes of on-chip memory

c)Each Blackfin core includes: Two 16-bit MACs, two 40-bit ALUs, four 8-bit

video ALUs,

d)40-bit shifter

e)2 Parallel Peripheral Interfaces (PPIs)

f)2 Serial Ports (SPORTs)

g)Serial Peripheral Interface (SPI)

h)12 General-Purpose Timers

i)Universal Asynchronous Receiver Transmitter (UART)

j)2 Watchdog Timers

k)48 General Purpose I/O (Programmable Flags)

ADSP-BF561 Features

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BF561 Processor core

Blackfin processors support a modified Harvard architecture in combination

with a hierarchical memory structure.

Level 1 (L1) memories typically operate at the full processor speed with no

latency.

Level 2 (L2) memories are other memories, on-chip or off-chip, that may take

multiple processor cycles to access.

DATA PROGRAM

CONTROL UNIT

Program BusData Bus

The Harvard architecture

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BF561 memory architecture #1

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Off-chip memory is accessed through the External Bus Interface Unit (EBIU),

provides expansion with SDRAM, flash memory, and SRAM, optionally

accessing more than 768M bytes of physical memory.

The memory DMA controllers provide high bandwidth data movement

capability. They can perform block transfers of code or data between the

internal L1/L2 memories and the external memory spaces

BF561 memory architecture #2

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BF561 2D DMA Example

Start

X Count, X modify

Y Count, Y modify

Image cropping

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BF561 PPI Interface

The ADSP-BF561 provides two 16-bit Parallel Peripheral Interfaces (PPI0

and PPI1) that can connect directly to parallel A/D and D/A converters,

video encoders and decoders and other general purpose peripherals.

The Parallel Peripheral Interface (PPI) is a half-duplex, bidirectional port

accommodating up to 16 bits of data.

ADSP - BF561

Core A

L1 Memory

Core B

L1 MemoryVideo

Decoder

A/D

Video

Encoder

D/A

PPI0 PPI1

L2 Shared Memory

SDRAM

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How to write program

Analog Devices provides VisualDSP++® an easy-to-use integrated

software development and debugging environment (IDDE).

VisualDSP++ supports Analog Devices’ Blackfin® Processors, SHARC®

Processors, and TigerSHARC® Processors.

Operating systems Windows XP,® Windows 2000,® and Windows Vista®

are supported.

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Project Development stages

Emulator Pod WT-DSPPORT-V.1

Pod WT-DSPPORT-V.1

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Image viewer

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How to use

Power supply Connection to

PTZ

Emulator Pod

Video OutVideo In

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Typical Applications of WT-DSPPORT-V.1 board

• Video security system

• Video analytics

• Image Processing Lab

• Project Platform

Applications

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Applications developed on

WT-DSPPORT-V.1

• Single camera object tracking

• Motion tracking

• Trip wire

• Virtual Fence

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Single camera object tracking

WT-DSPPORT-V.1

Monitor

Pan Tilt

Zoom

(PTZ)

camera

IR Remote

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Single camera object tracking

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Motion Tracking

WG-DSPPORT-V.1

Monitor

Overview

camera

PTZ camera

Joystick

Server

IR Remote

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Motion tracking Single reference camera

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Tripwire

WG-DSPPORT-V.1

Monitor

Overview

camera

PTZ camera

Joystick

Server

IR Remote

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Tripwire

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Tripwire Video

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Virtual Fence

WG-DSPPORT-V.1

Monitor

Overview

camera

PTZ camera

Joystick

Server

IR Remote

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Virtual Fence Video

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WT-DSPPORT-V.1 Pattern Generator

Camera LCD MonitorRS232USB

VGA Converter

Video Processor

WT-DSPPORT-V.1Pattern Generator

WT-DSPPORT-V.1

Host PC-Via Hyper Terminal

CRT monitor

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WT-DSPPORT-V.1 Pattern Generator

• Bar

• Chequer

• Sine

• Gaussian Noise

• Add Gaussian noise

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Pattern Generator – Bar pattern

4 BARS

16 BARS

64 BARS

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Pattern Generator – Chequer pattern

4x4

10x10

50x50

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Pattern Generator – Sine pattern

Sine pattern

16 Cycles/512 pixels 32 Cycles/512 pixels

512 pixels 512 pixels

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Pattern Generator – Gaussian noise

Mean – 128, Std Dev - 0 Mean – 128, Std Dev - 8

Mean – 128, Std Dev - 16 Mean – 128, Std Dev - 32

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Pattern Generator – Add Gaussian Noise

Mean – 0, Std Dev - 0 Mean – 0, Std Dev - 8

Mean – 0, Std Dev - 16 Mean – 0, Std Dev - 32

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WT-DSPPORT-V.1 Video Processor

Camera LCD MonitorRS232USB

VGA Converter

Video Processor

WT-DSPPORT-V.1

Pattern Generator

WT-DSPPORT-V.1

Host PC-Via Hyper Terminal

CRT monitor

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WT-DSPPORT-V.1 Video Processor

List of functions in video processor

1. Live video

2. Negate

3. Horizontal flip

4. Vertical flip

5. Histogram display

6. Histogram stretching

7. Histogram equalization

8. Image statistics (Min, Max, Mean, Mean Square, Variance, Std Deviation, Entropy)

9. Global Threshold

10. Otsu Threshold

11. Dilation binary

12. Erosion binary

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WT-DSPPORT-V.1 Video Processor

List of functions in video processor (cont…)

13. Dilation grey

14. Erosion grey

15. Gamma correction

16. Mean filter

17. Median filter

18. Sharpening filter

19. Edge detection (Sobel operator)

20. Pseudo coloring

21. Region counting

22. FFT

23. Wavelet transform

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OutputInput

Video in out

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Video processing architecture

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OutputInput

Video processor - Negate

Mammogram of tissue

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OutputInput

Video processor – Horizontal flip

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OutputInput

Video processor – Vertical flip

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Video processor – Histogram display # 1

Bar pattern from WT-DSPPORT-V.1 pattern generator

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Video processor – Histogram display # 2

Bar pattern print in front of camera

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Video processor – Histogram display #3

Gaussian noise from WT-DSPPORT-V.1 pattern generator

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Video processor – Histogram Stretching

Image print in front of camera

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OutputInput

Histogram Equalization

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Video processor – Histogram Equalization

Image print in front of camera

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Video processor – Image Statistics #1

Gaussian noise from WT-DSPPORT-V.1 pattern generator

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Video processor – Image Statistics #2

Bar pattern from WT-DSPPORT-V.1 pattern generator

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OutputInput

Threshold - 150

Otsu Threshold

Video processor – Global/Otsu Threshold

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Video processor – Global/Otsu Threshold

Image print in front of camera

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Video processor –Otsu Threshold

Image print in front of camera

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Video processor –Morphological operations

Image print in front of camera

Dilation and Erosion

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Video processor – Gamma correction #1

Image print in front of camera

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Video processor – Gamma correction #2

Image print (noise) in front of camera

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OutputInput

Video Processor - Mean filter

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Output (Mean)Input

Video Processor - Mean & Median filter

Output (Median)

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Video Processor – Sharpening # 1

OutputInput

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Video Processor – Sharpening # 2

Image print in front of camera

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Video Processor - Edge Detection # 1

OutputInput

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Video Processor - Edge Detection # 2Image print in front of camera

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OutputInput

Video processor – Psuedo coloring

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Video Processor - Region Counting

Image print in front of camera

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Video processor – FFT

Image print in front of camera

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Video Processor - Wavelet Transform

Image print in front of camera

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Project kit WT-DSPPORT-V.1 also available

• Training Kit

• Project Kit

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Wavelet TechnologiesUnit No. 10, Plot No. 59, Amchi Colony

Survey No. 1, N. D. A. Road, Bawdhan, Pune 411021Phone +91-20-22951983/84/85, Fax +91-20-22951904

Info@waveletgroup.com

Thank You !