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April 2, 2001
AGB Programming ManualVersion 1.1
1999 - 2001 Nintendo of America Inc.
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AGB Programming Manual
©1999 - 2001 Nintendo of America Inc. D.C.N. AGB-06-0001-002B42
“Confidential”
This document contains confidential and proprietary informationof Nintendo and is also protected under the copyright laws ofthe United States and other countries. No part of this documentmay be released, distributed, transmitted or reproduced in anyform or by any electronic or mechanical means, includinginformation storage and retrieval systems, without permission inwriting from Nintendo.
1999 - 2001 Nintendo of America Inc.
TM and are trademarks of Nintendo
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AGB Programming Manual Introduction
©1999 - 2001 Nintendo of America Inc. 3 D.C.N. AGB-06-0001-002B4
Introduction
CHARACTER/BITMAP BG
MULTIPLAY COMMUNICATION
32768 COLORS
32BIT RISC CPU 16MHz
2.9" WIDE TFT COLOR
PCM STEREO SOUND
COLOR GRAPHIC EFFECTS
COMPATIBLE FOR CGB
Game Boy Advanced (AGB) stresses portability and focuses on 2D rather than 3D imageprocessing functions, resulting in a cutting-edge portable game device with revolutionarycapabilities.
It provides window-like functions, rotation, scaling, α blending, and fade-in/fade-outfeatures that can be combined to produce exactly the image representations desired.
Additionally, the bitmap image-rendering function, with its two modes (double bufferingmode for rewriting full-screen images in real time and single buffering mode for stills), canbe used to handle realistic images that are indistinguishable from actual photographs.
The 2.9-inch-wide reflective TFT color LCD screen provides a clear display with littleafterimage.
In addition to Game Boy Color compatible sound, AGB has a PCM stereo sound generator.Multiple tracks can be played simultaneously by overlapping them using the CPU. L and Rbuttons have been added to the Controller. The broader range of control provided alsoexpands the breadth of game designs possible.
Although AGB uses a 32-bit RISC CPU whose computing performance and data processingcapabilities far surpass those of Game Boy Color, it consumes little power, allowingapproximately 15 hours of continuous play. This is made possible by the inclusion of the varioustypes of RAM on a single custom chip.
Furthermore, software for AGB can be developed using the C language, minimizing thecost of development equipment. This favorable development environment and the highlevel of freedom of the system configuration allow one to build a profound world of play inwhich anyone can become absorbed.
With its extremely high-performance computational and data processing capabilities as afoundation, AGB provides greater image and sound representation capabilities, making thepursuit of fun its essential aim.
The purpose of this high level of performance is to bring unique game ideas fully to life.
AGB is an innovation born from experience. While providing backwards compatibility withthe enormous software resources available for the 100 million Game Boy units in useworldwide, it also breaks new ground for portable game devices.
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AGB Programming Manual Revision History
©1999 - 2001 Nintendo of America Inc. 4 D.C.N. AGB-06-0001-002B4
Revision HistoryVersion Date Description0.3.6.2 12/21/1999 -Minor modification. ( Numbering for items: P81,P82,P149),
(Reference to chapter removed)-Deleted 14.3
0.3.6.3 01/05/2000 -Minor modification.-Corrected BG Offset Registers diagrams-Corrected the diagrams of Registers for Setting the Direction Parameters of BG data.-Corrected diagram of the Sound 1 Duty Cycle.-Corrected the name of d05 bit for the DISPCNT Register.-Added the description of Bit map BG mode.-Corrected the SIO Timing Chart of Normal Serial Communication.-Changed the diagrams and descriptions of the Sound Control Registers.-Added the formula for calculating the number of OBJs that canbe displayed on 1 line.
0.4.0 01/25/2000
02/09/2000
-Changed specifications. *Changed CPU internal working RAM memory capacity, and
created CPU external working RAM. *Changed the bit structures of DMA control registers. *Deleted Infrared Communication functions. *Created the interrupt IME register, and changed the bit structures of IE and IF registers. *Changed the number of colors that can be displayed to 32,768. *Changed the specifications of Normal Serial Communication (Bit width, communication speed) *Changed the specifications of Multi SIO Communication (UART system). *Changed the center coordinate of OBJ Rotation to dot boundary. *Added UART system communication function.-Added the Complete Block Diagram.
0.4.1 02/22/2000
02/24/200002/25/2000
-Modified the description of Direct Sounds, and correctedregister R bit structure.-Added the PWM sampling cycle control function.-Changed the method to specify OBJ size.-Corrected misprints in the communication control register.
0.4.1.1 03/08/200003/10/2000
03/10/2000
-Added the description of ROM registration data.-Improved the description of interrupt and multiple interrupt process.-Improved the description of system call and multiple system call process.
0.4.1.2 04/06/2000 -Added the description of UART system communication.
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AGB Programming Manual Revision History
©1999 - 2001 Nintendo of America Inc. 5 D.C.N. AGB-06-0001-002B4
Version Date Description0.4.1.3 05/08/2000
05/16/2000
05/25/2000
-Corrected [Sound 1 Usage Notes].-In 1) Normal Communication of Communication Functions,mentioned not to use a cable.-Added the diagram of Multi Player AGB Game Link cableconnection.-Changed the diagram in System-Allocated Area in Working RAM,and deleted “(Tentative)”.-Revised ROM registration data.-Corrected the description of internal shift clock of normal SIOcontrol register.-Newly added the description of “AGB Game Link cable” in thechapter of Communication Functions.-Corrected Overview of Screen Sizes for Text BG Screens in“Rendering Functions”.
0.4.1.4 05/29/2000 -Added the description for the device type of ROM RegistrationData.-Corrected “Fault Function” to ”Halt Function.”-Corrected the diagram of “AGB Game Link cable.”
0.4.1.5 06/01/2000 -Corrected the attributes of timer setting values register from Wto R/W.-Added one sentence to 1) of 15.2.1. Normal Interrupt and 15.2.2.Multiple Interrupts respectively.-Emphasized the prohibition of use of cable for normal SIOcommunication.
0.4.1.6 06/26/2000 -Modified the connection diagram of the multi-play cable.-Added the transition diagram of the multi-play communicationdata.-Modified the description of "16-Bit Multi-play Communication".
0.4.1.7 08/10/2000 -Modified the description of an error flag for the multi=playcontrol register.-Modified the description of a valid flag for all the DMA controlregisters.-Added the number of transfer when 0 is set for the DMA wordcount register.
0.4.1.8 10/16/2000 -Added cautions to the priority setting of OBJ.-Added a description and cautions to Sound 1,2,3, and 4.-Added the description to "Mapping of character data".-Revised the description in SIOCNT[d14] and [06] of UARTcommunication register.-Revised the connection diagram of 16 bit multi-playcommunication.-Added a description to all sound operation modes of the soundcontrol register.-Revised the itemized description of Chapter 10 "Sound".
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AGB Programming Manual Revision History
©1999 - 2001 Nintendo of America Inc. 6 D.C.N. AGB-06-0001-002B4
Version Date Description1.0 12/01/2000 -Deleted the checksum of ROM registration data and revised the
diagram.-Revised the diagram for "AGB Game Link Cable" in the "CommunicationFunction".-Revised the number of DMG sold from tens of millions to a hundredmillion in the introduction of AGB.-Revised the hours you can play continuously from "about 20 hours" to"about 15 hours".-Revised the illustrations of the AGB hardware and the Multi Player AGBGame Link cable in the multi play communication diagram.-Added the description of the timing chart for normal SIO communication.-Added a caution in the DMA valid flag of all the DMA control registers.-Added a caution in the master start bit of the multi-play control register.-Revised the multi-play timing chart.-Revised the memory map for system reserve area in the work RAM.-Added a caution to "Communication Function".-Revised the first sentence in "UART Communication". Added "Relationbetween Data register, FIFO and Shift register".-Revised the expression of [Cautions] to a more specific expression[Cautions for ~~].-Added a description of X coordinate and Y coordinate for OAM. Addedthe diagram to Y coordinate.-Revised the description of the pre-fetch buffer flag in the Game Pakmemory wait control register.-Added cautions to the description of the input/output select flag in the Rregister of general communication.
1.01 2/01/2001 -Modified the description of pin 31 in the Game Pak bus.-Revised the cancel conditions for the Stop function in the power-downmode.-Added additional descriptions and cautions for the initialization flag ofSound 1.
1.02 2/13/2001 -Modified the description of "8-Bit/32-Bit Normal Communication Function"summary in "Communication" chapter.-Added a paragraph to "Selecting Communication Function" in"Communication" chapter.
1.04 3/1/2001 -Specified the method to control the OBJ display individually in the description of the double size flag and the rotation/scaling flag for OAM attribute 0.-Added the description of display synchronization DMA to DMA3.-Added the description of the DMA problem and how to avoid it at the endof the chapter on DMA.*Added the restrictions to the description of the repeat flag in DMA3.*Updated the timing chart and the cable connection diagram for the multi-play communication.*Revised the description of the normal serial communication cautions.
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AGB Programming Manual Revision History
©1999 - 2001 Nintendo of America Inc. 7 D.C.N. AGB-06-0001-002B4
1.1 4/2/2001 - Changed the picture in the AGB introduction in the beginning paragraph.- Added a caution regarding clearing of IME and IE in the chapter "Interrupt Control".- Added additional description of an error flag and ID flag for multi-play communication. - Added additional description of communication error flag of multi-play communication control register. - Modified the host side example in the description of JOY bus communication from NUS to DOL. Added DOL to the abbreviation in "Using This Manual". - Modified the SIO timing chart for normal serial communication.- Revised the number of colors from 256 to 32,768 in thedescription of Display Synchronization DMA of DMA3. - Modified the description of general purpose communication mode. - Revised the caution for normal serial communication. - Revised the caution for communication function.- Revised the summary of normal serial communication in the communication function chapter, and added additional description. - Added additional description in the caution for the selection of communication function in the communication function chapter. - Emphasized that unless general purpose communication mode, the cancellation condition SIO for System Call Stop will not work. - Changed LPU to LCD controller in system calls Halt and Stop. - Deleted the first item in Sound 3 Usage Note.- Changed the names of following registers according to header files provided by Nintendo. --Wait Control-- 204h WSCNT àà WAITCNT --Color Special Effects-- 050h BLDMOD àà BLDCNT 052h COLEV àà BLDALPHA
054h COLY àà BLDY
--Sound Related-- 080h~ SGCNT0_(L H) àà SOUNDCNT_(L H) ** Combined multiple names 084h SGCNT1 àà SOUNDCNT_X
088h SG_BIAS àà SOUNDBIAS
060h~ SG10_(L H) àà SOUND1CNT_(L H) **
064h SG11 àà SOUND1CNT_X
068h SG20 àà SOUND2CNT_L
06Ch SG21 àà SOUND2CNT_H
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AGB Programming Manual Revision History
©1999 - 2001 Nintendo of America Inc. 8 D.C.N. AGB-06-0001-002B4
074h SG31 àà SOUND3CNT_X
078h SG40 àà SOUND4CNT_L
07Ch SG41 àà SOUND4CNT_H
090h~ SGWR(0-3)_L àà WAVE_RAM(0-3)_L **
092h~ SGWR(0-3)_H àà WAVE_RAM(0-3)_H **
0A0h~ SG_FIFOA_(L H) àà FIFO_A_(L H) ** 0A4h~ SG_FIFOB_(L H) àà FIFO_B_(L H) **
--DMA Related-- 0B0h~ DM(0-3)SAD_L àà DMA(0-3)SAD_L **
0B2h~ DM(0-3)SAD_H àà DMA(0-3)SAD_H **
0B4h~ DM(0-3)DAD_L àà DMA(0-3)DAD_L **
0B6h~ DM(0-3)DAD_H àà DMA(0-3)DAD_H **
0B8h~ DM(0-3)CNT_L àà DMA(0-3)CNT_L **
0Bah~ DM(0-3)CNT_H àà DMA(0-3)CNT_H **
--Timer Related-- 100h~ TM(0-3)D àà TM(0-3)CNT_L **
102h~ TM(0-3)CNT àà TM(0-3)CNT_H **
--Communication Related-- 134h R àà RCNT
128h SCCNT_L àà SIOCNT
12Ah SCCNT_H àà SIODATA8 (Normal serial, UART communication)
SIOMLT_SEND (Multi-play communication)
120h SCD0 àà SIODATA32_L (Normal serial communication)
SIOMULTI0 (Multi-play communication)
122h SCD1 àà SIODATA32_H (Normal serial communication)
SIOMULTI1 (Multi-play communication)
124h~ SCD(2 3) àà SIOMULTI(2 3) **
140h HS_CTRL àà JOYCNT
158h JSTAT àà JOYSTAT
150h~ JOYRE_(L H) àà JOY_RECV_(L H) **
154h~ JOYTR_(L H) àà JOYTRANS_(L H) **
--Key Related--130h P1 àà KEYINPUT
132h P1CNT àà KEYCNT
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AGB Programming Manual Table of Contents
©1999 - 2001 Nintendo of America Inc. 9 D.C.N. AGB-06-0001-002B4
Table of Contents
1 AGB SYSTEM .....................................................................................131.1 SYSTEM OVERVIEW .....................................................................................................13
2 SYSTEM CONFIGURATION..............................................................152.1 CPU BLOCK DIAGRAM ...............................................................................................15
2.2 COMPLETE BLOCK DIAGRAM .....................................................................................16
2.3 MEMORY CONFIGURATION AND ACCESS WIDTH .......................................................17
2.4 LITTLE-ENDIAN ............................................................................................................17
3 AGB MEMORY ....................................................................................183.1 OVERALL MEMORY MAP .............................................................................................18
3.2 MEMORY CONFIGURATION ..........................................................................................193.2.1 AGB Internal Memory .................................................................................................193.2.2 Game Pak Memory ....................................................................................................20
3.3 GAME PAK MEMORY WAIT CONTROL ........................................................................213.3.1 Access Timing...........................................................................................................233.3.2 Game Pak Bus ..........................................................................................................24
4 LCD.......................................................................................................254.1 LCD STATUS...............................................................................................................26
4.1.1 V Counter..................................................................................................................264.1.2 General LCD Status ...................................................................................................27
5 IMAGE SYSTEM...............................................................................295.1 BG MODES ..................................................................................................................31
5.1.1 Details of BG Modes ..................................................................................................315.1.2 VRAM Memory Map...................................................................................................32
6 RENDERING FUNCTIONS...............................................................336.1 CHARACTER MODE BG (BG MODES 0-2)..................................................................33
6.1.1 BG Control ................................................................................................................336.1.2 Mosaic Size ..............................................................................................................396.1.3 VRAM Address Mapping of BG Data............................................................................406.1.4 Character Data Format ..............................................................................................426.1.5 BG Screen Data Format .............................................................................................436.1.6 BG Screen Data Address Mapping for the LCD Screen..................................................456.1.7 BG Rotation and Scaling Features ...............................................................................496.1.8 BG Scrolling ..............................................................................................................52
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AGB Programming Manual Table of Contents
©1999 - 2001 Nintendo of America Inc. 10 D.C.N. AGB-06-0001-002B4
6.2 BITMAP MODE BGS (BG MODES 3-5).......................................................................536.2.1 BG Control ................................................................................................................536.2.2 BG Rotation/Scaling...................................................................................................546.2.3 Pixel Data .................................................................................................................546.2.4 Pixel Data Address Mapping for the LCD Screen...........................................................55
6.3 OBJ (OBJECT).............................................................................................................586.3.1 OBJ Function Overview .............................................................................................586.3.2 Character Data Mapping .............................................................................................606.3.3 OAM.........................................................................................................................626.3.4 OBJ Rotation/Scaling Feature .....................................................................................70
6.4 DISPLAY PRIORITY OF OBJ AND BG.........................................................................72
7. COLOR PALETTES...........................................................................737.1 COLOR PALETTE OVERVIEW ......................................................................................73
7.2 COLOR PALETTE RAM ...............................................................................................74
7.3 COLOR DATA FORMAT................................................................................................76
8 WINDOW FEATURE............................................................................778.1 WINDOW POSITION SETTING......................................................................................77
8.2 WINDOW CONTROL .....................................................................................................78
9 COLOR SPECIAL EFFECTS ..........................................................809.1 SELECTION OF COLOR SPECIAL EFFECTS ................................................................80
9.2 COLOR SPECIAL EFFECTS PROCESSING...................................................................82
10 SOUND ...............................................................................................8410.1 SOUND BLOCK DIAGRAM .........................................................................................84
10.2 DIRECT SOUNDS A AND B ........................................................................................85
10.3 SOUND 1 ....................................................................................................................87
10.4 SOUND 2 ....................................................................................................................91
10.5 SOUND 3 ....................................................................................................................93
10.6 SOUND 4 ....................................................................................................................97
10.7 SOUND CONTROL....................................................................................................100
10.8 SOUND PWM CONTROL .........................................................................................104
11 TIMER...............................................................................................106
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AGB Programming Manual Table of Contents
©1999 - 2001 Nintendo of America Inc. 11 D.C.N. AGB-06-0001-002B4
12 DMA TRANSFER ............................................................................10812.1 DMA 0 .....................................................................................................................109
12.2 DMA 1 AND 2 ..........................................................................................................113
12.3 DMA 3 ....................................................................................................................117
12.4 DMA 4 ....................................................................................................................122
13 COMMUNICATION FUNCTIONS ..................................................12513.1 8-BIT/32-BIT NORMAL SERIAL COMMUNICATION ................................................128
13.2 16-BIT MULTI-PLAYER COMMUNICATION ..............................................................134
13.3 UART COMMUNICATION FUNCTIONS ....................................................................142
13.4 GENERAL PURPOSE COMMUNICATION...................................................................148
13.5 JOY BUS COMMUNICATION ...................................................................................150
13.6 AGB GAME LINK CABLE.........................................................................................154
14 KEY INPUT ......................................................................................15514.1 KEY STATUS............................................................................................................155
14.2 KEY INTERRUPT CONTROL......................................................................................15514.2.1 Interrupt Conditions...................................................................................................156
15 INTERRUPT CONTROL.................................................................15715.1 SYSTEM-ALLOCATED AREA IN WORK RAM..........................................................159
15.2 INTERRUPT OPERATION...........................................................................................16015.2.1 Normal Interrupt........................................................................................................16015.2.2 Multiple Interrupts.....................................................................................................161
16 POWER-DOWN FUNCTIONS ........................................................16316.1 STOP FUNCTION......................................................................................................163
16.2 HALT FUNCTION......................................................................................................164
17 AGB SYSTEM CALLS ...................................................................16517.1 SYSTEM CALL OPERATION.....................................................................................165
17.1.1 Normal Calls ............................................................................................................16517.1.2 Multiple Calls ...........................................................................................................167
18 ROM REGISTRATION DATA........................................................170
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AGB Programming Manual Using This Manual
©1999 - 2001 Nintendo of America Inc. 12 D.C.N. AGB-06-0001-002B4
Using This Manual
Important terms and symbols used in this manual are defined below.
1. Terms
The term “user” in this manual refers to the software developer, not to the general consumer.
Bit lengths in this manual are expressed as follows.
Bit Length Term Used8 bits byte16 bits half-word32 bits word
2. Symbols
The attributes of bits used in bit operations are represented as follows.
3. Abbreviations
Nintendo's game hardware is abbreviated as follows:
Ø DMG (Game Boy)Ø CGB (Game Boy Color)Ø AGB (Game Boy Advance)Ø DOL (Nintendo GameCube)
Read/write bitA readable and writable bit.
Read-only bitA bit that is readable but notwritable.
Write-only bitA bit that is not readable butis writable.
Fixed-value bitMust be set to aspecified fixed value.
1
Unrestricted bitCan be set to either 0 or 1.
Not used
*
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AGB Programming Manual AGB System
©1999 - 2001 Nintendo of America Inc. 13 D.C.N. AGB-06-0001-002B4
1 AGB System
1.1 System Overview
AGB is a portable game device that maintains downward compatibility with Game BoyColor (CGB) and provides higher performance.
AGB’s 2.9-inch-wide reflective TFT color LCD and 32-bit RISC CPU enable productionof games that match or surpass the Super Nintendo Entertainment System (SuperNES) in performance.
AGB CPU
32-bit RISC CPU (ARM7TDMI)/16.78 MHz
Downward Compatibility with CGB
Integral 8-bit CISC CPU for compatibility(However, it cannot operate at the same time as the AGB CPU.)
Memory
System ROM 16 Kbytes (and 2 Kbytes for CGB System ROM)Working RAM 32 Kbytes + CPU External 256 Kbytes (2 wait)VRAM 96 KbytesOAM 64 bits x 128Palette RAM 16 bits x 512 (256 colors for OBJ ;
256 colors for BG)Game Pakmemory
Up to 32 MB: mask ROM or flash memory(&EEPROM)
+Up to 512 Kbits: SRAM or flash memory
Display
240 x 160 x RGB dots32,768 colors simultaneously displayableSpecial effects features (rotation/scaling, α blending, fade-in/fade-out, and mosaic)4 image system modes
Operation
Operating keys (A, B, L, R, START, SELECT, and Control Pad)
Sound
4 sounds (corresponding to CGB sounds) + 2 CPU direct sounds (PCM format)
Communication
Serial communication (8 bit/32 bit, UART, Multi-player, General-purpose, JOY Bus)
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AGB Programming Manual AGB System
©1999 - 2001 Nintendo of America Inc. 14 D.C.N. AGB-06-0001-002B4
Game Pak
Like DMG and CGB, AGB is equipped with a 32-pin connector for Game Pakconnection. When a Game Pak is inserted, AGB automatically detects its type andswitches to either CGB or AGB mode.
The following Game Paks operate on the AGB system.
1. DMG Game Paks, DMG/CGB dual mode Game Paks, and CGB dedicated GamePaks
2. AGB dedicated Game Paks(Game Paks that only function with AGB)
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AGB Programming Manual System Configuration
©1999 - 2001 Nintendo of America Inc. 15 D.C.N. AGB-06-0001-002B4
2 System Configuration
2.1 CPU Block Diagram
ARM7TDMICPU
(16.78MHz)
Game Pak I/F
(Prefetch Buffer)
INTControl
WRAM(32KByte)
DMAC(4ch)
Timer(4ch)
SIO
SOUND(CGBcompatible + PWM)
VRAM_A(64KByte)
VRAM_B(16KByte)
VRAM_C(16KByte)
Special Color Processing Circuit
BitmapMode
RGB(5:5:5)
32
32
32
32
32
32
32
32
32
32
16
16 16
16 16
16
16
16
16
16
16
R:16/32W:16/32
R:8/16/32
* "R:8/16/32" and "W:8/16/32" mean that you canaccess an area of 8bits/16bits/32bits when readingand writing, respectively.
ROM(16KByte)
Palette RAM(16bit x 512)
Priority Evaluation Circuit
OBJ Processing Circuit
OAM(64bit x 128)
BG Processing Circuit
R:8/16/32W:8/16/32
32
32
R:8/16/32W:8/16/32
R:8/16/32W:8/16/32
R:8/16/32W:8/16/32
R:8/16/32W:8/16/32
R:8/16/32W:8/16/32
R:16/32W:16/32
KEYControl
R:16/32W:16/32
3216
Game Pak
CPU
R:16/32W:16/32
LCD Unit
EXT. WRAM(256KByte)
16(2 Wait)
R:8/16/32W:8/16/32
16
16
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AGB Programming Manual System Configuration
©1999 - 2001 Nintendo of America Inc. 16 D.C.N. AGB-06-0001-002B4
2.2 Complete Block Diagram
General Purpose BusMemory Space32KByte Max.
Power 5V
DMG/CGB Game Pak
RG
B
Regulator IC
General PurposeBus Memory Space
64KByte Max.AD Bus Memory
Space32MByte Max.
Power 3.3V
AGB Game Pak(AGB Only)
CPU External WRAM256KByte16bit Bus
Controller
Game Pak ShapeDetection Switch
SoundAmp
SoundVolume
SpeakerHeadphone
Jack
6Pin-EXPSIO
Communi-cation
InfraredCommuni
-cationAdaptor,
etc.
CPU
2wait
8/32bit SIOGeneral Purpose
Port
Multi-SIOUARTJOY
AGB Unit
LCD Module
4.194MHz(System 16.78MHz)
AB
SELECT START
RL
5V(DMG/CGB)3.3V(AGB)
Sw
itch
Be
twe
en
AD
Bu
s/G
en
era
l Pu
rpo
se B
us
Game Pak Power3.3V(AGB)/5V(DMG/CGB)Gane Pak
ExternalUnit
3.3V/5VVoltage
DetectionCircuit
AA Alkaline Battery
AA Alkaline Battery
Power Switch
DC-DC Converterand Regulator
13.6V5V3.3V2.5V-15V
VRAM98KByte16bit Bus
CPU Internal WRAM32KByte32bit Bus
AGB 32bitCPU Core
ARM7TDMI
CGB 8bitCPU Core
AGB System ROM16KByte32bit Bus
Peripheral Circuit(SOUND, DMA, TIMER, I/O, etc)
Prefetch Buffer16bit x 8
LCD Controller
CGB System ROM2KB
2.9"Reflective TFT Color LCD
240 x 160 x RGB Dot32,768 Colors Displayable
LCD DriverLCD Driver LCD Driver
LC
D D
rive
r
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AGB Programming Manual System Configuration
©1999 - 2001 Nintendo of America Inc. 17 D.C.N. AGB-06-0001-002B4
2.3 Memory Configuration and Access Width
DMA CPUMemory Type
BusWidth Read
WidthWriteWidth
ReadWidth
WriteWidth
OAM 32 16/32 16/32 16/32 16/32
Palette RAM 16 16/32 16/32 16/32 16/32
VRAM 16 16/32 16/32 16/32 16/32
CPU Internal Working RAM 32 16/32 16/32 8/16/32 8/16/32
CPU External Working RAM 16 16/32 16/32 8/16/32 8/16/32
Internal registers 32 16/32 16/32 8/16/32 8/16/32
Game Pak ROM(Mask ROM, Flash Memory)
16 16/32 16/32 8/16/32 16/32
Game Pak RAM(SRAM, Flash Memory)
8 -- -- 8 8
Good execution efficiency is obtained when programs that operate from the Game Pakuse 16-bit instructions (16-bit compiler), and those that operate from CPU InternalWorking RAM use 32-bit instructions (32-bit compiler).
2.4 Little-Endian
In the AGB CPU, memory addresses are allocated in 8-bit increments, and little-endian format is used in implementing the 8-, 16-, and 32-bit access widths.
A
B
C
D
0000h
0001h
0002h
0003h
Memory Register
ABCD
d31 d24 d23 d16 d15 d08 d07 d00
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AGB Programming Manual AGB Memory
©1999 - 2001 Nintendo of America Inc. 18 D.C.N. AGB-06-0001-002B4
3 AGB Memory
3.1 Overall Memory MapThe following is the overall memory map of the AGB system.
System ROM(16 Kbytes)
OAM(1 Kbyte)
VRAM(96 Kbytes)
Palette RAM(1 Kbyte)
CPU Internal Working RAM(32 Kbytes)
Game Pak RAM(0 - 512 Kbits)
Game Pak ROMWait State 2
(32 MB)
Game Pak ROMWait State 1
(32 MB)
Game Pak ROMWait State 0
(32 MB)Game Pak Memory
AGB InternalMemory
Images0E000000h
0C000000h
0A000000h
08000000h
07000000h
06000000h
05000000h
04000000h
02000000h
00000000h
Flash Memory(1 Mbit)
Mask ROM(255 Mbits)
Flash Memory(1 Mbit)
Mask ROM(255 Mbits)
Flash Memory(1 Mbit)
Mask ROM(255 Mbits)
00003FFFh
0203FFFFh
050003FFh
06017FFFh
070003FFh
0FFFFFFFh
0E00FFFFh
09FFFFFFh
0BFFFFFFh
0DFFFFFFh
CPU External Working RAM(256 Kbytes)
03000000h
03007FFFh
ROM
RAM
Image Area
Unused Area
I/O, Registers
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AGB Programming Manual AGB Memory
©1999 - 2001 Nintendo of America Inc. 19 D.C.N. AGB-06-0001-002B4
3.2 Memory Configuration
In broad terms, the area 00000000h-07FFFFFFh is allocated as AGB internal memory,and 08000000-0EFFFFFFh is allocated as Game Pak memory.
3.2.1 AGB Internal Memory
1) System ROM
The 16 KBytes from 000000000h is the system ROM.
Various types of System Calls can be used.
2) CPU External Working RAM
The 256 Kbytes from 02000000h is CPU External Working RAM. Itsspecifications are 2 Wait 16 bit Bus.
3) CPU Internal Working RAM
The 32 Kbytes from 03000000h is CPU Internal Working RAM. It is used tostore programs and data.
4) I/O and Registers
This area is used for various registers.
5) Palette RAM
The 1 Kbyte from 05000000h is palette RAM. It is used to assign palettecolors.
6) VRAM
The 96 Kbytes from 06000000h is the VRAM area. This area is for BG andOBJ data.
7) OAM
The 1 Kbyte from 07000000h is Object Attribute Memory (OAM). It holdsthe objects to be displayed and their attributes.
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AGB Programming Manual AGB Memory
©1999 - 2001 Nintendo of America Inc. 20 D.C.N. AGB-06-0001-002B4
3.2.2 Game Pak Memory
1) Game Pak ROM
Three 32 MB Game Pak ROM spaces are allocated to the area beginningfrom 08000000h.
The access speed of each of these spaces can be set individually. Thus,they are named Wait State 0, Wait State 1, and Wait State 2.
This specification enables memory of varying access speeds in Game PakROM to be accessed optimally.
The base addresses of the 3 spaces are 08000000h for Wait State 0,0A000000h for Wait State 1, and 0C000000h for Wait State 2.
In addition, the upper 1 Mbit of each space is allocated as flash memory.
This area is used primarily for saving data.
2) Game Pak RAM
The area beginning from 0E000000h is the Game Pak RAM area. Up to512 Kbits of SRAM or Flash Memory can be stored here. However, it is an8 bit data bus. Due to the specifications, any Game Pak device other thanROM must be accessed using Nintendo's library.
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AGB Programming Manual AGB Memory
©1999 - 2001 Nintendo of America Inc. 21 D.C.N. AGB-06-0001-002B4
3.3 Game Pak Memory Wait Control
Although the 32 MB Game Pak memory space is mapped to the area from 08000000honward, the 32 MB spaces beginning from 0A000000h and 0C000000h are images ofthe 32 MB space that starts at 08000000h.
These images enable memory to be used according to the access speed of the GamePak memory (1-4 wait cycles).
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
WAITCNT204h 0000hR/W
Address Register AttributesInitialValue
Game Pak RAMWait Control
Wait State 0Wait Control
Wait State 1Wait Control
Wait State 2Wait Control
PHI Terminal Output Control00: No Output01: 4.19 MHz clock10: 8.38 MHz clock11: 16.76 MHZ clock
Prefetch Buffer Flag0: Disabled1: Enabled
Game Pak Type Flag
WAITCNT [d15] Game Pak Type Flag
The System ROM uses this.
WAITCNT [d14] Prefetch Buffer Flag
When the Prefetch Buffer Flag is enabled and there is some free space,the Prefetch Buffer takes control of the Game Pak Bus during the timewhen the CPU is not using it, and reads Game Pak ROM data repeatedly.When the CPU tries to read instructions from the Game Pak and if it hitsthe Prefetch Buffer, the fetch is completed with no wait in respect to theCPU. If there is no hit, the fetch is done from the Game Pak ROM andthere is a wait based on the set wait state.
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AGB Programming Manual AGB Memory
©1999 - 2001 Nintendo of America Inc. 22 D.C.N. AGB-06-0001-002B4
If the Prefetch Buffer Flag is disabled, the fetch is done from the Game PakROM. There is a wait based on the wait state associated with the fetchinstruction to the Game Pak ROM in respect to the CPU.
WAITCNT [d12 - 11] PHI Terminal Output Control
Controls the output from the PHI terminal. This should always be set to00(No Output).
WAITCNT [d10 - 08],[d07 - 05],[d04 - 02] Wait State Wait Control
Individual wait cycles for each of the three areas(Wait States 0-2) thatoccur in Game Pak ROM can be set. The relation between the wait controlsettings and wait cycles is as follows. Use the appropriate settings for thedevice you are using.
Wait Cycles2nd Access
Wait Control Value1st Access Wait State
0
Wait State
1
Wait State
2
000 4 2 4 8001 3 2 4 8010 2 2 4 8011 8 2 4 8100 4 1 1 1101 3 1 1 1110 2 1 1 1111 8 1 1 1
After executing the System ROM (when the User Program is started) the WaitControl Value is 000. In the Game Pak Mask ROM used with the actualmanufactured product, the specifications are 1st Access/3 Wait, 2nd Access/1 Wait.In this case, set the Wait Control Value to 101.
WAITCNT [d01 - 00] Game Pak RAM Wait Control
Wait cycles for the Game Pak RAM can be set. The relation between thewait control settings and wait cycles is as follows. Use the appropriatesettings for the device you are using.
Wait Control Value Wait Cycles00 401 310 211 8
Nintendo America
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AGB Programming Manual AGB Memory
©1999 - 2001 Nintendo of America Inc. 23 D.C.N. AGB-06-0001-002B4
3.3.1 Access Timing
The following timing charts illustrate Game Pak ROM access with 3 waitcycles on the first access and 1 wait cycle on the second.
1) Sequential Access
1st Access(3 wait cycles)
2nd Access(1 wait cycle)
3rd Access(1 wait cycle)
System Clock16.78 MHz
Wait Cycles
AD Bus
wait wait wait
Address Data Data
wait
Data
wait
2) Random Access
1st Access(3 wait cycles)
1st Access(3 wait cycles)
System Clock16.78 MHz
Wait Cycles
AD Bus
wait wait wait
Address Data
wait
Data
waitwait
Address
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AGB Programming Manual AGB Memory
©1999 - 2001 Nintendo of America Inc. 24 D.C.N. AGB-06-0001-002B4
3.3.2 Game Pak BusThe Game Pak bus has a total of 32 terminals, which are described in the following table.
Game Pak ROM Access Game Pak RAM AccessNo.
Terminal Use Terminal Use1 VDD(3.3V) VDD(3.3V)2 PHI PHI3 /WR Write Flag /WR Write Flag4 /RD Read Flag /RD Read Flag5 /CS ROM Chip Selection /CS6 AD0 A07 AD1 A18 AD2 A29 AD3 A3
10 AD4 A411 AD5 A512 AD6 A613 AD7 A714 AD8 A815 AD9 A916 AD10 A1017 AD11 A1118 AD12 A1219 AD13 A1320 AD14 A1421 AD15
Terminals used forboth address(lower)and data
A15
Address
22 A16 D023 A17 D124 A18 D225 A19 D326 A20 D427 A21 D528 A22 D629 A23
Address(upper)
D7
Data
30 /CS2 /CS2 RAM Chip Selection
31IREQ and
DREQTerminal used for IREQ
and DREQIREQ andDREQ
Terminal used for IREQand DREQ
32 GND GND
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AGB Programming Manual LCD
©1999 - 2001 Nintendo of America Inc. 25 D.C.N. AGB-06-0001-002B4
4 LCDAGB uses a 2.9-inch-wide reflective TFT color LCD screen.
The vertical blanking interval of AGB is longer than that of DMG and CGB, and its horizontalblanking interval is fixed.
HorizontalBlank
VerticalBlank
DisplayScreen
308 dots
240 dots
160 lines
228 lines
(16.212µs)
(4.994ms)
Item Value IntervalDisplayscreen size
Number of dots perhorizontal line
240 dots 57.221 µs
Number ofhorizontal lines
160 lines 11.749 ms
Total numberof dots
Number of dots perhorizontal line
308 dots 73.433 µs
Number ofhorizontal lines
228 lines 16.743 ms
Blanking Number of dots perhorizontal blank
68 dots 16.212 µs
Number ofhorizontal lines pervertical blank
68 lines 4.994 ms
H interval frequency 13.618 KHz 73.433 µsScanningcycle V interval frequency 59.727 Hz 16.743 ms
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AGB Programming Manual LCD
©1999 - 2001 Nintendo of America Inc. 26 D.C.N. AGB-06-0001-002B4
4.1 LCD Status
4.1.1 V Counter
The VCOUNT register can be used to read which of the total of 228 LCDlines (see previous figure) is currently being rendered.
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
VCOUNT006h 0000hR
Address Register Attributes Initial Value
V counter value0-227
A value of 0-227 is read.
A value of 0-159 indicates that rendering is in progress; a value of 160-227indicates a vertical blanking interval.
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AGB Programming Manual LCD
©1999 - 2001 Nintendo of America Inc. 27 D.C.N. AGB-06-0001-002B4
4.1.2 General LCD Status
General LCD status information can be read from bits 0-5 of theDISPSTAT register.
In addition, 3 types of interrupt requests can be generated by the LCDcontroller.
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
DISPSTAT004h 0000hR/W
Address RegisterInitial Value
V count setting0-227
V-Blank Status 0: Outside V-blank interval 1: During V-blank interval
H-Blank Status0: Outside H-blank interval1: During H-blank interval
V Counter Evaluation0: V counter non-match1: V counter match
V-Blank Interrupt Request Enable Flag0: Disable1: Enable
H-Blank Interrupt Request Enable Flag0: Disable1: Enable
V Counter Match Interrupt Request Enable Flag0: Disable1: Enable
Attributes
DISPSTAT [d15-08] V Count Setting
Can be used to set the value used for V counter evaluation and V countermatch interrupts. The range for this setting is 0-227.
DISPSTAT [d05] V Counter Match Interrupt Request Enable Flag
Allows an interrupt request to be generated when the value of the V countersetting and the value of the line actually rendered (VCOUNT register value)agree.
DISPSTAT [d04] H-Blank Interrupt Request Enable Flag
Allows an interrupt request to be generated during horizontal blanking.
DISPSTAT [d03] V-Blank Interrupt Request Enable Flag
Allows an interrupt request to be generated during vertical blanking.
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AGB Programming Manual LCD
©1999 - 2001 Nintendo of America Inc. 28 D.C.N. AGB-06-0001-002B4
DISPSTAT [d02] V Counter Evaluation
Flag indicating whether the V count setting and the V count register valuematch. It is set while they match and automatically reset when they nolonger match.
DISPSTAT [d01] H-Blank Status
Can check whether a horizontal blanking interval is currently in effect.
DISPSTAT [d00] V-Blank Status
Can check whether a vertical blanking interval is currently in effect.
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AGB Programming Manual Image System
©1999 - 2001 Nintendo of America Inc. 29 D.C.N. AGB-06-0001-002B4
5 Image SystemAGB can use different image systems depending on the purpose of the software.These display-related items are changed mainly using the DISPCNT register.
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
DISPCNT0000h 0080hR/W
Address Register Attributes Initial Value
(CGB Mode)
Display Frame Selection0: Frame buffer 01: Frame buffer 1
BG Mode0-5
OBJ BG3 BG2BG1 BG0
Window 0 Display Flag
OBJ Window Display Flag
Window 1 Display Flag
0: Enable(OBJ Processing of all H-Line Intervals)1: Disable(OBJ Processing of H-Line Display Intervals Only)
OBJ Character VRAM Mapping Format0: 2-dimensional1: 1-dimensional
Forced Blank0: Disable1: Enable
Individual Screens Display0: OFF1: ON
H-Blank Interval OBJ Processing Flag
DISPCNT [d15] OBJ Window Display Flag
Master flag that controls whether the OBJ window is displayed.
For information on the OBJ window, see section “6.3, OBJ (Object)”.
DISPCNT [d14][d13] Display Flags for Windows 0 and 1
Master flag that controls whether windows 0 and 1 are displayed.
For information on windows, see “Chapter 8, Window Feature”.
DISPCNT [d12-08] Individual Screens Display Flag
Allows individual control of whether BG0, BG1, BG2, BG3, and OBJ,respectively, are displayed.
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AGB Programming Manual Image System
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DISPCNT [d07] Forced Blank
Setting this bit causes the CPU to forcibly halt operation of the imageprocessing circuit, allowing access to VRAM, color palette RAM, OAM, andthe internal registers. The LCD screen displays white during a forcedblank. However, the internal HV synchronous counter continues to operateeven during a forced blank. When the internal HV synchronous countercancels a forced blank during a display period, the display begins from thebeginning, following the display of three vertical lines.
DISPCNT [d06] OBJ Character VRAM Mapping Format
Specifies the VRAM mapping format for an OBJ character.
A setting of 0 causes the OBJ character to be handled in memory mapped2-dimensional. A setting of 1 causes the OBJ character to be handled inmemory mapped 1-dimensional.
For information on OBJ character VRAM mapping formats, see section6.3.2, Character Data Mapping.
DISPCNT [d05] H-Blank Interval OBJ Processing Flag
A setting of 0 executes OBJ Render Processing with all H-Lineintervals(including H-Blank intervals).
A setting of 1 executes OBJ Render Processing with the display intervalsonly and not for H-Blank intervals. Thus, when the user accesses OAM orOBJ VRAM during an H-Blank interval, this bit needs to be set. However,also in this situation, maximum OBJ display performance cannot beobtained.
DISPCNT [d04] Display Frame Selection
When rendering in bitmap format in a mode in which there are 2 framebuffers (BG modes 4 and 5), this bit allows selection of one of the framebuffers for rendering. A setting of 0 selects the contents of frame buffer 0for rendering; a setting of 1 selects the contents of frame buffer 1 forrendering.
DISPCNT [d03] (CGB Mode)
AGB is equipped with 2 CPUs. In AGB mode, a 32-bit RISC CPU starts,and in CGB mode, an 8-bit CISC CPU starts. Because this bit iscontrolled by the system, it cannot be accessed by the user.
DISPCNT [d02-00] BG Mode
Selects the BG mode from a range of 0-5.
For more information on BG modes, see the following section.
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AGB Programming Manual Image System
©1999 - 2001 Nintendo of America Inc. 31 D.C.N. AGB-06-0001-002B4
5.1 BG Modes
5.1.1 Details of BG Modes
In AGB, changing the BG mode allows character format and bitmap formatto be used selectively, as appropriate.
In modes 0, 1, and 2, rendering to the LCD screen is performed in acharacter format suitable for the game.
In modes 3, 4, and 5, rendering to the LCD screen is performed in bitmapformat.
Character Format BG ScreenFeatures
BG Mode Rotation/Scaling
No. ofScreens
SizeNumber ofCharactersSpecifiable
Number of Colors/Palettes
*1 *2 *3 *4 *5 *6
0 No 4256 x 256
to512 x 512
102416 / 16256 / 1
O O O O O O
No 2256 x 256
to512 x 512
102416 / 16256 / 1
O O O O O O
1Yes 1
128 x 128to
1024 x 1024256 256 / 1 O X O O O O
2 Yes 2128 x 128
to1024 x 1024
256 256 / 1 O X O O O O
Bitmap Format BG Screen FeaturesBG Mode
Rotation/
Scaling
No. of
ScreensSize
FrameMemory
No. of Colors*1 *2 *3 *4 *5 *6
3 Yes 1 240 x 160 1 32,768 O X O O O O
4 Yes 1 240 x160 2 256 O X O O O O
5 Yes 1 160 x 128 2 32,768 O X O O O O
Features *1 HV Scroll (individual screens) *4 Semitransparent(16 levels)*2 HV Flip (individual characters) *5 Fade-in/Fade-out*3 Mosaic (16 levels) *6 Screen priority specification (2 bits)
[Note]In mode 3, one frame memory is available that can display 32,768 colors, which is suitable forrendering still images. Modes 4 and 5 allow double buffering using two frame memories, and arethus suitable for rendering animated video.
The method of controlling text BG scrolling is different from that of BG rotation/scaling andbitmap BG scrolling. (See “6.1.8 BG Scrolling” and “6.1.7 BG Rotation and Scaling Features”.)
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AGB Programming Manual Image System
©1999 - 2001 Nintendo of America Inc. 32 D.C.N. AGB-06-0001-002B4
5.1.2 VRAM Memory Map
The VRAM (96 Kbyte) memory maps in the BG modes are as shown in thefollowing figure.
OBJCharacter Data
32 Kbytes
Frame Buffer 080 Kbytes
OBJCharacter Data
16 Kbytes
Frame Buffer 140 Kbytes
OBJCharacter Data
16 Kbytes
Frame Buffer 040 Kbytes
BG Modes 0, 1, and 2 BG Mode 3 BG Modes 4 and 5
06010000h
06014000h
0600A000h
06014000h
06000000h
06017FFFh
BG0-BG3Screen Data
Maximum 32 Kbytes
BG0-BG3 SharedCharacter Data
Minimum 32 Kbytes
and
Users can map the screen and character data areas in the 64 Kbyte BGarea in BG modes 0, 1, and 2. For more information, see section 6.1.3,VRAM Address Mapping of BG Data.
In addition, see the descriptions below for more information on the memoryareas and the data formats for each area.
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AGB Programming Manual Rendering Functions
©1999 - 2001 Nintendo of America Inc. 33 D.C.N. AGB-06-0001-002B4
6 Rendering FunctionsThe AGB CPU has 96 Kbytes of built-in VRAM.
Its rendering functions include BG and OBJ display capability. The method used for BGrendering varies with the BG mode, as described below.
6.1 Character Mode BG (BG Modes 0-2)
In character mode, the components of the BG screen are basic characters of 8 x 8dots.
6.1.1 BG Control
There are 4 BG control registers, corresponding to the maximum numberof BG screens (registers BG0CNT, BG1CNT, BG2CNT, and BG3CNT).
Registers BG0CNT and BG1CNT are exclusively for text BG control, whileBG2CNT and BG3CNT also support BG rotation and scaling control.
The registers used by the BG modes are as follows.
BG Mode BG Control RegisterBG0CNT BG1CNT BG2CNT BG3CNT
0 BG0(text)
BG1(text)
BG2(text)
BG3(text)
1 BG0(text)
BG1(text)
BG2(rotation/scaling)
2 BG2(rotation/scaling)
BG3(rotation/scaling)
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AGB Programming Manual Rendering Functions
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The contents of the BG control registers are shown below.
1) Text BG Screen Control (BG0, BG1)
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00BG0CNTBG1CNT
008h00Ah
0000hR/W
Address Register Attributes Initial Value
Priority Specification
00: 1st priority01: 2nd priority10: 3rd priority11: 4th priority
Character Base Block0-3
00
Screen Size
Mosaic0: Disable1: Enable
Color Mode0: 16 colors x 16 palettes1: 256 colors x 1 palette
Screen Base Block0-31
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AGB Programming Manual Rendering Functions
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2) Text BG and Rotation/Scaling BG Screen Control (BG2 and BG3)
Whether the screen is a text screen or a scaling/rotation screen varieswith the BG mode.
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00BG2CNTBG3CNT
00Ch00Eh
0000hR/W
Address Register AttributesInitial Value
Priority Specification00: 1st priority01: 2nd priority10: 3rd priority11: 4th priority
Character Base Block0-3
00
Screen SizeScreen Size
Mosaic0: Disable1: Enable
Color Mode0: 16 colors x 16 palettes1: 256 colors x 1 palette
Screen Base Block0-31
Area Overflow Processing Flag0: Transparent display1: Wraparound display
BG*CNT [d15-14] Screen Size
Allows the screen size for the BG as a whole to be specified.
When a value other than the maximum is specified, the remaining VRAMarea can be used as a character data area.
Refer to the table below and the VRAM Memory Map figure above.
Screen SizeSetting
Text Screen Rotation/Scaling Screen
Screen Size Screen Data Screen Size Screen Data
00 256×256 2 Kbytes 128×128 256 Bytes
01 512×256 4 Kbytes 256×256 1 Kbyte
10 256×512 4 Kbytes 512×512 4 Kbytes
11 512×512 8 Kbytes 1024×1024 16 Kbytes
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AGB Programming Manual Rendering Functions
©1999 - 2001 Nintendo of America Inc. 36 D.C.N. AGB-06-0001-002B4
1) Overview of Screen Sizes for Text BG Screens
[d15,d14]=[0,0] Virtual screen size:256 x 256 [d15,d14]=[0,1] Virtual Screen size: 512 x 256
Display Screen(240 x 160)
SC0(256 x 256) SC0
SC1SC1(256 x 256)
Display Screen(240 x 160)
SC0(256 x 256)
SC1(256 x 256)
SC2(256 x 256)
SC3(256 x 256)
SC0
SC2
SC0SC1SC0
[d15,d14]=[1,0] Virtual screen size: 256 x 512 [d15,d14]=[1,1] Virtual screen size: 512 x 512
SC0(256 x 256) SC0
SC0 SC0
Display Screen(240 x 160)
SC0(256 x 256)
SC0 SC1
SC1(256 x 256)
Display Screen(240 x 160)
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AGB Programming Manual Rendering Functions
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2) Illustration of Screen Sizes for Rotation/Scaling BG Screens
[d15,d14]=[0,0] Virtual screen size: 128 x 128 [d15,d14]=[0,1] Virtual screen size: 256 x 256
[d15,d14]=[1,0] Virtual screen size: 512 x 512
SC0(256 x 256)
[d15,d14]=[1,1] Virtual screen size: 1024 x1024
Display Screen(240 x 160)
SC0(1024 x1024)
SC0or
Transparent
SC0or
Transparent
SC0or
Transparent
SC0or
Transparent
Display Screen(240 x 160)
SC0(512 x 512)
SC0or
Transparent
SC0or
Transparent
SC0or
Transparent
SC0or
Transparent
SC0or
Transparent
SC0(128 x 128)
Display Screen(240 x 160)
SC0or
Transparent
Display Screen(240 x 160)
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AGB Programming Manual Rendering Functions
©1999 - 2001 Nintendo of America Inc. 38 D.C.N. AGB-06-0001-002B4
BG2CNT,BG3CNT [d13] Area Overflow Processing
When the display screen overflows the boundaries of the virtual screendue to a rotation/scaling operation, this bit can be used to choose whetherthe area of the screen into which the overflow occurs is displayed astransparent or wraps around the display screen.
For information on scaling, see “6.1.7 BG Rotation and Scaling Features”.
BG*CNT [d12-08] Screen Base Block Specification
Specifies the starting block in VRAM where screen data are stored.(32 steps: 0-31; 2-Kbyte increments).
See section 6.1.3, VRAM Address Mapping of BG Data.
BG*CNT [d07] Color Mode
Specifies whether to reference BG character data in 16 color x 16 paletteformat or 256 color x 1 palette format.
BG*CNT [d06] Mosaic
Turns mosaic processing for BG on and off.
BG*CNT [d03-02] Character Base Block Specification
Specifies the starting block in VRAM where the character data to bedisplayed in the BG is stored.(4 steps: 0-3; 16-Kbyte increments)
See section 6.1.3, VRAM Address Mapping of BG Data.
BG*CNT [d01-00] Priority Among BGs
With the default value (same priority value specified for all), the order ofpriority is BG0, BG1, BG2, and BG3. However, this order can be changedto any desired.
Values of 0 (highest priority) to 3 can be specified.
When the BG priority has been changed, care should be taken inspecifying the pixels used for color special effects.
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AGB Programming Manual Rendering Functions
©1999 - 2001 Nintendo of America Inc. 39 D.C.N. AGB-06-0001-002B4
6.1.2 Mosaic Size
Mosaic size is set in the MOSAIC register.
Turning mosaic on/off for each BG is accomplished by the mosaic flag ofthe BG control register.
For information on the mosaic flag, see the previous section, BG Control.
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
MOSAIC04Ch 0000hW
Address RegisterAttributesInitial Value
BG MosaicH size
BG MosaicV size
OBJ MosaicH size
OBJ MosaicV size
The mosaic value specifies how many dots of a normal display shouldcomprise each large dot displayed.
Counting from the upper left-most dot on the screen, the number of dotsequal to the mosaic size are used in the mosaic display. The other dotsare overwritten by the mosaic. Please refer to the figure below.
If the mosaic size value is 0, a normal display is seen even if mosaic isturned on.
Mosaic Schematic
01 02 03 04 05 06 07 08 09
11 12
21
13
22
30
14
23
31
40
15 16
24 25
1917 18
26 27 28
32
41
33 34 35
42
50
45 46 47 48 49
55 56
65
57
66
75
58
67
76
59
68 69
77 78 79
60 61 62 63 64
70 71 72 73 74
39
51 52 53 54
36 37 38
43 44
29
00
10
20
04 06 08
22
40
24 26 28
42 46 48
66 6860 62 64
44
20
0200
00 00
04 08
6860 64
0000 00
00 00
00 00
00 00
00 00
00 00
00 00
00 00
00 00
00 00
00 00
00 00
Normal Display Mosaic H size: 1V size: 1
Mosaic H size: 3V size: 5
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AGB Programming Manual Rendering Functions
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6.1.3 VRAM Address Mapping of BG Data
BG data (BG character and screen data) are stored in the 64-Kbyte BGarea of VRAM.
1) BG Character Data
The starting address for referencing BG character data can be specifiedusing the character base block specification of the BG control register.
The amount of data depends on the number of character data items storedand the data format (color formats: 256 colors x 1 palette or 16 colors x 16palettes).
2) BG Screening Data
The starting address for referencing BG screen data can be set using thescreen base block specification of the BG control register.
The amount of data depends on the type of BG screen (text orrotation/scaling) and the screen size. These can be set by the BG controlregister.
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AGB Programming Manual Rendering Functions
©1999 - 2001 Nintendo of America Inc. 41 D.C.N. AGB-06-0001-002B4
Illustration of VRAM Base Blocks for BG Data
OBJCharacter Data
32 Kbytes
OBJCharacter Data
32 Kbytes
BG Character DataBase Block
BG Screen DataBase Block
10000h
Base Block 3
C000h
Base Block 31Base Block 30Base Block 29Base Block 28Base Block 27Base Block 26Base Block 25Base Block 24
Base Block 2
8000h
Base Block 23Base Block 22Base Block 21Base Block 20Base Block 19Base Block 18Base Block 17Base Block 16
Base Block 1
4000h
Base Block 15Base Block 14Base Block 13Base Block 12Base Block 11Base Block 10Base Block 9Base Block 8
Base Block 0
0000h
Base Block 7Base Block 6Base Block 5Base Block 4Base Block 3Base Block 2Base Block 1Base Block 0
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AGB Programming Manual Rendering Functions
©1999 - 2001 Nintendo of America Inc. 42 D.C.N. AGB-06-0001-002B4
6.1.4 Character Data Format
There are two formats for character dot data, 16 color x 16 palettes and256 colors x 1 palette. The same format is used for OBJ and BG.
The data are held in VRAM in the form indicated below.
1) 16 Colors x 16 Palettes
There are 2 dots per address. Thus, the amount of data for each basiccharacter is 20H x 8 bits.
4 bits of dataper dot
(Specifies 1 of 16colors)
d7
d6
d5
d4
d3
d2
d1
d0
d7
d6
d5
d4
d3
d2
d1
d0
d7
d6
d5
d4
d3
d2
d1
d0
d7
d6
d5
d4
d3
d2
d1
d0
8 dots
a(n)
a(n+ 4)
a(n+ 8)
a(n+1C)
a(n+14)
a(n+10)
a(n+ C)
a(n+18)
a(n+ 1)
a(n+ 5)
a(n+ 9)
a(n+1D)
a(n+ D)
a(n+11)
a(n+15)
a(n+19)
a(n+ 2)
a(n+ 6)
a(n+ A)
a(n+ E)
a(n+12)
a(n+16)
a(n+1A)
a(n+1E)
a(n+ 3)
a(n+ 7)
a(n+ B)
a(n+ F)
a(n+13)
a(n+17)
a(n+1B)
a(n+1F)
8 dots
2) 256 Colors x 1 Palette
There is 1 dot specified per address. Thus, the amount of data for eachbasic character is 40H x 8 bits.
a(n+ 4)
a(n+ C)
a(n+14)
a(n+1C)
a(n+24)
a(n+2C)
a(n+34)
a(n+3C)
a(n+ 5)
a(n+ D)
a(n+15)
a(n+1D)
a(n+25)
a(n+2D)
a(n+35)
a(n+3D)
a(n+ 6)
a(n+ E)
a(n+16)
a(n+1E)
a(n+26)
a(n+2E)
a(n+36)
a(n+3E)
a(n+ 7)
a(n+ F)
a(n+17)
a(n+1F)
a(n+27)
a(n+2F)
a(n+37)
a(n+3F)
a(n)
a(n+ 8)
a(n+10)
a(n+18)
a(n+20)
a(n+28)
a(n+30)
a(n+38)
a(n+ 1)
a(n+ 9)
a(n+11)
a(n+19)
a(n+21)
a(n+29)
a(n+31)
a(n+39)
a(n+ 2)
a(n+ A)
a(n+12)
a(n+1A)
a(n+22)
a(n+2A)
a(n+32)
a(n+3A)
a(n+ 3)
a(n+ B)
a(n+13)
a(n+1B)
a(n+23)
a(n+2B)
a(n+33)
a(n+3B)
8 bits of data per dot(Specifies 1 of 256
colors)
d7
d6
d3
d5
d4
d2
d1
d0
d7
d6
d3
d5
d4
d2
d1
d0
d7
d6
d3
d5
d4
d2
d1
d0
d7
d6
d3
d5
d4
d2
d1
d0
d7
d6
d3
d5
d4
d2
d1
d0
d7
d6
d3
d5
d4
d2
d1
d0
d7
d6
d3
d5
d4
d2
d1
d0
d7
d6
d3
d5
d4
d2
d1
d0
8 dots
8 dots
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AGB Programming Manual Rendering Functions
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6.1.5 BG Screen Data Format
A BG screen is considered to be the 8 x 8 dot unit that represents the sizeof the basic character, and the BG screen data specifies the charactersthat are arranged.
BG screen data should be stored, beginning from the starting address ofthe BG screen base block specified in the BG control register. Thenumber of screen data items specified per BG depends on the screen sizesetting in the BG control register.
BG screen data for text and rotation/scaling screens are specified in thefollowing formats.
1) Text BG Screen
A text BG screen consists of 2 bytes of screen data per basic character;1,024 character types can be specified.
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Character name
Horizontal flip flag
Vertical flip flag
Color PaletteWith 16 colors x 16 palettes: 0-15With 256 colors x 1 palette: disabled
[d15-12] Color Palette
If the color mode specification in the BG control register is 16 colors x 16palettes, these bits specify palette 0-15 as the palette to be applied to thecharacter.
This is disabled when the color mode specification is 256 x 1 palette.
[d11] Vertical Flip Flag
Enables the BG character to be flipped vertically.
A setting of 1 produces the vertical-flip display.
[d10] Horizontal Flip Flag
Enables the BG character to be flipped horizontally.
A setting of 1 produces the horizontal-flip display.
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[d09-00] Character Name
Specify the number of the character that has character base block startingaddress specified in the BG control register as its starting point.
2) Rotation/Scaling BG Screen
The rotation/scaling BG screen consists of 1 byte of screen data per basiccharacter; 256 character types can be specified.
The character data must be classified as 256 colors x 1 palette.
The color mode specification in the BG control register is disabled for arotation/scaling screen.
Character Name
07 06 05 04 03 02 01 00
[Cautions for VRAM]
AGB provides a high degree of freedom in using the BG area of VRAM.
Consequently, in managing VRAM, the following points deserve particularattention.
1. There are 2 formats for BG character data (defined by 16 and 256colors), and these can be used together.
2. The BG character data base block can be selected from among 4blocks (BG control register).
3. The BG screen data base block can be selected from among 32blocks (BG control register).
4. The screen size (amount of VRAM used) can be set for each BG (BGcontrol register).
5. Text and rotation/scaling BGs can be present and used together in aBG screen.
In managing VRAM, particular care is required in BG mode 1, because textBG screens (which can handle BG character data in both 256 colors x 1palette and 16 colors x 16 palettes) and rotation/scaling BG screens(which can handle only 256 colors x 1 palette) may be used together.
Therefore, the VRAM mapping status should be sufficiently understoodwhen programming.
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AGB Programming Manual Rendering Functions
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6.1.6 BG Screen Data Address Mapping for the LCD Screen
1) Text BG
1-1) Virtual Screen Size of 256 x 256 Dots
LCD Display Area
000H 002H 004H 006H
040H 042H 044H
088H080H 082H 084H 086H
008H
048H
03AH
046H
0C0H 0C2H 0C4H 0C6H
4C8H4C0H 4C2H 4C4H 4C6H
0C8H
7C8H7C0H 7C2H 7C4H 7C6H
07CH
03CH
0BCH
0DCH
4FCH
7FAH 7FCH
03EH
0BEH
07EH
0DEH
4FEH
7BEH
7FEH
07AH
0DAH
0BAH
4FAH
240 dots(30 blocks)
160 dots(20 blocks)
256 dots(32 blocks)
256 dots(32 blocks)
780H 782H 784H 788H786H 7BAH 7BCH
1-2) Virtual Screen Size of 512 x 256 Dots
LCD Display Area
000 H 002 H 004 H 006 H
040 H 042 H 044 H
080 H 082 H 084 H 086 H
800 H03A H
046 H
83E H
4C0 H 4C2 H 4C4 H 4C6 H
7C8 H7C0 H 7C2 H 7C4 H 7C6 H
07C H
03C H
0BC H
4FC H
03E H
0BE H
07E H
4FE H
07A H
0BAH
4FA H
256 dots(32 blocks)
512 dots(64 blocks)
256 dots(32 blocks)
780 H 782 H 784 H 788 H786 H
FFE HFC0 H7FE H7FC H
7BC H 7BE H
256 dots(32 blocks)
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1-3) Virtual Screen Size of 256 x 512 Dots
LCD display area
000H 002H 004H
040H 042H 044H
03AH
4C0H 4C2H 4C4H
FC0H FFEH
07AH
256 dots(32 blocks)
256 dots(32 blocks)
512 dots(64 blocks)
7C0H
800H
7C2H 7C4H
03CH
7FEH
83EH
4FCH 4FEH4FAH
07CH
03EH
07EH
7FCH
1-4) Virtual Screen Size of 512 x 512 Dots
LCD display area
000H 002H 004H
040H 042H 044H
800H
07AH
4C0H 4C2H 4C4H
7FEH7C0H 7C2H 7C4H 7FCH
4FAH
1000H
256 dots(32 blocks)
512 dots(64 blocks) 256 dots
(32 blocks)
512 dots(64 blocks)
256 dots(32 blocks)
256 dots(32 blocks)
83EH03AH 03CH 03EH
07CH 07EH
4FCH 4FEH
FC0H
103EH 1800H
FFEH
183EH
17C0H 17FEH 1FFEH
040H 042H 044H
03AH
07AH
4C0H 4C2H 4C4H 4FAH
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2) Rotation/scaling BG
2-1) Virtual Screen Size of 128 x 128 Dots
LCD display area
000H 001H 002H 003H
010H 011H 012H
004H
014H
00FH
013H
0E1H 0E2H 0E3H
0F4H
0E0H
0F1H 0F2H 0F3H
0E4H
0F0H
01FH
0EFH
0FFH
128 dots(16 blocks)
128 dots(16 blocks)
240 dots(30 blocks)
160 dots(20 blocks)
2-2) Virtual Screen Size of 256 x 256 Dots
LCD display area
000H 001H 002H 003H
020H 041H 042H
084H040H 081H 082H 083H
004H
044H
01DH
043H
060H 0C1H 0C2H 0C3H
264H260H 261H 262H 263H
0C4H
280H 281H 282H 283H 284H
3E4H3E0H 3E1H 3E2H 3E3H
03EH
01EH
05EH
06EH
27EH
29DH 29EH
3FDH 3FEH
01FH
05FH
03FH
06FH
29FH
27FH
3DFH
3FFH
03DH
06DH
05DH
27DH
240 dots(30 blocks)
160 dots(20 blocks)
256 dots(32 blocks)
256 dots(32 blocks)
3C0H 3C1H 3C2H 3C4H3C3H 3DDH 3DEH
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AGB Programming Manual Rendering Functions
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2-3) Virtual Screen Size of 512 x 512 Dots
LCD display area
000H 001H 002H 003H
040H 041H 042H
084H080H 081H 082H 083H
004H
044H
01DH
043H
0C0H 0C1H 0C2H 0C3H
4C4H4C0H 4C1H 4C2H 4C3H
0C4H
500H 501H 502H 503H 504H
FC4HFC0H FC1H FC2H FC3H
05EH
01EH
09EH
0DEH
4DEH
51DH 51EH
FDDH FDEH
03EH
0BEH
07EH
0FEH
03FH
0BFH
07FH
0FFH
53EH
4FEH
53FH
4FFH
FFEH
FBFH
FFFH
05DH
0DDH
09DH
4DDH
240 dots(30 blocks)
160 dots(20 blocks)
512 dots(64 blocks)
512 dots(64 blocks)
F80H F81H F82H F84HF83H F9DH F9EH FBEH
2-4) Virtual Screen Size of 1024 x 1024 Dots
000H 001H 002H 003H
080H 081H 082H
104H100H 101H 102H 103H
004H
084H
01DH
083H
180H 181H 182H 183H
984H980H 981H 982H 983H
184H
A00H A01H A02H A03H A04H
3F84H3F80H 3F81H 3F82H 3F83H
09EH
01EH
11EH
19EH
99EH
A1DH A1EH
3F9DH 3F9EH
07EH
17EH
0FEH
1FEH
07FH
17FH
0FFH
1FFH
A7EH
9FEH
A7FH
9FFH
3FFEH
3F7FH
3FFFH
09DH
19DH
11DH
99DH
240 dots(30 blocks)
160 dots(20 blocks)
1024 dots(128 blocks)
1024 dots(128 blocks)
3F00H 3F01H 3F02H 3F04H3F03H 3F1DH 3F1EH 3F7EH
LCD display area
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AGB Programming Manual Rendering Functions
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6.1.7 BG Rotation and Scaling Features
Rotation and scaling of the BG as a whole can be performed in arotation/scaling BG screen.
With rotation, BG data is referenced as shown in the following figure.
BG displayscreen
BG data reference area
Horizontal line beforerotation
Horizontal line after
rotation
θ
x-axis
y-axis
dx (distance moved in direction x, same line) = (1 / α ) cos θ dy (distance moved in direction y, same line) = - (1 / β ) sin θdmx (distance moved in direction x, next line) = ( 1 / α ) sin θdmy (distance moved in direction y, next line) = ( 1 / β ) cos θ
α: Magnification along x-axisβ : Magnification along y-axis
θ
θ
dx
dydmy
dmx
∗
Rotation centercoordinate
),( 00 yx
Origin)0,0( Coordinate
before rotation),( 11 yx
Coordinate afterrotation
),( 22 yx
BG rotation and scaling are implemented in AGB using the following arithmeticexpressions.
001012
001012
0
0
01
01
2
2
)()()()(
cos1,sin1,sin1,cos1
yyyDxxCy
xyyBxxAx
DCBA
yx
yyxx
DC
BAyx
+−+−=
+−+−=
=−===
+
−−
=
θβ
θβ
θα
θα
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AGB Programming Manual Rendering Functions
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Parameters used in rotation and scaling operations are specified for BG2and BG3 in the following registers. Registers for Starting Point of BG DataReference are also used when Scaling/Rotation BG and Bitmap Mode BGare offset displayed (scrolled). (There is also an offset register for TextBG.)
Registers for Setting the Starting Point of BG Data
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00BG2X_LBG3X_L
028h038h
0000hW
Address Register AttributesInitial Value
X-coordinate of reference starting point (rotation/scaling results)
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00BG2X_HBG3X_H
02Ah03Ah
0000hW
Address Register AttributesInitial Value
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00BG2Y_LBG3Y_L
02Ch03Ch
0000hW
Address Register Attributes Initial Value
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00BG2Y_HBG3Y_H
02Eh03Eh
0000hW
Address Register AttributesInitial Value
Y-coordinate of reference starting point(rotation/scaling results)
Y-coordinate of reference starting point (rotation/scaling results)
X-coordinate of reference starting point(rotation/scaling results)
Registers for Setting the Direction Parameters of BG Data
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00BG2PABG3PA
020h030h
0100hW
Address Register Attributes Initial Value
dx: distance of movement in x direction along same line
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00BG2PBBG3PB
022h032h
0000hW
Address Register
dmx: distance of movement in x direction along next line
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00BG2PCBG3PC
024h034h
0000hW
Address Register
dy: distance of movement in y direction along same line
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00BG2PDBG3PD
026h036h
0100hW
Address Register
dmy: distance of movement in y direction along next line
Attributes Initial Value
Attributes Initial Value
Attributes Initial Value
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AGB Programming Manual Rendering Functions
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Operations Used in BG Rotation/Scaling Processing
1. Using software, the user determines the results of the rotation/scalingoperation for the left-upper coordinate of the display screen and setsthis as the starting point of the BG data reference in registers BG2X_L,BG2X_H, BG2Y_L, BG2Y_H, BG3X_L, BG3X_H, BG3Y_L, andBG3Y_H. The set value is a signed fixed-point number (8 bits forfractional portion, 19 bits for integer portion, and 1 bit for sign, for a totalof 28 bits).
The BG data reference direction is set in BG2PA, BG2PB, BG2PC,BG2PD, BG3PA, BG3PB, BG3PC, and BG3PD. The set value is asigned fixed-point number (8 bits for fractional portion, 7 bits for integerportion, and 1 bit for sign, for a total of 16 bits).
2. The image processing circuit sums the increases in the x direction (dx,dy) in relation to the BG data reference starting point set in the aboveregisters, and calculates the x-coordinate.
3. When the line is advanced, the increases in the y direction (dmx, dmy)are summed in relation to the reference starting point, and thecoordinate of the rendering starting point for the next line is calculated.The processing in step 2) is then performed.
4. However, if a register for the BG data reference starting point isrewritten during an H-blanking interval, the y-direction summation forthat register is not calculated. The CPU uses this mode to change thecenter coordinate and the rotation/scaling parameters for each line.
Area Overflow Processing
When the display screen overflows the boundaries of the virtual screendue to a rotation/scaling operation, this BG control register can be used toselect whether the area of the screen into which the overflow occurs istransparent or wraps around the display screen.
For information on BG control, see “6.1.1 BG Control”.
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6.1.8 BG Scrolling
For each text BG screen, the offset on the display screen can be specifiedin 1-dot increments. Offset register is only valid for Text BG. In order tooffset display Scaling/Rotation BG and Bitmap Mode BG set the BGReference Starting Point. See “6.1.7, BG Rotation and Scaling Features”.
Offset Settings Registers
H offset
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00BG0HOFSBG1HOFSBG2HOFSBG3HOFS
010h014h018h01Ch
0000hW
Address RegisterAttributesInitial Value
V offset
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00BG0VOFSBG1VOFSBG2VOFSBG3VOFS
012h016h01Ah01Eh
0000hW
Address Register AttributesInitial Value
Offset Illustration
H Offset
V Offset
Screen
Display Screen
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6.2 Bitmap Mode BGs (BG Modes 3-5)
In the bitmap modes, the components of the BG screen are handled in pixel units, andthe contents of VRAM (frame buffer) are displayed as color data for each dot on thescreen.
6.2.1 BG Control
The bitmap BG will be treated as BG2. Therefore, in order to display thecontent of the frame buffer on the LCD screen, you need to set the BG2display flag to ON in the DISPCNT Register. For BG Control the BG2CNTRegister is used.
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00BG2CNT00Ch
0000hR/W
Address Register Attributes Initial Value
Priority Specification
00: 1st priority01: 2nd priority10: 3rd priority11: 4th priority
00
Mosaic0: Disable1: Enable
BG2CNT [d06] Mosaic
This controls the ON/OFF of mosaic processing for BG2. When ON, thesettings for the Mosaic Size Register, MOSAIC, are referenced. Forinformation on Mosaic, see “6.1.2 Mosaic Size”.
BG2CNT [d01-00] Priority Among BGs
Due to the fact that in Bitmap Mode there is only one BG plane(other thanthe backdrop plane), there is no priority relationship among BGs, but youcan set up priorities with OBJ. For information on this, see “6.4 DisplayPriority of OBJ and BG”.
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6.2.2 BG Rotation/Scaling
The parameters for Bitmap BG Rotation/Scaling use BG2 relatedregisters(BG2X_L, BG2X_H, BG2Y_L, BG2Y_H, BG2PA, BG2PB, BG2PC,and BG2PD).
For information on rotation/scaling parameters, see “6.1.7 BGRotation and Scaling Features”.
With Bitmap BG, if the displayed portion exceeds the edges of the screendue to the rotation/scaling operation, that area becomes transparent.
6.2.3 Pixel Data
In the bitmap modes, only the amount of pixel data corresponding to thesize of the display screen can be stored in VRAM. Available bitmap modesallow the simultaneous display of 32,768 colors (BG modes 3 and 5) andthe display of 256 of the 32,768 colors (BG mode 4). The format of thedata in the frame buffer differs between the modes as described below.
1. 32,768-Color Simultaneous Display Format (BG Modes 3 and 5)
Palette RAM is not referenced.
Each pixel uses a half-word.
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
RedGreenBlue
B4 B3 B2 B1 B0 G4 G3 G2 G1 G0 R4 R3 R2 R1 R0
2. 256-Color (of 32,768) Display Format (BG Mode 4)
Palette RAM color data (256 of the 32,768 colors storable) arereferenced.
Each pixel uses 1 byte.
Color No.
07 06 05 04 03 02 01 00
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6.2.4 Pixel Data Address Mapping for the LCD Screen
The different address mappings for the different BG modes are shownbelow.
The frame buffer (VRAM) starts at address 06000000h. Thus, to see theaddresses used by the CPU, add 06000000h to the addresses shownbelow.
6.2.4.1 BG Mode 3 (32,768 colors, 240X160 dots, 1 frame buffer)
Because there is a single frame buffer, this mode is used mainly for stillimages. However, it enables 32,768 colors to be displayed simultaneouslyover the full screen.
0 1 2 3 4 236 237 238 239
0 0h 2h 4h 6h 8h 1D8h 1Dah 1DCh 1DEh
1 1E0h 1E2h 1E4h 1E6h 1E8h 3B8h 3Bah 3BCh 3BEh
2 3C0h 3C2h 3C4h 3C6h 3C8h 598h 59Ah 59Ch 59Eh
3 5A0h 5A2h 5A4h 5A6h 5A8h 778h 77Ah 77Ch 77Eh
4 780h 782h 784h 786h 788h 958h 95Ah 95Ch 95Eh
156 12480h 12482h 12484h 12486h 12488h 12658h 1265Ah 1265Ch 1265Eh
157 12660h 12662h 12664h 12666h 12668h 12838h 1283Ah 1283Ch 1283Eh
158 12840h 12842h 12844h 12846h 12848h 12A18h 12A1Ah 12A1Ch 12A1Eh
159 12A20h 12A22h 12A24h 12A26h 12A28h 12BF8h 12BFAh 12BFCh 12BFEh
VRAM address (+06000000h)
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6.2.4.2 BG Mode 4 (256 colors, 240X160 dots, 2 frame buffers)
Two frame buffers are allocated in VRAM, making this mode suitable forfull-motion video. Of the total of 32,768 colors, 256 can be displayedsimultaneously over the full screen.
1) Frame 0
0 1 2 3 4 236 237 238 239
0 0h 1h 2h 3h 4h ECh EDh EEh EFh
1 F0h F1h F2h F3h F4h 1DCh 1DDh 1DEh 1DFh
2 1E0h 1E1h 1E2h 1E3h 1E4h 2CCh 2CDh 2CEh 2CFh
3 2D0h 2D1h 2D2h 2D3h 2D4h 3BCh 3BDh 3BEh 3BFh
4 3C0h 3C1h 3C2h 3C3h 3C4h 4ACh 4ADh 4AEh 4AFh
156 9240h 9241h 9242h 9243h 9244h 932Ch 932Dh 932Eh 932Fh
157 9330h 9331h 9332h 9333h 9334h 941Ch 941Dh 941Eh 941Fh
158 9420h 9421h 9422h 9423h 9424h 950Ch 950Dh 950Eh 950Fh
159 9510h 9511h 9512h 9513h 9514h 95FCh 95FDh 95FEh 95FFh
VRAM address (+06000000h)
2) Frame 1
0 1 2 3 4 236 237 238 239
0 A000h A001h A002h A003h A004h A0ECh A0EDh A0EEh A0EFh
1 A0F0h A0F1h A0F2h A0F3h A0F4h A1DCh A1DDh A1DEh A1DFh
2 A1E0h A1E1h A1E2h A1E3h A1E4h A2CCh A2CDh A2CEh A2CFh
3 A2D0h A2D1h A2D2h A2D3h A2D4h A3BCh A3BDh A3BEh A3BFh
4 A3C0h A3C1h A3C2h A3C3h A3C4h A4ACh A4ADh A4AEh A4AFh
156 13240h 13241h 13242h 13243h 13244h 1332Ch 1332Dh 1332Eh 1332Fh
157 13330h 13331h 13332h 13333h 13334h 1341Ch 1341Dh 1341Eh 1341Fh
158 13420h 13421h 13422h 13423h 13424h 1350Ch 1350Dh 1350Eh 1350Fh
159 13510h 13511h 13512h 13513h 13514h 135FCh 135FDh 135FEh 135FFh
VRAM address (+06000000h)
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6.2.4.3 BG Mode 5 (32,768 colors, 160X128 dots, 2 frame buffers)
Although there are 2 frame buffers, the display area is limited in this modeto enable simultaneous display of 32,768 colors.
1) Frame 00 1 2 3 4 156 157 158 159
0 0h 2h 4h 6h 8h 138h 13Ah 13Ch 13Eh
1 140h 142h 144h 146h 148h 298h 29Ah 29Ch 29Eh
2 2A0h 2A2h 2A4h 2A6h 2A8h 3B8h 3BAh 3BCh 3BEh
3 3C0h 3C2h 3C4h 3C6h 3C8h 4F8h 4FAh 4FCh 4FEh
4 500h 502h 504h 506h 508h 638h 63Ah 63Ch 63Eh
124 9B00h 9B02h 9B04h 9B06h 9B08h 9C38h 9C3Ah 9C3Ch 9C3Eh
125 9C40h 9C42h 9C44h 9C46h 9C48h 9D78h 9D7Ah 9D7Ch 9D7Eh
126 9D80h 9D82h 9D84h 9D86h 9D88h 9EB8h 9EBAh 9EBCh 9EBEh
127 9EC0h 9EC2h 9EC4h 9EC6h 9EC8h 9FF8h 9FFAh 9FFCh 9FFEh
VRAM Address (+06000000h)
2) Frame 1
0 1 2 3 4 156 157 158 159
0 A000h A002h A004h A006h A008h A138h A13Ah A13Ch A13Eh
1 A140h A142h A144h A146h A148h A298h A29Ah A29Ch A29Eh
2 A2A0h A2A2h A2A4h A2A6h A2A8h A3B8h A3BAh A3BCh A3BEh
3 A3C0h A3C2h A3C4h A3C6h A3C8h A4F8h A4FAh A4FCh A4FEh
4 A500h A502h A504h A506h A508h A638h A63Ah A63Ch A63Eh
124 13B00h 13B02h 13B04h 13B06h 13B08h 13C38h 13C3Ah 13C3Ch 13C3Eh
125 13C40h 13C42h 13C44h 13C46h 13C48h 13D78h 13D7Ah 13D7Ch 13D7Eh
126 13D80h 13D82h 13D84h 13D86h 13D88h 13EB8h 13EBAh 13EBCh 13EBEh
127 13EC0h 13EC2h 13EC4h 13EC6h 13EC8h 13FF8h 13FFAh 13FFCh 13FFEh
VRAM address (+06000000h)
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6.3 OBJ (Object)
6.3.1 OBJ Function Overview
Objects are in character format regardless of the BG mode. However, thenumber of basic characters that can be defined varies depending on theBG mode.
Item FunctionNumber of display colors 16 colors/16 palettes or 256 colors/1 palette (mixed display possible)
Number of characters(8x8 dots)
1,024 (16 colors x 16 palettes) : in BG modes 0-2 512 (256 colors x 1 palette) : " 512 (16 colors x 16 palettes) : in BG modes 3-5 256 (256 colors x 1 palette) : "
Character size 8x8 - 64x64 dots (12 types)
Max. number per screen 128 (64x64 dot conversion)
Max. number per line 128 (8x8 dot conversion)
Color special effects HV flip, semi-transparency, mosaic, priority specification, OBJ windows
OBJ Display Capability on a Single Line
The single-line OBJ display capability shown in the table above, is thecapability at maximum efficiency.
When the displayed OBJ are arranged continuously from the start of OAM,you can calculate the OBJ display capability on a single line using thefollowing formula:
(Number of H Dots × 4 - 6) / Number of Rendering Cycles =
OBJ Displayable on a single line(Max. of 128)
The “Number of H Dots” is usually 308 dots, but when the H-Blank IntervalOBJ Processing Flag for Register DISPCNT is set to 1, there are 240dots(Refer to “4 LCD”).
“×4” expresses the number of cycles that the OBJ
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