verilog design chapter 3
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Chapter 3
Number Representationand
Arithmetic Circuits
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Binary numbers
Unsigned numbers
• all bits represent the magnitude of a positive integer
Signed numbers
• left-most bit represents the sign of a number
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Table 3.1. Numbers in different systems.
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Figure 3.1. Half-adder.
Sum
s
0
1
10
Carry
c
0
0
01
0
0+
0
1+
1000
1
0+
10
1
1+
01
x
y+
sc
SumCarry
(a) The four possible cases
x y
0
0
11
0
1
01
(b) Truth table
x
y
s
c
HA
x
y
s
c
(c) Circuit (d) Graphical symbol
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Figure 3.3. Full-adder.
0
0
0
1
0
1
1
1
c
i 1+
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
ci
xi
yi
00 01 11 10
0
1
xi y
i
ci
1
1
1
1
si
xi
yi
ci
=
00 01 11 10
0
1
x i y i
ci
1
1 1 1
ci 1+
xi y
i x
ici
yici
+ +=
ci
xi
yi si
ci 1+
(a) Truth table
(b) Karnaugh maps
(c) Circuit
0
1
1
0
1
0
0
1
si
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Figure 3.4. A decomposed implementation of the full-adder circuit.
HA
HAs
c
s
cci
xi
yi ci 1+
si
ci
xi
yi
ci 1+
si
(a) Block diagram
(b) Detailed diagram
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Figure 3.5. An n-bit ripple-carry adder.
FA
xn –1
cn cn 1”
yn 1 –
sn 1 –
FA
x1
c2
y1
s1
FA
c1
x0 y0
s0
c0
MSB position LSB position
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Figure 3.6. Circuit that multiplies an eight-bitunsigned number by 3.
7 x0 y7 y0
x7 x0 y8 y0y7 x8
s0s7
c7
0
s0s8
c8
P9
P8
P0
P 3 A= :
x1
x0
y8
y0
y7
x8
s0s8
c8
0 0
a7 A :
P9 P8 P0P 3 A= :
(a) Naive approach
(b) Efficient design
a0
a7 A : a0
x
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Figure 3.7. Formats for representation of integers.
bn 1 – b1 b0
Magnitude
MSB
(a) Unsigned number
bn 1 – b1 b0
MagnitudeSign
(b) Signed number
bn 2 –
0 denotes1 denotes
+ – MSB
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Negative numbers can be represented in following ways:
• Sign and magnitude
•1’s complement
•2’s complement
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1’s complement
Let K be the negative equivalent of an n-bit positive number P.
Then, in 1’s complement representation K is obtained by
subtracting P from 2
n
– 1, namely
K = (2n – 1) – P
This means that K can be obtained by inverting all bits of P.
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Deriving 2’s complement
For a positive n-bit number P, let K 1 and K 2 denote its 1’s
and 2’s complements, respectively.
K 1 = (2n – 1) – PK 2 = 2
n – P
Since K 2 = K 1 + 1, it is evident that in a logic circuit the 2’s
complement can computed by inverting all bits of P and thenadding 1 to the resulting 1’s-complement number.
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Table 3.2. Interpretation of four-bit signed integers.
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Figure 3.10. Examples of 2’s complement subtraction.
–
0 1 0 1
0 0 1 0
5+( )
2+( )
3+( )
–
1
ignore
+
0 0 1 1
0 1 0 1
1 1 1 0
–
1 0 1 1
0 0 1 0 –
1
ignore
+
1 0 0 1
1 0 1 1
1 1 1 0
–
0 1 0 11 1 1 0
5+( )
7+( )
– +
0 1 1 1
0 1 0 10 0 1 0
5 –( )
7 –( )
2+( )
2 –( )
–
1 0 1 1
1 1 1 0 – +
1 1 0 1
1 0 1 1
0 0 1 02 –( )5 –( )
3 –( )
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Figure 3.12. Adder/subtractor unit.
s0s1sn 1 –
x0 x1 xn 1 –
cn n-bit adder
y0y1yn 1 –
c0
Add Subcontrol
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Figure 3.13. Examples of determination of overflow.
++
1 0 1 1
1 0 0 1
0 0 1 0
1 0 0 1
0 1 1 1
0 0 1 0
7+( )
2+( )
9+( )
+
++
0 1 1 1
1 0 0 1
1 1 1 0
0 1 0 1
0 1 1 1
1 1 1 0
7+( )
5+( )
+ 2 –( )
11
c 4 0=c 3 1=
c 4 0=c 3 0=
c 4 1=
c 3 1=
c 4 1=
c 3 0=
2+( )
7 –( )
5 –( )
+
7 –( )
9 –( )
+ 2 –( )
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Figure 3.15. The first two stages of a carry-lookahead adder.
x1 y1
g1 p1
s1
x0 y0
s0
c2
x0 y0
c0
c1
g0 p0
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Figure 3.16. A hierarchical carry-lookahead adder with
ripple-carry between blocks.
Block
x 31 24 –
c 32 c 24
y 31 24 –
s31 24 –
x 15 8 –
c 16
y 15 8 –
s15 8 –
c 8
x 7 0 – y 7 0 –
s7 0 –
c 03Block
1Block
0
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Figure 3.17. A hierarchical carry-lookahead adder.
Block
x15 8 – y15 8 – x7 0 – y7 0 –
3Block
1Block
0
Second-level lookahead
c0
s7 0 –
P0G0P1G1P3G3
s15 8 –s31 24 –
c8c16c32
x31 24 – y31 24 –
c24
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Figure 3.34. Multiplication of unsigned numbers.
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Figure 3.35. A 4x4 multiplier circuit.
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Figure 3.36. Multiplication of signed numbers.
0 00 1 1 1 0
0 1 1 1 0
0 1 0 1 1
0 0 1 1 1 0
0 0 1 0 1 0 1
0 0 0 0 0 0
Multiplicand M
Multiplier Q
Product P
(+14)
(+11)
(+154)
+
+
0 0 0 1 0 1 0
0 0 1 1 1 0+
0 0 1 0 0 1 1
0 0 0 0 0 0+
0 0 1 0 0 1 1 0 1 0
Partial product 0
Partial product 1
Partial product 2
Partial product 3
1 11 0 0 1 0
1 0 0 1 0
0 1 0 1 1
1 1 0 0 1 0
1 1 0 1 0 1 1
0 0 0 0 0 0
Multiplicand M
Multiplier Q
Product P
( 14)
(+11)
( 154)
+
+
1 1 1 0 1 0 11 1 0 0 1 0+
1 1 0 1 1 0 0
0 0 0 0 0 0+
1 1 0 1 1 0 0 1 1 0
Partial product 0
Partial product 1
Partial product 2
Partial product 3
–
–
(a) Positive multiplicand
(b) Negative multiplicand
x
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Figure 3.42. Conversion from decimal to hexadecimal.
Convert (14959)10
Remainder Hex digit
14959 ÷ 16 = 934 15 F LSB
934 ÷ 16 = 58 6 6
58 ÷ 16 = 3 10 A
3 ÷ 16 = 0 3 3 MSB
Result is (3A6F)16
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