unit 5 synchronous and asynchronous sequential circuits

Unit 5Synchronous And Asynchronous

Sequential Circuits

Algorithmic State Machine

ASM Block

Timing

An Algorithmic Binary Multiplier

Either adding the multiplier or 0000

Shifting partial product rightis the same as shifting the multiplier to the left

Synchronous Moore Machine

Combinational logic circuit {Input decoder}

Memory Elements

Outputdecoder

State signals

Next state

Present state

Outputs

Inputs

Asynchronous Moore Machine

Outputdecoder

State signals

Outputs

Inputs

Synchronous Mealy Machine

Memory Elements

Outputdecoder

State signals

Next state

Present state

Inputs

Asynchronous Mealy Machine

Outputdecoder

State signals

Outputs

Inputs

• Asynchronous Sequential Circuits

In steady-state condition, the y's and the Y's are the same, but during transition they are not.

According to how input variables are to be considered, there are 2 types of asynchronous circuits: Fundamental mode circuits Pulse mode circuits

FUNDAMENTAL MODE CIRCUITS:

It assumes that: Input changes should be spaced by at least t,the time needed for the circuit to settle into a stable state following an input change. That is, the input variables should change only when the circuit is stable. Only 1 input variable can change at a given instant of time.

Inputs are levels and not pulses. Delay lines are used as memory elements.

PULSE MODE CIRCUIT:

It assumes that The input variables are pulses instead of levels. The width of the pulse is long enough for the circuit to respond to the input. The pulse width must not be so long that it is still present after the new state is reached. pulses should not occur simultaneously on 2 or more input lines.

Derivation of primitive flow table:

The flow table in asynchronous sequential circuit is same as that of state table in the synchronous sequential circuit. In asynchronous sequential circuits stable state table is known as flow table because of the behaviour of the asynchronous sequential circuits. The state changes occur independent of a clock, based on the logic propagation delay, and cause the states to ‘flow’ from one to another. A primitive flow table is a special case of flow table which has exactly 1 stable state for each row in the table. The design process begins with the construction of primitive flow table 1515

• fundamental mode

fundamental mode :Only one input variable can change at any one time and the time between two input changes must be longer than the time it takes the circuit to reach a stable state.

TRANSITION TABLE

This diagram clearly shows 2 feedback loops from the OR gate outputs back to the AND gate inputs. The circuit consists of 1 input variable x and 2 internal states. The 2 internal states have 2 excitation variables, Y1 and Y2, and 2 secondary variables, y1 and y2. Each logic gate in the path introduces a propagation delay of about 2 to 10 ns. We can derive the Boolean expressions for the excitation variables as a function of the input and secondary variables. 1717

Transition Table

Y1 = xy1 + x'y2 Y2 = xy'1 + x'y21818

The encoded binary values of the y variables are used for the labeling the rows, and the input variable x is used to designate the columns. The following table provides the same information as the transition table. There is 1 restriction that applies to the asynchronous case, but not the synchronous case. In the asynchronous transition table, there usually is at least 1 next state entry that is the same as the present state value in each row. Otherwise, all the total states in that row will be unstable.

Transition Table

Y1 = xy1 + x'y2 Y2 = xy'1 + x'y2

Transition Table

For a state to be stable, the value of Y must be the same as that of y = y1y2

Transition Table

The Unstable states, Y ≠ y

Transition Table

Consider the square for x = 0 and y = 00. It is stable.

x changes from 0 to 1.

The circuit changes the value of Y to 01. The state is unstable.

The feedback causes a change in y to 01. The circuit reaches stable.

Transition Table

In general, if a change in the input takes the circuit to an unstable state, y will change until it reaches a stable state.

Flow Table

Transition table whose states are named by letter symbol instead of binary values.

Flow Table

FLOW TABLE

During the design of asynchronous sequential circuits, it is more convenient to name the states by letter symbols without making specific reference to their binary values. Such table is called a flow table.

Flow TableIt is called primitive flow table because it has only one stable state in each row.

It is a flow table with more than one stable state in the same row. 2727

Flow Table

Prob 2: Design a circuit with inputs A and B to give an output Z=1 when AB=11 but only if A=1 before B, by drawing total state diagram, primitive flow table and output map in which transient state is included

prob 3: Develop the state diagram and primitive flow table for a logic system that has two inputs X and Y and a single output Z, which is to behave in the following manner.1.Initially both inputs and outputs are equal to 0.2.Whenever X=1 and Y=0, the Z becomes 1.3.Whenever X=0 and Y=1, the Z becomes 0. 4.When X=Y=0 or X=Y=1, the output Z does not change; it remains in the previous state. The logic system has edge triggered inputs and the system change state on the rising edges of the two inputs. 3535

Output

Inputs State diagram

Present state

Next state, output Z for XY inputs

00 00 00 00

A A , 0 B , 0 _ , _ C , _

B A , _ B , 0 D , _ _ , _

C E , _ _ , _ F , _ C , 1

D _ , _ B , _ D,0 C , _

E E, _ B , _ _ , _ C , _

F _ , _ B , _ F,1 C , _

Primitive Flow Table

Reduction of Primitive Flow Table

Set of maximal compatibilities (A ,B,D) S0

(C ,E,F) S1

PresentState

Next state , output Z for XY inputs

00 01 11 10

S0 S0 , 0 S0 , 0 S0 , 0 S1 , _

S1 S1 , 1 S0 , _ S1 , 1 S1 , 1

Reduced flow diagram

PresentState

Next state , output Z for XY inputs

00 01 11 10

0 0 , 0 0 , 0 0 , 0 1 , _

1 1 , 1 0 , _ 1 , 1 1 , 1

0 0 0 1

1 0 1 1

Implementation using K-map

F+ = XY’ + FX + FY’

Transition table S0 0 S1 1

0 0 0 X

1 X 1 1

F+ = Z

Z = FX + FX’ + XY’

State Diagram

S6S5S4S3

X=1 X=1

X=1X=1X=1 X=0X=0

X=0 X=0

Present StateNext State

X=0 X=1

Output O=0S1

Output O=0

Output O=0S3

Output O=0

Output O=0S5

Output O=0

Output O=1S0

Output O=1

Output O=0S0

Output O=0

Output O=1S0

Output O=1

Output O=0S0

Output O=0

State Table

X=0 X=1

Output O=0S1

Output O=0

Output O=0S35

Output O=0

Output O=0S35

Output O=0

Output O=1S0

Output O=1

Output O=0S0

Output O=0

Reduced State Table

X=0 X=1

Output O=0S12

Output O=0

S12S46

Output O=0S35

Output O=0

Output O=1S0

Output O=1

Output O=0S0

Output O=0

Minimal State Table

Reduced State Diagram

X=1X=0X=1

X=0X=0

X=1 X=0

PresentState

Next State Flip-Flop State OutputsOX=0 X=1 X=0 X=1

AB AB AB D1 D0 D1 D0

00 01 01 0 1 0 1 0

01 10 11 1 0 1 1 0

10 00 00 0 0 0 0 0

11 00 00 0 0 0 0 1

Revised State Table of State Diagram

A’B’ (00) A’B (01) AB (11) AB’ (10)

X’ (0) 0 1 0 0

X (1) 0 1 0 0

3 Variable K-Map D1 = A’B

A’B’ (00) A’B (01) AB (11) AB’ (10)

X’ (0) 1 0 0 0

X (1) 1 1 0 0

3 Variable K-Map D0 = A’B’ + XA’

Implementation of sequential circuit using logic gates and D flip-flops

Q = AB Clock

Problem: Analyze the given fundamental mode asynchronous sequential circuit given.

Solution: The given circuit has 2 input variables I1 and I0 and 1 output variable Z. The circuit has 2 feedback paths which provide inputs to the gates, creating latching operation necessary to produce a sequential circuit. The feedback path also generates the state variables X0 and X1. The next state for the circuit is determined by both, the state of the input variables and the state variables.

Step 1: Determine next-secondary state and output equations. Step 2: Construct state table.

OUTPUT MAP:

0 0 0 0

- - 0 -

0 - 1 -

- - - -

01 11 10

X1 X0I1 I0

Design Example

Problem: Design a gated latch circuit with two inputs G (gate) and D (data), and one output Q. Binary information present at the D input is transferred to the Q output when G is equal to 1. The Q output will follow the D input as long as G=1. When G goes to 0, the information that was present at the D input at the time the transition occurred is retained at the Q output. The gated latch is a memory element that accepts the value after G goes to 0. Once G=0, a change the value of the output Q.

Primitive flow tableA primitive flow table is a flow table with only one stable state in each row.

Inputs

Output

commentsD G Qabcdef

0 11 10 01 01 00 0

010011

D =Q because G = 1D =Q because G = 1

After state a or dAfter state c

After state b or fAfter state e

The primitive flow table shown has one row for each state and one column for each input combination. For eg, state a is stable and the output is 0 when the input is 01. This information is entered in the flow table in the first row and second column. Similarly, the other 5 stable states together with their output are entered in the corresponding input columns. Since both the inputs are not allowed to change simultaneously, we can enter dash marks in each row that differs in 2 or more variables from the input variables associated with the stable state. Next it is necessary to find the values for 2 or more squares in each row. The unstable state values for the other squares are determined in a similar manner. All the outputs associated with unstable states are marked with dash to indicate don’t care conditions.

Design Example

Inputs

Output

D G Qabcdef

0 11 10 01 01 00 0

010011 5757

Reduction of the Primitive Flow Table

Two of more rows in the primitive flow table can be merged into one row if there are non-conflicting states and outputs in each of the columns.

Reduction of the Primitive Flow Table

Transition Table and Logic Diagram

Circuit With SR Latch

Assigning Output to Unstable States

1. Assign a 0 to an output variable associated with an unstable state that is a transient state between two stable states that have a 0 in the corresponding output variable.

2. Assign a 1 to an output variable associated with an unstable state that is a transient state between two stable states that have a 1 in the corresponding output variable.

3. Assign a don't-care condition to an output variable associated with an unstable state that is a transient state between two stable states that have different values in the corresponding output variable.

Equivalent States

Two states are equivalent if for each possible input, they give exactly the same output and go to the same next states or to equivalent next states.

The characteristic of equivalent states is that if (a,b) imply (c,d) and (c,d) imply (a,b), then both pairs of states are equivalent.

Implication table

The state reduction procedure for completely specified state table can be combined into one if they can be shown to be equivalent if for each possible input, they can give exactly the same output and go to the next states or equivalent states.

Implication Table

Two states are equivalent if for each possible input, they give exactly the same output and go to the same next states or to equivalent next states.

The characteristic of equivalent states is that if (a,b) imply (c,d) and (c,d) imply (a,b), then both pairs of states are equivalent.

Implication Table

00 01 11 10

BCDEFG

D/0 D/0 F/0 A/0C/1 D/0 E/1 F/0

C/1 D/0 E/1 A/0D/0 B/0 A/0 F/0C/1 F/0 E/1 A/0D/0 D/0 A/0 F/0G/0 G/0 A/0 A/0B/1 D/0 E/1 A/0

S n+1/Zn

Example

A B C D E F G

Without the last

Without the first

A B C D E F G

00 01 11 10

BCDEFG

D/0 D/0 F/0 A/0C/1 D/0 E/1 F/0

C/1 D/0 E/1 A/0D/0 B/0 A/0 F/0C/1 F/0 E/1 A/0D/0 D/0 A/0 F/0G/0 G/0 A/0 A/0B/1 D/0 E/1 A/0

S n+1/Zn

example

Implied Pairs

A B C D E F G

The equivalent states ： [A ， F] 、 [B ， H] 、 [B ， C] 、 [C ， H]。

The largest group of equivalent states

[A ， F], [B ， C ， H],[D], [E], [G]

S n+1/Zn

00 01 11 10

D/0 D/0 A/0 A/0C/1 D/0 E/1 A/0

D/0 B/0 A/0 A/0B/1 A/0 E/1 A/0

G/0 G/0 A/0 A/0

Denoted by A Denoted by B

Combined into [B,C,H]

Reduction of Primitive Flow Table Reduction of the Flow Table to a MinimumNumber of Rows Reduce the number of state variables Reduce the amount of logic required Reduction Method :1.Equivalent states can be combined by usingimplication table method for completely specifiedstate tables2.Compatible rows can be merged for incompletelyspecified tables

Equivalent StatesIf c and d are equivalent, thena and b are equivalent(a,b) -> (c,d)

State Table To Be Reduced

Reduced State Table

State diagram:

Problem: Obtain the primitive flow table for an asynchronous circuit that has 2 inputs x, y and 1 output z. An output z=1 occur only during the input state xy=01 and then if the input state xy=01 is preceded by the input sequence xy=01, 00, 10, 00, 10, 00.

Primitive flow table:

States Machine Design• Other topics on state machine design

– Equivalent sequential machines– Incompletely specified machines– One Hot State Machines

Equivalent State Machines• So far have seen that equivalent states in

the state table of a sequential machine are equivalent and can be removed.

• How about the equivalence between two sequential circuits?– Two sequential circuits are equivalent is they

are capable of doing the same work.

Formally

– Sequential circuit N1 is equivalent to sequential circuit N2 if for each state p in N1, there is a state q in N2 such that pq, and conversely, for each state s in N2 there is a state t in N1 such that st.

– Simply said they have the same states which can be seen if the circuit is small enough.

• An implication table can be used to prove this.

An example• State tables and state graphs of two

sequential machines. Figure 15-6 from the text.

• Equivalent?

Proving equivalence• Again will use an implication table.

– Only this time it is the full square.– Along bottom are the state of one machine– Along the side are the states of the second.

• Start by removing output incompatible states.

Step 2• Go back through and remove

the implied equivalence pairs that were Xed on the first pass. Continue until no further Xs are entered.

• If there is one square not Xed in each row and each column, the state machines are equivalent.

• Consider problem 15-17

9/2/2012 – ECE 3561 Lect 10

The equivalence implication table

• X squares where the outputs are incompatible

• Enter implied equivalence pairs for remaining states.

Incompletely Specified• Incompletely Specified State Tables

– State tables that contain don’t cares.– Results in reduced logic

• Determining the best way to fill in the don’t cares is another of the n-p complete problems.

• For this course do the most logical approach.

RACES AND CYCLES

When two or more binary state variables change their value in response to a change in an input variable, race condition occurs in an asynchronous sequential circuit. In case of unequal delays, a race condition may cause the state variables to change in an unpredictable manner. For example, if there is a change in two state variables due to change in input variable such that both change from 00 to 11. In this situation, the difference in delays may cause the first variable to change faster than the second resulting the state variables to change in sequence 83

from 00 to 11 and then to 11. On the other hand, if the second variable changes faster than first, the state variables change from 00 to 01 and then to 11. If the final stable state that the circuit reaches does not depend on the order in which the state variable changes, the race condition is not harmful and it is called a non critical race. But if the final stable state depends on the order in which the state variable changes, the race condition is harmful and it is called a critical race. Such critical races must be avoided for proper operation.

NON CRITICAL RACES

The following diagram illustrates non critical races. It shows transition tables in which X is a input variable and y1 y2 are the state variables. Consider a circuit is in a stable state y1 y2 x=000and there is change in the input there are three possibilities that the state variables may change. They can either change simultaneously from 00 to 11, or they may change in sequence from 00 to 01 and then to 11, or they may change in sequence from 00 to 10 and then to 11. In all cases, the final stable state is 11, which results in a non critical race condition. 85

Race Conditions

Two or more binary state variables change value in response to a change in an input variable

Noncritical Race:State variables change from 00 to 11. The possible transition could be

00 01 11

00 10 11

It is a noncritical race. The final stable state that the circuit reaches does not depend on the order in which the state variables change.

CRITICAL RACES

The following diagram illustrates critical race. Consider a circuit is in a stable state y1 y2 x=000 and there is a change in input from 0 to 1. If state variable change simultaneously, the final stable state is y1 y2 x=111. If Y2 changes to 1 before Y1 because of unequal propagation delay, the circuit goes to stable state 011 and remain there. On the other hand, if Y1 changes faster than Y2, then the circuit goes to the stable state 101 and remain there. Hence the race is critical because the circuit goes to different stable states depending on the order in which the state variables change.

Race Conditions

Critical Race:State variables change from 00 to 11. The possible transition could be

00 01 11

It is a critical race. The final stable state depends on the order in which the state variables change.

CYCLES

A cycle occurs when an asynchronous circuit makes a transition through a series of unstable states. When a state assignment is made so that it introduces cycles, care must be taken to ensure that each cycle terminates on a stable state. If a cycle does not contain a stable state, the circuit will go from one unstable state to another, until the inputs are changed. Obviously, such a situation must always be avoided when designing asynchronous circuits. 89

Race Conditions

It starts with y1 y2 =00, then input changes from 0 to 1.

00 01 11

When a circuit goes through a unique sequence of unstable states, it is said to have a cycle.

The sequence is as follows,

The primary objective in choosing a proper binary state assignment is the prevention of critical races.

Critical races can be avoided by making a binary state assignment in such a way that only one variable changes at any given time when a state transition occurs in the flow table.

SHARED ROW METHOD

The assignment of a single binary variable to a flow table with two rows does not impose critical race problems. A flow table with three rows requires an assignment of two binary variables. The assignment of binary values to the stable states may cause critical races if not done properly. consider the following flow table. Inspection of row a reveals that there is a transition from state a to state b in column 01 and from state a to c in column 11. To avoid critical races, we must find a binary state assignment such that only one binary variable changes

during each state transition. An attempt to find such assignment is that, state a is assigned binary 00 and state c is assigned 11.

Three-Row Flow-Table Example

This assignment will cause a critical race during the transition from a to c.

A race free state assignment can be obtained if we add an extra row to the flow table. The use of fourth row does not increase the number of binary state variables, but it allows the formation of cycles between two state tables. The first 3 rows represent the same conditions as the original 3-row table. The fourth row, labeled d, is assigned the binary value 10, adjacent to both a and c. The transition from a to c must now go through d, with the result that the binary variables change from a to d to c, this avoiding a critical race. This is accomplished by changing row a, column 11 to d and row d, column 11 to c. similarly, the transition from c to a should go through unstable state d even though column 00 constitutes a non critical race.

Three-Row Flow-Table Example

The transition from a to c must now go through d, thus avoiding a critical race.

MULTIPLE-ROW METHOD

In multiple row assignment, each state in the original flow table is replaced by two or more combinations of state variables. There are 2 binary state variables for each stable state, each being the logical complement of each other. For example, the original state a is replaced with 2 equivalent states a1=000 and a2=111. Note that a1 is adjacent to b1, c2 and d1 and a2 is adjacent to c1, b2 and d2, and similarly each state is adjacent to 3 states of different letter designation. 9797

Multiple-Row Method

In the multiple-row assignment, each state in the original flow table is replaced by two or more combinations of state variables.

Note that a2 is adjacent to d2, c1, b2.

The expanded table is formed by replacing each row of the original table with 2 rows. For eg, row b is replaced by rows b1 and b2 and stable state b is entered in columns 00 and 11 in both the rows b1 and b2. After all the stable states have been entered, the unstable states are filled in by reference to the assignment specified in the map. When choosing the next state for a given present state, a state that is adjacent to the present state is selected from the map. In the original table, the next states of b are a and d for the inputs 10 and 01, respectively. In the expanded table, the next states for b2 are a2 and d1 because they are adjacent to b2.

Multiple-Row Method

The original flow table 100100

ONE HOT STATE ASSIGNMENT

The one hot state assignment is an another method for finding a race free state assignment In this method, only one variable is active or ‘hot’ for each row in the original flow table, i.e. it requires one state variable changes between internal state transitions. Consider a flow table.

101101

State variables State Inputs X1 X2

F4 F3 F2 F1 00 01 11 10

0 0 0 1 A A B C C

0 0 1 0 B A B C D

0 1 0 0 C A B C C

1 0 0 0 D D B C D

Flow table:

4 state variables are used to represent the 4 rows in the table. Each row is represented by a case where only one of the 4 state variables is a 1. A transition from state A to state B requires 2 state variable changes; F1 from 1 to 0 and F2 from 0 to 1. By directing the transition from A to B through a new row E which contains 1s where both states A and B have 1s.

102102

We require only one state variable change from transition A to E and then from transition E to B. This permits the race free transition between A and B. In general, we can say that, in row I of the table, state variable Fi is 1 and all other state variables are 0. When a transition between row i and j is required, first state variable Fj is set to 1 and Fi is set to 0. Thus each transition between 2 rows in the flow table goes through one intermediate row. This permits the race free transition but requires 2 state transitions. The following table is the complete one hot state assignment flow table. 103103

State variables State Inputs X1 X2

F4 F3 F2 F1 00 01 11 10

0 0 0 1 A A B C C

0 0 1 0 B A B C D

0 1 0 0 C A B C C

1 0 0 0 D D B C D

0 0 1 1 E A B - -

0 1 0 1 A - C C

0 1 1 0 G - B C -

1 0 1 0 H - B - D

1 1 0 0 I - - C -

When X1 X2=01 the transition from A to B is passing through the dummy state E. Similarly, when X1X2=00 the transition from C to A is passing through the dummy state F and so on. 104104

Guidelines for State Assignment

• To try all equivalent state assignments, i.e., and exhaustive exploration of all possible state assignments is a n-p complete problem.

• Do not panic!!! (where does this come from?)• There are guidelines that help• 1. States which have the same next state for a

given input should be given adjacent assignments.• 2. States which are the next states of the same

state should be given adjacent assignments.• And third• 3. States which have the same output for a given

input should be given adjacent assignments.

105105

Hazards

Hazards definition. Hazards in combinational circuit. static hazard dynamic hazard Hazard free circuit. Hazards in sequential circuit Essential hazards

106106

Hazards are unwanted switching transients that may appear at the output of a circuit because different paths exhibit different propagation delays.Hazards occur in combinational circuits, where they may cause a temporary false-output value.

When hazards occur in sequential circuits, it may result in a transition to a wrong stable state.

Hazards

Hazards in Combinational Circuits

-> Assume that all the three inputs are initially equal to 1. This causes the output of the gate 1 to be 1, that of gate 2 to be 0, and the output of the circuit to be equal to 1.

-> Now consider a change of x2 from 1 to 0. The output of gate 1 changes to 0 and that of gate 2 changes to 1, leaving the output at 1.

-> However, the output may momentarily go to 0 if the propagation delay through the inverter is taken into consideration.

-> The delay in the inverter may cause the output of gate 1 to change to 0 before the output of gate 2 changes to 1. 109

-> In that case, both inputs of gate 3 are momentarily equal to 0, causing the output to go to 0 for short interval of time that the input signal from x2 is delayed while it is propagating through the inverter circuit.

-> If the circuit is implemented in SOP,Y=x1 x2+x2’ x3This type of implementation may cause the output to go to 0 when it should remain at 1. This type is called as static 1-hazard.

-> If the circuit is Implemented in POS,Y=(x1+x2’) (x2+x3)Then the output may momentarily go to 1 when it should remain 0. This type is called as static 0- hazard.

-> A third type of hazard, known as dynamic hazard, causes the output to change three or more times when it should change from 1 to 0 or from 0 to 1. 110

The hazard exists because the change of input results in a different product term covering the two minterms.

In the above K-map, the change in x2 from 1 to 0 moves the circuit from minterm 111 to minterm 101. The hazard exists because the change of input results in a different product term covering the two min terms. Min term 111 is covered by the product term implemented in gate 2. whenever the circuit must move from one product term to another, there is a possibility of a momentary interval when neither term is equal to 1, giving rise to an undesirable 0 output.

Eliminating hazards

The remedy for eliminating hazard is to enclose the two minterms in question with another product term the overlap both the groupings.

This is shown in the following K-map, where two min terms that cause the hazard are combined into one product term.

The remedy for eliminating a hazard is to enclose the two minterms in question with another product term that overlap both grouping.

HAZARD FREE CIRCUIT

The following circuit is the hazard free circuit.The extra gate in the circuit generates the product term x1 x3.

In general hazards in combinational circuits can be eliminated covering any two minterms that may produce a hazard with a product term common to both.

The removal of hazard requires the addition of redundant gates to the circuit.

Prob: Give hazard-free realization for the following Boolean function.f(A,B,C,D)=m(0,2,6,7,8,10,12)Soln: The given function can be implemented using K-map.

00 101101

f= B’D’+A’BC+AC’D’ f= B’D’+A’BC+AC’D’+A’CD’

A C’ D’C DA’ B’B

HAZARDS IN SEQUENTIAL CIRCUITS

ESSENTIAL HAZARDS

There is another type of hazard that may occur in asynchronous sequential circuits, called essential hazard. An essential hazard is caused by unequal delays along two or more paths that originate from the same input. An excessive delay through an inverter circuit in comparison to the delay associated with the feedback path may cause such a hazard. Essential hazards cannot be corrected by adding redundant gated as in static hazards. The problem that they impose can be corrected by adjusting the amount of delay in the affected path.

To avoid essential hazards, each feedback loop must be handled with individual care to ensure that the delay in feedback path is long enough compared to delays of other signals that originate from the input terminals.

This problem tends to be specialized, as it depends on the particular circuit used and the amount of delays that atr encountered in its various paths.

Essential hazards

• A critical race between an input signal change and a feedback signal change – may cause an incorrect state transition

• Incorrect behaviour depends upon specific delays in gates/interconnections

• “If from any stable state, the final state reached after one change in an input is different to that reached after three changes in that input, then an essential hazard exists”

123123

Essential hazards

Starting from PRY1Y2 = 1010

The final state can be 00 or 01 for one or three changes in P

But, depending upon circuit delays, a single change in P may cause an incorrect transition to state 01

• What circuit delays? We must ensure that input signal delays are smaller than feedback signal delays.

124124

Essential hazards

Buffer delay increased here

125125

ELIMINATING ESSENTIAL HAZARDS

We can avoid essential hazards in asynchronous circuits by implementing them using SR latches. A momentary 0 signal applied to the S or R inputs of a NOR latch will have no effect on the state of the circuit. Similarly, a momentary 1 signal is applied to the S and R inputs of a NAND latch will have no effect on the state of the latch. Let us consider a NAND SR latch with the following Boolean function:

S= AB+CDR= A’C

126126

The first level consists of NAND gates that implement each product term in the original Boolean expression of S and R. The second level forms the cross coupled connection of the SR latch with the inputs that come from the outputs of each NAND gate in the first level.

127127

D1y1’

Essential hazard elimination128128

Present state Next state (Y1 Y2)

y1 y2 x=0 x=1

00 00 01

01 11 01

11 11 11

Flow table:

129129

Hardware Description Language - Introduction

• HDL is a language that describes the hardware of digital systems in a textual form.

• It resembles a programming language, but is specifically oriented to describing hardware structures and behaviors.

• The main difference with the traditional programming languages is HDL’s representation of extensive parallel operations whereas traditional ones represents mostly serial operations.

• The most common use of a HDL is to provide an alternative to schematics.

HDL – Introduction (2)

• When a language is used for the above purpose (i.e. to provide an alternative to schematics), it is referred to as a structural description in which the language describes an interconnection of components.

• Such a structural description can be used as input to logic simulation just as a schematic is used.

• Models for each of the primitive components are required.

• If an HDL is used, then these models can also be written in the HDL providing a more uniform, portable representation for simulation input.

Logic Simulation

• A simulator interprets the HDL description and produces a readable output, such as a timing diagram, that predicts how the hardware will behave before its is actually fabricated.

• Simulation allows the detection of functional errors in a design without having to physically create the circuit.

Verilog - Module

• A module is the building block in Verilog.• It is declared by the keyword module and is always

terminated by the keyword endmodule.• Each statement is terminated with a semicolon, but

there is no semi-colon after endmodule.

Verilog – Module (2)

HDL Examplemodule smpl_circuit(A,B,C,x,y);

input A,B,C;

output x,y;

wire e;

and g1(e,A,B);

not g2(y,C);

or g3(x,e,y);

endmodule

//Description of circuit with delay module circuit_with_delay (A,B,C,x,y); input A,B,C; output x,y; wire e; and #(30) g1(e,A,B); or #(20) g3(x,e,y); not #(10) g2(y,C);endmodule

• In order to simulate a circuit with HDL, it is necessary to apply inputs to the circuit for the simulator to generate an output response.

• An HDL description that provides the stimulus to a design is called a test bench.

• The initial statement specifies inputs between the keyword begin and end.

• Initially ABC=000 (A,B and C are each set to 1’b0 (one binary digit with a value 0).

• $finish is a system task.

Bitwise operators– Bitwise NOT : ~– Bitwise AND: &– Bitwise OR: |– Bitwise XOR: ^– Bitwise XNOR: ~^ or ^~

Boolean Expressions:• These are specified in Verilog HDL with a

continuous assignment statement consisting of the keyword assign followed by a Boolean Expression.

• The earlier circuit can be specified using the statement:assign x = (A&B)|~C)E.g. x = A + BC + B’D

y = B’C + BC’D’

//Circuit specified with Boolean equationsmodule circuit_bln (x,y,A,B,C,D); input A,B,C,D; output x,y; assign x = A | (B & C) | (~B & C); assign y = (~B & C) | (B & ~C & ~D);endmodule

User Defined Primitives (UDP):• The logic gates used in HDL descriptions with

keywords and, or,etc., are defined by the system and are referred to as system primitives.

• The user can create additional primitives by defining them in tabular form.

• These type of circuits are referred to as user-defined primitives.

• A module can be described in any one (or a combination) of the following modeling techniques.– Gate-level modeling using instantiation of primitive

gates and user defined modules.• This describes the circuit by specifying the gates and how

they are connected with each other. – Dataflow modeling using continuous assignment

statements with the keyword assign.• This is mostly used for describing combinational circuits.

– Behavioral modeling using procedural assignment statements with keyword always.

• This is used to describe digital systems at a higher level of abstraction.

4-bit Half Adder

4-bit Full Adder

//Gate-level hierarchical description of 4-bit adder module halfadder (S,C,x,y); input x,y; output S,C; //Instantiate primitive gates xor (S,x,y); and (C,x,y);endmodule module fulladder (S,C,x,y,z); input x,y,z; output S,C; wire S1,D1,D2; //Outputs of first XOR and two AND gates //Instantiate the half adders halfadder HA1(S1,D1,x,y), HA2(S,D2,S1,z); or g1(C,D2,D1);endmodule

4-bit Full Adder

module _4bit_adder (S,C4,A,B,C0); input [3:0] A,B; input C0; output [3:0] S; output C4; wire C1,C2,C3; //Intermediate carries

//Instantiate the full adder fulladder FA0 (S[0],C1,A[0],B[0],C0), FA1 (S[1],C2,A[1],B[1],C1), FA2 (S[2],C3,A[2],B[2],C2), FA3 (S[3],C4,A[3],B[3],C3);endmodule

4-bit Full Adder

2 to 4 Decoder

//Gate-level description of a 2-to-4-line decodermodule decoder_gl (A,B,E,D); input A,B,E; output[0:3]D; wire Anot,Bnot,Enot; not n1 (Anot,A), n2 (Bnot,B), n3 (Enot,E); nand n4 (D[0],Anot,Bnot,Enot), n5 (D[1],Anot,B,Enot), n6 (D[2],A,Bnot,Enot), n7 (D[3],A,B,Enot);endmodule

2 to 4 Decoder

2-to-4 Line Decoder

//2 to 4 line decodermodule decoder_2_to_4_st_v(E_n, A0, A1, D0_n, D1_n,

D2_n, D3_n);input E_n, A0, A1;output D0_n, D1_n, D2_n, D3_n;

wire A0_n, A1_n, E;not g0(A0_n, A0), g1(A1_n, A1), g2(E,E_n);nand g3(D0_n,A0_n,A1_n,E), g4(D1_n,A0,A1_n,E),

g5(D2_n,A0_n,A1,E), g6(D3_n,A0,A1,E);endmodule

Three-State Gates

• Three-state gates have a control input that can place the gate into a high-impedance state. (symbolized by z in HDL).

• The bufif1 gate behaves like a normal buffer if control=1. The output goes to a high-impedance state z when control=0.

• bufif0 gate behaves in a similar way except that the high-impedance state occurs when control=1

• Two not gates operate in a similar manner except that the o/p is the complement of the input when the gate is not in a high impedance state.

• The gates are instantiated with the statement– gate name (output, input, control);

Three-State Gates

module muxtri(A,B,sel,out); input A,B,sel; output OUT; tri OUT; bufif1 (OUT,A,sel); bufif0 (OUT,B,sel);endmodule

The output of 3-state gates can be connected together to form a common output line. To identify such connections, HDL uses the keyword tri (for tri-state) to indicate that the output has multiple drivers.

Three-State Gates

• Keywords wire and tri are examples of net data type.

• Nets represent connections between hardware elements. Their value is continuously driven by the output of the device that they represent.

• The word net is not a keyword, but represents a class of data types such as wire, wor, wand, tri, supply1 and supply0.

• The wire declaration is used most frequently.

• The net wor models the hardware implementation of the wired-OR configuration.

• The wand models the wired-AND configuration.

• The nets supply1 and supply0 represent power supply and ground.

Writing a Test Bench (2)

initial beginA=0; B=0; #10 A=1; #20

A=0; B=1;

• The block is enclosed between begin and end. At time=0, A and B are set to 0. 10 time units later, A is changed to 1. 20 time units later (at t=30) a is changed to 0 and B to 1.

Writing a Test Bench (2)

• Inputs to a 3-bit truth table can be generated with the initial block

initial beginD = 3’b000; repeat (7);

#10 D = D + 3’b001;

• The 3-bit vector D is initialized to 000 at time=0. The keyword repeat specifies looping statement: one is added to D seven times, once every 10 time units.

2-to-4 Line Decoder – Data flow description

//2-to-4 Line Decoder: Dataflow

module dec_2_to_4_df(E_n,A0,A1,D0_n,D1_n,D2_n,D3_n);

input E_n, A0, A1;

output D0_n,D1_n,D2_n,D3_n;

assign D0_n=~(~E_n&~A1&~A0);

assign D1_n=~(~E_n&~A1& A0);

assign D2_n=~(~E_n& A1&~A0);

assign D3_n=~(~E_n& A1& A0);

endmodule

4-to-1 Multiplexer

//4-to-1 Mux: Structural Verilogmodule mux_4_to_1_st_v(S,D,Y);

input [1:0]S;input [3:0]D;output Y;wire [1:0]not_s;wire [0:3]N;not g0(not_s[0],S[0]),g1(not_s[1],S[1]);and g2(N[0],not_s[0],not_s[1],D[0]), g3(N[1],S[0],not_s[1],D[0]), g4(N[2],not_s[0],S[1],D[0]), g5(N[3],S[0],S[1],D[0]);or g5(Y,N[0],N[1],N[2],N[3]);

endmodule

4-to-1 Multiplexer – Data Flow

//4-to-1 Mux: Dataflow descriptionmodule mux_4_to_1(S,D,Y);

input [1:0]S;input [3:0]D;output Y;assign Y = (~S[1]&~S[0]&D[0])|(~S[1]&S[0]&D[1])

|(S[1]&~S[0]&D[2])|(S[1]&S[0]&D[3]);endmodule

//4-to-1 Mux: Conditional Dataflow descriptionmodule mux_4_to_1(S,D,Y);

input [1:0]S;input [3:0]D;output Y;assign Y = (S==2’b00)?D[0] : (S==2’b01)?D[1] : (S==2’b10)?D[2] : (S==2’b11)?D[3]:1’bx;;

endmodule159

4-to-1 Multiplexer

//4-to-1 Mux: Dataflow Verilog Description

module mux_4_to_1(S,D,Y);

input [1:0]S;

input [3:0]D;

output Y;

assign Y=S[1]?(S[0]?D[3]:D[2]):(S[0]?D[1]:D[0]);

endmodule

HDL for Sequential Circuits

Lecture Outline

• Latches and Flip-flops

• Counters and Registers

Gated D Latch

module D_latch (Q,D,control); output Q; input D,control; reg Q; always @ (control or D) if (control) Q = D; //Same as: if (control = 1)endmodule

D Flip-flop

module D_FF (Q,D,CLK); output Q; input D,CLK; reg Q; always @ (posedge CLK) Q = D;endmodule

Testing Flip-flops

• Need to have flip-flop in known state at start of test– Add reset input

module DFF (Q,D,CLK,RST); output Q; input D,CLK,RST; reg Q; always @(posedge CLK or negedge RST) if (~RST) Q = 1'b0; // Same as: if (RST = 0) else Q = D;endmodule

T Flip-flop from D type

• Characteristic Equation

TQQ nn )()1(

module TFF (Q,T,CLK,RST); output Q; input T,CLK,RST; wire DT; assign DT = Q ^ T ;//Instantiate the D flip-flop DFF TF1 (Q,DT,CLK,RST);endmodule

JK Flip-flop from D type

• Characteristic Equation

)()()1( .. nnn QKQJQ

module JKFF (Q,J,K,CLK,RST); output Q; input J,K,CLK,RST; wire JK; assign JK = (J & ~Q) | (~K & Q);//Instantiate D flipflop DFF JK1 (Q,JK,CLK,RST);endmodule

Ripple Counter

module ripplecounter(count, reset, A0, A1, A2, A3); input count; input reset; output A0, A1, A2, A3; TFF T0(count, reset, A0); TFF T1(A0, reset, A1); TFF T2(A1, reset, A2); TFF T3(A2, reset, A3);endmodule

T Flip-flop

module TFF (T,RST,Q); input T, RST; output Q; reg Q; always @(negedge T or posedge RST) begin if (RST) begin Q = 1'b0; end else begin #2 Q = ~Q; end endendmodule

Binary Countermodule counter (Count,Load,IN,CLK,Clr,A,CO); input Count,Load,CLK,Clr; input [3:0] IN; //Data input output CO; //Output carry output [3:0] A; //Data output reg [3:0] A; assign CO = Count & ~Load & (A == 4'b1111); always @ (posedge CLK or negedge Clr) if (~Clr) A = 4'b0000; else if (Load) A = IN; else if (Count) A = A + 1'b1; else A = A; // no change endmodule

unit 5 synchronous and asynchronous sequential circuits

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