ultrafast 16-channel adc for nica-mpd forward detectors a.v. shchipunov join institute for nuclear...

Ultrafast 16-channel ADC for NICA-MPD Forward Detectors

A.V. Shchipunov

Join Institute for Nuclear Research

Dubna, Russia

http://afi.jinr.ru

Motivation Create a PCB Design for digitizing signals

from NICA-MPD’s Forward Detectors

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General view of the MPD

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Time Projection Chamber

Outer radius ~ 110 cmInner radius 27 cmDrift length ~ 150 cmNumber of sectors (each side) 12Total number of readout chambers 24 (12 - each side)Drift time ~ 25-30 ms

Multiplicity for charged particles ~ 500Total pad/channels number ~ 80000dE/dx resolution ~ 6% Spatial resolution (sx, sy, sz) 0.6 x 1.0 x 2.0 mmMaximal rate ~ 6 kHzTwo track resolution ~ 1 cm

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Time Of Flight

• Radius from the beam line 1.3 m• Time resolution 100 ps• Max momentum of π/K system

separated better than 2,5 σ 1,3 GeV/c

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16 input channels

high sampling rate — up to 5 GHz — for each channel

VME compatible PCB design

Self-calibration

Contain 72-bit QDR SRAM

Spartan-6 FPGA family

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Specifications and readout characteristicsSpecifications

Number of channels 16Effective resolution 11.5 bits

Bandwidth -3dB 950 MHzFull scale range ±1V on 50 ΩSampling speed 1, 1.7, 2, 3.4, 4, 5 GS/s

Sampling ring buffer 1024 samplesFPGA buffer size 4Mb / 256k samplesSRAM buffer size 64Mb / 4M samples

Readout characteristicsWaveform size 256 1024

DRS readout time 7,8 μs 31 μsEvent rate to RAM 124 kHz 31 kHz

FPGA buffer 1024 waveforms 256 waveformsSRAM buffer 16384 waveforms 4096 waveforms

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Functional diagram 16 Input Channels

Preamplifiers

Trigger logic

Sampling signals

ADCs

FPGASRAM buffer

VME itnerface

Self-calibrationTrig

ger

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DRS4 — Functional block diagram Sampling speed – 0,7 to 5 GSPS

8+1 channels with 1024 storage cells each

Differential inputs with 950 MHz bandwidth

Readout time: 30ns * number of samples

Simultaneous reading and writing

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CY7C1515KV18 — 72-Mb QDR® II SRAM 4-Word Burst Architecture

Separate independent read and write data ports

4-word burst for reducing address bus frequency

DDR interfaces for on both read and write ports

Full data coherency, providing most current data

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FPGA Spartan 6 — XC6SLX150T 147.443 logic cells

configurable logic blocks: 23.038 slices, 184.304 flip-flops, 1,355 MAX distributed RAM

4.824 RAM Blocks

4 memory controller blocks

6 banks

540 user I/O pins

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AD9788 — 16-bit 800 MSPS DAC Adjustable analog output: 8.7mA to 31.7mA, RL = 25Ω to 50Ω

Internal digital upconversion capability

High performance, low noise PLL clock multiplier

Digital inverse sinc filter

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ADC16V-DRS16 input channels

SRAM buffer

2 x DRS4 &2 x ADCs

Preamplifiers & analog switches

FPGA

TxDAC

VME interface

TTC ConnectorOutput connectors

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ADC8BE-DRS

FPGA

EtherNET interface

8 in

put c

hann

els

Preamplifiers & analog switches

DRS4 & ADC

TxDAC

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