tutorial 4 system level design an industrial perspective laurent maillet-contoz, st microelectronics...

Tutorial 4System Level Design

An Industrial Perspective

Laurent Maillet-Contoz, ST Microelectronics

Guido Stehr, Infineon Technologies

Sören Sonntag, Lantiq

Drew Taussig, Synopsys

Sylvian Kaiser, DOCEA Power

Enno Wein, ProximusDA

Speakers

Moderator Guido Stehr, Infineon Technologies

Cell phones offNo photography

Concept of this Tutorial

“System Level Design” – Covers wide range of problems and solution techniques

– Young discipline: Established but still evolving

Goal:– Give you an idea of how varied this discipline is

– Show what has arrived in industrial practice

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Contributions Overview presentation:

– Guido Stehr, Infineon Technologies: Transaction Level Modeling in Practice:

Motivation and Introduction

Focus presentations:– Laurent Maillet-Contoz, ST Microelectronics:

Standards for System Level Design

– Sören Sonntag, Lantiq: Design Space Exploration and Performance Evaluation

at Electronic System Level for NoC-based MP-SoC

– Sylvian Kaiser, DOCEA Power: ESL Solutions for Low Power Design

– Enno Wein, ProximusDA: HW / SW Co-Design of Parallel Systems

– Drew Taussig, Synopsys: Application Specific Processor Design

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1

2

3

4

5

coffeebreak

Transaction Level Modeling in Practice:Motivation and Introduction

Nov. 9th, 2010

Dr. Guido StehrDr. Josef Eckmüller

Infineon Technologies AG

Outline Transaction Level Modeling (TLM): Motivation

– Historic and emerging trends in electronic system design

– SystemC as language for system design in TLM style

TLM: Introduction– Modeling basics

Communication Computation

– Consistency between TLM and RTL

– Applications

Conclusions

5

Outline Transaction Level Modeling (TLM): Motivation

– Historic and emerging trends in electronic system design

– SystemC as language for TLM

TLM: Introduction– Modeling basics

Communication Computation

– Consistency between TLM and RTL

– Applications

Conclusions

6

Historic Trends in System Design

Increasing design complexity– Technological progress

Duplication of transistor count every two years

– Chip-level integration Combination of formerly separated chips

– Chip business platform business Vendor offers entire chip sets including software

Changing design styles– Shift in HW/SW partitioning

Custom HW programmable cores (standard/custom) + SW

– Increasing importance of IP Focus of in-house development on differentiators

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5

Emerging Trends in System Design

Introduction of multi-core architectures– Heterogeneous

Controller + DSPs

– Homogeneous Software Defined Radio with massive parallelism (> 20 cores)

Networks on chip– Increasing throughput requirements

Buses crossbars networks on chip (NoC)

Advanced power management– Battery life is key

Problem: Increasing demand for flexibility and processing power

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2

3

4

Outline Transaction Level Modeling (TLM): Motivation

– Historic and emerging trends in electronic system design

– SystemC as language for TLM

TLM: Introduction– Modeling basics

Communication Computation

– Consistency between TLM and RTL

– Applications

Conclusions

9

SystemC as Modeling Language

Challenges:– Tight interaction between HW and SW development

– Large systems to be modeled

Abstraction level beyond RTL required– Our solution: SystemC (C++ library)

Suitable for HW and SW development• Naturally inherits SW aspects• Adds features for HW modeling (parallelism, HW signals, etc.)

Applicable to large systems• Supports abstraction well due to power of C++

Includes simulation kernel• Combination of model and simulator in one executable

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Outline Transaction Level Modeling (TLM): Motivation

– Historic and emerging trends in electronic system design

– SystemC as language for TLM

TLM: Introduction– Modeling basics

Communication Computation

– Consistency between TLM and RTL

– Applications

Conclusions

11

Bus at Transaction Level: function call

write(addr, data)read(addr, data)

initiator target

Communication: Abstraction

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RX/TX

valid

addr

data

targetinitiator

Bus at RT Level: signal protocol

e.g. TLM 2

Transaction Level does not define a precise level of abstraction

customHW

HW signals still possible

Basic idea of transaction level modeling (TLM):– Hide details of communication protocols– Represent communication transactions by function calls

More general: Hide HW implementation details

1

Communication: Timing

Programmer’s View (PV)– Non-blocking transaction function calls

Focus: functionally correct sequence of function calls Time not modeled explicitly

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PV

initiator target

Communication: Timing Example

write(addr, dat)

write(addr, dat)

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Communication: Timing

Programmer’s View (PV)– Non-blocking transaction function calls

Focus: functionally correct sequence of function calls Time not modeled explicitly

Programmer’s View with annotated Timing (PVT)– Non-blocking transaction function calls

Transaction target yields delay time as return value Initiator lets simulation time advance by given amount

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initiator target

PVTPV

initiator target

Communication: Timing Example

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t0

t0+d

d

write(addr, dat)

write(addr, dat)

write(addr, dat, d)

write(addr, dat, d)

t

Communication: Timing

Programmer’s View (PV)– Non-blocking transaction function calls

Focus: functionally correct sequence of function calls Time not modeled explicitly

Programmer’s View with annotated Timing (PVT)– Non-blocking transaction function calls

Transaction target returns delay time Initiator lets simulation time advance by given amount

Cycle Callable (CC)– Blocking transaction function calls

Alignment with a periodic clock signal

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CC

initiator targetinitiator target

PVTPV

initiator target

Communication: Timing Example

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t0

t0+d

d

write(addr, dat)

write(addr, dat)

write(addr, dat)Tclk

write(addr, dat)

write(addr, dat, d)

write(addr, dat, d)

t t

Efficiency vs. Accuracy

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accuracy

efficiency

TLM 2 LTPV

CC

PVT

TLM 2 AT

Outline Transaction Level Modeling (TLM): Motivation

– Historic and emerging trends in electronic system design

– SystemC as language for TLM

TLM: Introduction– Modeling basics

Communication Computation

– Consistency between TLM and RTL

– Applications

Conclusions

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Computation: Timing

Clocked– Periodic clock event providing temporal pattern

– Units triggered each cycle

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t

Computation: Timing Examle

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timer

clk cnt rdy

cnt = 2> 0

cnt = 1> 0

cnt = 0== 0

Tcnt = 3

> 0

clock events

0clk 1 toggling

signal

0

1Xrdy

Computation: Timing

Clocked– Periodic clock event providing temporal pattern

– Units triggered each cycle

Event-driven– Units react to events (from transactions, signal changes, etc.)

– Events scheduled on demand for certain points in time

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t

Event-driven

Computation: Timing Examle

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cnt = 3> 0

cnt = 2> 0

cnt = 1> 0

cnt = 0== 0

clk0

1

tT

0

1Xrdy

clock events

togglingsignal

3 Tcnt = 3

!= 0

0

1Xrdy

clkclockperiod

timer eventtransaction event

Clocked

= T

Combinationsof

modeling styles

When to Apply What Modeling Style?

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Modeling style depends on required level of detail– HW with tight feedback loops

CC– Hardware-dependent SW

PVT, possibly with selected HW blocks in CC fashion Synchronization wrappers PVT CC

– SW PVT with simplified HW models

Event-driven Clocked

Computation

CC

PV

PVT

Com

mun

icat

ion

Stream-Driven Models

Stream-driven paradigm (Kahn Process Networks, KPNs)

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P1

input

output

P Process: Triggered by availability of data

Infinite FIFO

P2

P3

No notion of time!

popular for data flow modeling

Embedding KPN in TLM

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data out FIFO

data in FIFO

timerclock

ready

transaction

TL wrapper adds timing to untimed KPN

t = t0t = t0 +

Outline Transaction Level Modeling (TLM): Motivation

– Historic and emerging trends in electronic system design

– SystemC as language for TLM

TLM: Introduction– Modeling basics

Communication Computation

– Consistency between TLM and RTL

– Applications

Conclusions

28

Consistency Between TLM and RTL

Ensure consistency TL model RTL implementation– Code generation from spec

Interface (registers, memories, ports)• TLM / RTL: stub models• SW: register / memory access functions

Function• State machines: UML TLM / RTL

– High-Level Synthesis Requirements on input model: clocked, wire accurate

– Assertions Ensure essential properties

– Common testbench

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Common Testbench: RTL in TLM

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TLM

RTL

target_2

bus model

target_1

transactions

transactorTLMRTL

signals

initiator

typetranslator

• Transactions signals: transactors (FSMs)• Incompatible signal types: type translators (no internal states)• Compatible signal types: direct connect

RTL in TLM: Test RTL implementation in system context

TLM in RTL: Test TL model in legacy RTL testbenches

Outline Transaction Level Modeling (TLM): Motivation

– Historic and emerging trends in electronic system design

– SystemC as language for TLM

TLM: Introduction– Modeling basics

Communication Computation

– Consistency between TLM and RTL

– Applications

Conclusions

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Applications

TLM up to 100x faster than RTL Simulate entire system– Check correct system functionality

Assertions Signal traces Event logs Program traces

– Quantitative analyses Inspect statistics collected by modeled units

• CPU cores• Buses• Custom HW

– SW development / debugging Target SW debugger

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DSPblock 1

DSPblock 2

DSPblock N

CPU FSM

…

control/state

control/state

Check of Transmitter Performance

Typical performance simulation– 1 GSM frame (approx. 3.5 ms)

RTL: 30min TLM: 35sec

Speedup: 50x33

HW focus:– PVT/CC TL model: bit and cycle true signal chain

symbolgenerator

signalanalysis

timinganalysis

Core Selection

Uncached core with expensive on-chip memory

Simulate UMTS data transmission on both architectures

Cached core required 20% faster clock

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1000 1200

MHz

0

cacheduncached

1400 slots

cached core with cheap off-chip memory

Port of 3.5G Signal Processing SW

Challenge: – General purpose core replaced by dedicated DSP

Efforts:– Update system simulation model: 1 day

– Port software to DSP: 1 month

Benefit:– Software available several months before silicon

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Outline Transaction Level Modeling (TLM): Motivation

– Historic and emerging trends in electronic system design

– SystemC as language for TLM

TLM: Introduction– Modeling basics

Communication Computation

– Consistency between TLM and RTL

– Applications

Conclusions

36

Conclusions

Transaction level modeling (TLM):– Enables simulation of today’s complex electronic systems

– Common ground for SW and HW development

– More an art than a science Leaves and requires a great deal of modeling flexibility

– Has become indispensible in Infineon’s design flow

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Thank you!

Extra Material

Cache trade-off analysis

Performance analysis

Core models

SW success stories

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Optimal cache size?

Modify cache size and re-simulate testcases

Cache larger than 4kB not justified here

Cache Trade-off Analysis

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0 4 8 16 32

20

30

10

CPU load [MHz]

cache size [kB]0

Question: Enough performance for 3.5G data transmission?

Scenario: Run critical testcases, analyze core statistics

Result: Plenty of headroom available

Performance Analysis

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0 2 4 6data rateuplink

[Mb/s]

10

0

20

30

40

50 downlinkdata rate[Mb/s]

CPU load [%]

5.410.7

2.71.3

Core Models

CPU models essential for core-based designs– Instruction set simulator (ISS)

Emulates behavior of target core on host CPU Accurate Not very fast

– Performance optimized model Maps instructions of target core to native functions of host CPU Fast execution High costs

– CPU interface model Covers HW interface of target core (registers, interrupts, reset) SW code is compiled for native CPU

• Before compilation: HW accesses are mapped to transactions Fast, cheap Limited timing accuracy

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SW Success Stories 3.5G signal processing

– Challenge: General purpose core replaced by dedicated DSP

– Efforts: Update system simulation model: 1 day Port software to DSP: 1 month

– Benefit: Software available several months before silicon

3.5G control code– Challenge:

Verification: power-up, boot phase, host/device communication

– Required model quality: Full functional coverage Simulation speed > 1/20 HW speed

– Benefit: Control code debugged prior to silicon availability 42