tri-mode ethernet mac & 1g/2.5g ethernet pcs/pma or …tri-mode ethernet mac v9.0 pg051 and 1g/2.5g...
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Tri-Mode Ethernet MAC & 1G/2.5G Ethernet PCS/PMA or SGMII in IP Integrator
© Copyright 2018 Xilinx
The following example shows a Tri-Mode Ethernet MAC extended to use 1G/2.5G Ethernet
PCS/PMA or SGMII on a Kintex UltraScale device in IP integrator captured packets in
Wireshark.
It includes detailed steps for an example generated in Vivado 2018.2. Tri-Mode Ethernet MAC
v9.0 PG051 and 1G/2.5G Ethernet PCS/PMA or SGMII v16.1 PG047 are targeted on KCU105
Evaluation Platform
Tri-Mode Ethernet MAC v9.0 and 1G/2.5G Ethernet PCS/PMA or SGMII v16.1 on KCU105
Evaluation Platform
Vivado project steps:
1. Select “Create New Project” in Vivado 2018.2 and choose the KCU105 Evaluation Platform shown as below, then click on OK
Figure 1: Creating a Vivado Project for a KCU105
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© Copyright 2018 Xilinx
2. In Vivado, click on ‘Create Block Design’.
Figure 2: Creating Block design in IP Integrator
3. Using the Add IP option, add the Tri Mode Ethernet MAC as show in figure 3:
Figure 3: Adding IP
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© Copyright 2018 Xilinx
4. Configure the TEMAC and generate the core as show below:
Figure 4: TEMAC configuration
5. Similarly, Using the Add IP option, add 1G/2.5G Ethernet PCS/PMA or SGMII:
Figure 5: Adding IP in IP Integrator
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© Copyright 2018 Xilinx
6. Configure the PCS/PMA and generate the core as show below:
Figure 6: PCS/PMA configuration
7. Both Tri-Mode Ethernet MAC and 1G/2.5G Ethernet PCS/PMA or SGMII are added to
IP Integrator:
Figure 7: Added IPs in IP Integrator
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© Copyright 2018 Xilinx
8. Connect the Tri-Mode Ethernet MAC and 1G/2.5G Ethernet PCS/PMA or SGMII as
shown below and validate the design.
Figure 8: Complete block design in IP Integrator
9. The Block Design is instantiated in (TEMAC/Ethernet subsytem) core generated example
design as shown in the following figure:
Figure 9: Block design instantiated in core generated example
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© Copyright 2018 Xilinx
10. Run Behavioral simualtion as show below:
Figure 10: Behavioral Simulation
Simulation Results:
Figure 11: Behavioral Simulation
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© Copyright 2018 Xilinx
Simulation Results:
Figure 12: Behavioral Simulation
Simulation Results:
Figure 13: Behavioral Simulation
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© Copyright 2018 Xilinx
11. Synthesize the design and assign pin locations. Please refer to the following figure:
Figure 14: Synthesize the deisgn and assign pin location
Figure 15: Synthesize the deisgn and assign pin location
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© Copyright 2018 Xilinx
12. Implement the design and generate the bit stream:
Figure 16: Implementation and bit stream generation
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© Copyright 2018 Xilinx
13. Open hardware manager and configure the bit stream on the KCU105 board.
Figure 17: Hardware manager.
Figure 18: Hardware manager.
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© Copyright 2018 Xilinx
Capture the signals in Logic Analyzer:
Figure 19: ILA.
Capture the signals in Logic Analyzer:
Figure 20: ILA.
SFP connector:
The SFP to RJ45 connector is connected between KU105 SFP1 and the RJ45 cable, which is
connected to the PC to monitor packets in Wireshark.
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© Copyright 2018 Xilinx
14. Packets captured in Wireshark:
Figure 21: Packets captured in Wireshark
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