tri-gate fully-depleted cmos transistors: fabrication, design...
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Tri-Gate Fully-Depleted CMOS Transistors: Fabrication,
Design and LayoutB.Doyle, J.Kavalieros, T. Linton, R.Rios
B.Boyanov, S.Datta, M. Doczy, S.Hareland, B. Jin, R.Chau
Logic Technology DevelopmentIntel Corporation
2
Outline of Presentation
• Introduction − Different Depleted Substrate Transistor (DST)
Architectures
• Experimental Results
• Computer Simulation Results− Dimensional Analysis− Importance of Corner Effects
• Tri-Gate Layout Analysis
• Summary
3
Transistor Architectures
Single-Gate Planar
L
Si HSi
g
Si
GateSourceDrain
~ Lg/3
Double-gate (e.g. FINFET) Non-Planar
WSi
Lg
HSi
Isolation
Gate 1
Gate 2
Source
Drain
Tri-gateNon-Planar
WSiLg
HSiGate 1
Gate 2
Gate 3
Source
Drain
WSi ~ 2Lg/3HSi ~ WSi ~ Lg
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Tri-gate Transistor
WSiLg
Top GateSide Gate
Side Gate
HSi S/DD/S
Gate
Top Gate
Side Gate
Side Gate
Body controlled on three sides by adjacent gates-> Excellent electrostatic control of body
5
Experimental Tri-Gate Process
• Starting Si thickness = 50nm
• BOX thickness ~ 200nm
• Well implants
• N2O sacrificial oxidation
• Physical Tox = 1.5nm
• Poly thickness = 100nm
• Raised source-drain
• Nickel salicide
Top Gate
Side Gate
Side Gate
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60nm NMOS Tri-Gate Transistors
1E-08
1E-07
1E-06
1E-05
1E-04
1E-03
1E-02
0 0.4 0.8 1.2Vg (Volts)
Id (µ
A/µ
m)
Vd=0.05V
Vd=1.3V
0.0E+00
2.5E-04
5.0E-04
7.5E-04
1.0E-03
1.3E-03
0 0.4 0.8 1.2
Id (A
/µm
)
Vg=1.3V
Vg=1.1V
Vg=0.9V
Vd (Volts)
• Idsat = 1.23mA/µm and Ioff = 40nA/um at Vcc = 1.3V• Subthreshold slope = 72mV/decade• DIBL (Drain Induced Barrier Lowering) = 35mV/V
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60nm pMOS Tri-Gate Transistors
Gate Voltage (V)
Dra
in C
urre
nt (A
/µm
)
0.E+001.E-042.E-043.E-044.E-045.E-046.E-04
-0.8 -0.4Drain Voltage (V)
Dra
in C
urre
nt (A
/µm
)
1E-091E-081E-071E-061E-051E-041E-03
-1.2 -0.8 -0.4 0
Vd=1.3V
Vd=0.05V
-1.2 0
• Idsat = 520 µA/um and Ioff = 24nA/um at Vcc = 1.3V• Subthreshold slope = 69.5mV/decade• DIBL (Drain Induced Barrier Lowering) = 48mV/V
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Double Gate-likeUnderstanding Tri-Gate Behavior• Device simulator
- Full 3D single-carrier solution using DESSISdevice simulator
- Hansch quantum correction model applied- Intel 2.2 Ghz Xeon processor takes about 1
minute/bias point for an 18000 node mesh• Simulated structures
- Lg=60 nm / HSi=60 nm / WSi=60 nm- Lg=30 nm / HSi=30 nm / WSi=30 nm- Electrical Tox varies from 22 to 34 A
• - Corner radius varied from 0 (right-angle) to 16 nm- Adjusted doping adjusted to get Ioff ~100 nA/µm
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Simulation of Lg=HSi=WSi=60nm1.E-03
Vd=0.05V
Vd=1.3V
DIBL=56 mV/V
S/S (0.05V)= 72.5mV/dec
S/S (1.3V)= 76mV/dec
1.E-04
1.E-07
1.E-06
Id (A
) 1.E-05
1.E-08
1.E-090.0 0.3 0.6 0.9 1.2
Vg (V)
Tri-Gate device shows full depletion effects
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1.0E-03
Simulation of Lg=HSi=WSi=30nm
Vd=0.05VVd=1.0V
DIBL=62 mV/V
S/S (0.05V)= 76mV/dec
S/S (1.3V)= 76mV/dec
1.0E-04
1.0E-05
1.0E-06Id (A
)
1.0E-07
1.0E-080.0 0.2 0.4 0.6 0.8 1.0
Vg (V)
Lg = WSi = WSi= 30nm device shows excellent electrostatics
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Body Scaling Vs DST Architecture
Single-Gate
Double-Gate
Tri-Gate0
10
20
30
HSi=0.33*Lg
WSi=0.66*LgLg =30nm
Lg =20nm
Lg =15nm
(Hsi
, WSi
(nm
)M
inim
um B
ody
Dim
ensi
on
Tri-Gate body size more relaxed than single-gate or Double-Gate
HSi=WSi=Lg
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Tri-Gate Device Understanding• TCAD simulations partitioned
into 3 distinct regions:
Top channelSidewall channel
Corners
Oxide
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Components of Current
Vg (V)
Id (A
/ µm
)
1.0E-09
1.0E-08
1.0E-07
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
0.0 0.2 0.4 0.6 0.8 1.0
Non-CornerTotal
Corner
Vd=1.0V
Vd=0.05V
Corner device shows much improved S/S & DIBL over non-corner devices because of proximity of adjacent gates
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Components of Current
0.0%
20.0%
40.0%
60.0%
100.0%
0.0 0.6Vg (V)
% o
f Tot
al C
urre
nt
CornerNon-Corner
Vd=0.05V
Vd=1.0V80.0%
0.2 0.4 0.8 1.0
• Corner device dominates at low Vg’s • Non-Corner device (top & side) dominates at high Vg’s
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Physics of Corner Device
R=8nmVg=0.5V, Vd=1.0VCut at midpoint along channel
Proximity of the two gates at the corner give the nearly-ideal characteristics of the corner device, and the high current density
16
Physics of Tri-Gate Device
hDensity
1E+181E+161E+141E+121E+101E+081E+06100001001
Top Gate
Si
Drain
Lg =30nm
T Si=
30n
m
hDensity
1E+181E+161E+141E+121E+101E+081E+06100001001
Top Gate
Si
Drain
Lg =30nm
T Si=
30n
m
SourcehDensity
3E+04
(well conc. = 8E+18)
• All 3 gates control the depletion regions in the Tri-Gate device to make the Si body fully depleted
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Importance of Corner Profile
1.E-12
1.E-10
1.E-08
0 0.2 0.4 0.6 0.8 1Vg (V)
Cor
ner C
urre
nt (A
/µm
)
R=0 nmR=5 nmR=10 nmR=15 nmR=20 nmR= infinity
Gate
BodyBody
Radius R
1.E-02
1.E-04
1.E-06
R is the radius of curvature of the corner
Corner profile affects the sub-threshold characterisics of the corner device
18
Layout Implications: Fabricating Different Widths
Poly
Fins
To meet different required widths for transistors, multi-Tri-Gate fins are required. What are the layout width implications?
19
Layout Considerations
Planar Transistor
Zeff = Z
Tri-Gate Transistor
Fins
Zeff = 0.6Z
For a given pitch, total current per unit layout-width of the Tri-gate transistor has only 0.60X the channel width of the standard transistor
•Need to use spacer-litho technique to double the # of fins for a given pitch to increase total current
(R.Chau et al., SSDM, Nagoya, Japan, Sept. ,2002)(C-M Hu et al., IEEE Trans El Dev.,Vol. 49, pp. 436-441, 2002)
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Spacer-Defined Fins
FinsFins
Zeff = 0.6Z
Oxide Blockswith nitride spacers
Zeff = 1.2 Z
Litho-defined Fins For the same pitch, # ofspacer-defined fins doubles that of litho-defined fins
Oxide blocks to define spacer-masks for forming Si fins
• Use of spacer-litho technique enables the Tri-gate transistor to have 20% more total current per unit layout-width than the standard planar transistor
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Conclusions
• Tri-Gate transistors have been fabricated and achieve excellent drive current with near-ideal DIBL, S/S.
• Tri-Gate corners are responsible for the excellent sub-threshold slope, DIBL characteristics, as well as relaxing the body dimensions compared to double-gate devices.
• In addition to the corners, the top-gate and sidewall channel regions are important in achieving optimal device performance.
• Layout analysis shows Tri-Gate achieves 20% higher total current per unit layout area than standard planar devices.
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