transistor amplifiers

AEI302.16 1

• Amplifier raises the level of a weak signal.

• No change in the wave shape.

• No change in the frequency of the input signal

What is an amplifier?

AEI302.16 2

• The signal is generally the o/p of a transducer like

microphone, thermo couple.

• It is very weak.

• It must be amplified before feeding to the loud speaker etc.

Why we need Amplification?

AEI302.16 3

Block diagram of an Amplifier

AEI302.16 4

• Common Base Configuration

• Common Emitter Configuration

• Common Collector Configuration

Different Configurations of Transistor

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In how many regions a transistor can be operated?

1. Cut off region

2. Active region

3. Saturation region

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Cutoff region Emitter junction & Collector junction are in Reverse Biased

Active regionEmitter junction Forward Biased & Collectorjunction Reverse Biased

Saturation regionEmitter junction & Collector Junction are in Forward Biased

AEI302.17 7

CIRCUIT OF C.E.AMPLIFIER

AEI302.17 8

Working of C.E.Amplifier

• Base emitter junction is forward biased by VBB.

• Collector base junction is reverse biased by VCC.

• During positive half cycle of signal forward bias is increased.

• Hence base current IB is increased.

• So Ic increases and ICRC drop increases.

• The output VCE decreases

as VCE = VCC - ICRC

• There is a phase shift of 180º between input and output.

AEI302.17 9

Output Signal

Input Signal

Wave Forms of Input and Output Signals

AEI302.17 10

Salient points of C.E.Amplifier

• Moderately low input resistance(1 k to 2 k).

• Moderately high output resistance(50 k).

• High current gain.

• Very high voltage gain.

• Very high power gain.

• Input and output signals are 180° out of phase.

AEI302.17 11

Comparison Of Amplifier Configurations

NoYesNoPhase Reversal6.

LowHighVery HighOutput Impedance

5.

Very HighHighLowInput Impedance4.

Low HighHighPower Gain3.

Nearly UnityVery HighHighVoltage Gain2.

Very HighHighNearly UnityCurrent Gain1.

C.B C.E C.C

ParticularsS.No

AEI302.17 12

WHICH CONFIGURATION IS BEST SUITED AS AN AMPLIFIER ?

C.E.CONFIGURATION

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• its input and output impedances are suitable in many applications.

• it offers current gain,voltage gain,power gain.

Why C.E.Configuration Is Commonly Used?

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The operating conditions of a transistor are determined by

• VCE collector to emitter voltage

• IC collector current

Concept of DC Load Line

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The value of IC for a given VCE can be known

• From output characteristics of a transistor.

• From D.C.Load Line .

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Which one is convenient ?

• D.C. Load Line

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• It is a graph drawn between collector current IC and

collector to emitter voltage VCE for a given VCC and RC.

What is a D.C.Load Line ?

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• VCE is taken on X-axis

• IC is taken on Y-axis

To draw the d.c.Load Line of a transistor

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• Only two points cut-off point and saturation point are required.

• Line joining these two points is known as load line.

How we can draw the D.C.Load Line?

AEI302.18 20

Determination of cut-off point

The output equation of a transistor in C.E.mode is VCC = VCE + ICRC

When transistor is cut-off IC = 0

So VCC = VCE

Hence cut-off point = (VCE, 0)

AEI302.18 21

Determination of Saturation point:

In Saturation VCE of a transistor is zero.

Hence VCC = ICRC

Ic = VCC / RC

Hence Saturation point = (0,VCC / RC)

AEI302.18 22

Cut-off point

Saturation point(0 ,VCC /

RC)

(VCE,0)D.C.Load Line

VCE

IC

Active region

AEI302.18 23

• D.C.Load line represents all possible DC

operating points of a transistor for a specified

values of Vcc & Rc

AEI302.18 24

• The lower end of the D.C.Load Line is called cut-off

point.

• The upper end of D.C.Load Line is saturation point.

• The entire region between these two points indicates

active region.

AEI302.18 25

In a C.E. Configuration the Vcc = 12v, Rc = 3k

Find D.C.Load Line ?

Problem

AEI302.18 26

SOLUTION

The output equation of a transistor is VCC = VCE + ICRC

12 = VCE + 3 * IC

When IC = 0; VCE = 12 v

The Coordinates of cut off point are (12v , 0)

When VCE = 0

IC = VCC

/ RC

= 12 v / 3 kΩ

= 4 mA

The Coordinates of saturation

point are (0, 4mA)

AEI302.18 27

Active Region

(12,0)

(0,4mA)

D.C.Load Line

Cut-off point

Saturation point

VCE

IC

AEI-302.19 28

What is the difference between D.C & A.C load

lines?

AEI-302.19 29

A.C LOAD LINE

• A.C Load Line gives the values of ic and vce when

an A.C signal is applied.

AEI-302.19 30

Circuit of a C.E .Amplifier

RE

AEI-302.19 31

For A.C analysis

• All capacitors in the circuit may be considered as short circuits.

• The collector resistance Rc comes parallel with load

Resistor RL and forms the A.C load resistance.

• Effective Load for A.C signal is

Rac = Rc || RL = RcRL / Rc+RL

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• When signal is applied “Q”point swings

along ac load line.

AEI-302.19 33

Drawing an A.C load line

• The output equation of transistor is

Vce + ic Rc = 0 (1)

Ic = -Vce / Rac (2)

A.C collector voltage is

Vce = vCE – vCEQ (3)

Substituting these values in equation (1)

vCE – VCEQ + (ic-ICQ)Rac = 0

Ic = ICQ + VCEQ / Rac – vCE / Rac

AEI-302.19 34

Determination of Cut-off & Saturation points

• In saturation vCE = 0

• Hence ic(sat) = ICQ + VCEQ/Rac

• ic(sat) = a.c saturation current

• ICQ =d.c Collector current

• VCEQ = DC collector - Emitter voltage .

• Rac = a.c load resistance

Saturation point

AEI-302.19 35

Cut-off point

• When transistor is cut-off ic equals to zero

• ICQ +vCEQ / Rac - vCE(cutoff) / Rac = 0

• vCE(cutoff) = vCEQ + I CQ Rac.

AEI-302.19 36

Line joining these two points is called A.C Load Line

• The maximum possible positive signal swing is ICQRac.

• The maximum possible negative signal swing is vCEQ.

It represents all possible a.c operating points.

AEI-302.19 37

AEI-302.19 38

PROBLEM

1. Draw the dc & ac load line for the C.E circuit shown in figure.

AEI-302.19 39

SOLUTION• D.C OPERATING POINT

• Vce(cutoff) = Vcc

= 20 v (Represents point B)

• I c(saturation) = Vcc / Rc+RE = 20 / (3+2)K

=4 mA (Represents point A)

• Line AB represents dc load line.

AEI-302.19 40

ICQ =4 mA / 2 = 2mA

(Taking “Q”at the centre of dc load line)

VCEQ = Vcc - ICQ(Rc+RE)

= 20 – 2 (3+2) = 10 v

A.C Load resistance = RC || RL

= 3 || 12

= (3*12) / (3+12)

= 2.4 K

CALCULATION OF AC LOAD LINE

AEI-302.19 41

Ic (sat) = ICQ + VCEQ / Rac

= 2 X 10-3+ 10 / 2.4= 6.17 mA

Hence saturation point = ( 0 , 6.17mA)

VCE(cut off) = VCEQ + ICEQ * RE

= 10 + 2 X 10-3 * 2 X 103

= 14.8 v

Hence cut off point = ( 14.8 v , 0).

Line joining CD is ac load line.

This line passes through “Q” point.

AEI-302.19 42

(20 v,) 0

B

A (0, 4 mA)

D (14.8 v, 0)

C (0, 6.17mA)

A.C.Load line

D.C.Load line

VCE

IC

Fig. 4

AEI302.20 43

Need for biasing

• For normal operation of a transistor amplifier circuit, the transistor must be biased so that it operates in the active region (linear) of it’s characteristics. That means

• Forward bias on the emitter-base junction

• Reverse bias on the collector-base junction

AEI302.20 44

For achieving faithful amplification the following

conditions should be satisfied

• 1. Proper Zero signal collector current IC.

• 2. Proper Base-Emitter voltage VBE at any instant .

• 3. Proper Collector-Emitter voltage VCE at any instant.

AEI302.20 45

What is meant by Zero signal collector current?

• The current following through a transistor in the absence of A.C

signal is known as Zero signal collector current IC.

AEI302.20 46

Condition 1

• Zero signal collector current IC should be equal to the

maximum collector current due to signal alone.

AEI302.20 47

For Example:

• An input signal causes a peek collector current of 1mA; Then Zero

signal collector current can be either 1mA or more than 1mA.

AEI302.20 48

IC > Maximum current due to A.C.Signal

Here IC= 1mA

• The maximum collector current due to signal is 0.5mA.

• So the total collector current varies between 1.5mA to 0.5mA.

1mA

1.5mA

AEI302.20 49

When IC = Maximum current due to A.C.Signal

Here IC= 1mA

Maximum current due to A.C.Signal is 1mA.So total current varies between 2 mA and 0 mA

0mA

1mA

2mA

AEI302.20 50

When IC< Maximum current due to A.C.Signal

Here IC= 0.5mA

Maximum current due to A.C.Signal is 1mA Collector current IC becomes –ve during some part of input signal. • It means output waveform is clipped during that part. • Hence there is distortion in output.

-0.5mA

0.5mA0.m

A

1.5mA

AEI302.20 51

We can conclude that:

• For faithful amplification

Zero signal collector current IC maximum collector

current due to signal alone

AEI302.20 52

Condition - 2

Minimum proper Base -Emitter voltage .

• The Base – Emitter voltage VEBshould not fall below

• 0.3v for Germanium transistors.

• 0.7v for Silicon transistors.

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• If VBE falls below these values during any part of the signal,

that part will be amplified to a smaller extent and faithful

amplification is not possible.

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The conditions 1 & 2 ensures

• Emitter-Base junction remains properly forward biased during

all parts of input signal.

AEI302.20 55

Condition - 3

Minimum proper Collector-Emitter voltage should not fall below knee voltage.

• 0.5v for Germanium Transistors.

• 1.0v for Silicon Transistors.

AEI302.20 56

• If VCEis less than knee voltage

• Collector Base junction is not properly reverse biased.

• Amplification is not uniform.

• Causes distortion in o/p waveform.

AEI302.20 57

The condition 3 ensures

• The Collector-Base junction remains properly reverse biased

during all parts of input signal.

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• The proper flow of zero signal collector current and

maintenance of proper colletor - emitter voltage during the

passage of signal is called TRANSISTOR BIASING

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A Transistor can be biased

• With the help of a battery.

• Associating a circuit with the Transistor.

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The second method is more efficient:

• The circuit used for Transistor biasing is called

BIASING CIRCUIT.

AEI302.20 61

• Transistor Biasing is very essential for proper operation

of a Transistor.

AEI302.20 62

PROBLEM

Find the maximum input current permissible

for faithful

amplification of a silicon transistor having RC

= 4 kΏ and

VCC= 10 v. The knee voltage = 1 v. β = 50.

AEI302.20 63

SOLUTION

The output equation of transistor is

VCC =VCE + IC RC

10 = 1 + 4*103 * IC

Ic = (10-1)/ (4*103)

= 2.25 mA

IB = IC / β

= 2.25 mA / 50

= 45 μA

AEI-302.21 64

OPERATING POINT

o VCE

Dc Load line

Ac Load Line

Ic

VccRc

AEI-302.21 65

• It is a point on the DC load line which specifies

collector current IC and collector emitter voltage

VCE that exist when no signal is applied.

• The operating point is also known as “Quiescent

point” or “Q” point.

OPERATING POINT

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• When an input signal is applied, base current varies

according to the input signal.

• This causes collector current IC and out put voltage VCE

to vary.

• For faithful amplification selection of operating point is

very important.

OPERATING POINT

AEI-302.21 67

A transistor should be biased to operate within the maximum limits of the following.

• Maximum Collector Current ICmax)

• Maximum Collector voltage VC(max)

• Maximum Collector dissipation PC(max)

• Maximum Emitter –Base voltage VBE(max)

AEI-302.21 68

VCE

IC

Q2

QQ1

Output characteristics

DC Load Line

DC Load line is drawn on output characteristics Fig 1

AEI-302.21 69

As shown in fig.1 operating point is the

intersection of

D.C load line on O/P characteristics of a

transistor. There are several operating

points.

AEI-302.21 70

•If operating point is selected at Q1 near the cut off region,

output current Ic, and voltage VCE clipped at the negative

peaks for a sinusoidal varying input signal.

How the operating point is selected?

•If operating point is selected at Q2, near

the saturation region, the output signal

would be clipped at the positive peaks for a

sinusoid ally varying input signal.

AEI-302.21 71

•Selecting the operating point on the center of D.C. Load

Line is not a rule.

•Generally operating point is selected at the centre of DC load line.

•For large signal amplifiers “Q” point can be

taken on the center of D.C. Load Line.•For small signal amplifiers where the input signal excursion is very small.”Q” point can

be selected any where on D.C. Load Line depending on circuit conditions.

How the operating point is selected

AEI-302.21 72

PROBLEM

In a transistor circuit RC= 5 k Ώ and

VCC = 10v. The zero signal collector

current is 1.0 mA. Find the operating

point.

AEI-302.21 73

VCC =VCE + ICRC

VCE = VCC – ICRC

= 10 – (1 *10-3 * 5*103)

= 5 v.

The operating point is ( 5 v,

1mA)

Solution

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Stabilization is nothing but keeping the

Q- point (operating point)stable irrespective of

the variation in temperature, β of the

transistor and vbe

STABILIZATION

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•In a transistor amplifier fixing suitable operating point is not sufficient.

•The operating point should remain stable.

AEI302.22 76

Stabilization of operating point is essential because, it may change due to

Instability of Collector current IC. With

temperature ,Ie., ICBO or ICO

• Variation of VBE

• Change of β with transistor replacement.

AEI302.22 77

Instability of IC

In a CE amplifier

IC = β IB + (1+β) * ICO.

The reverse saturation current ICO increases at a rate

of 7 % / ° C for both Ge & Si transistors.

Or

ICO doubles for every 10 °C rise in temperature.

AEI302.22 78

Variation of VBE with temperature /change of transistor.

Base-Emitter voltage VBE decreases at a rate of 2.5 mv per°C.

AEI302.22 79

Change of β factor

• The value of β is not same for any two

transistors even of same type.

• For Ex : BC147 is a Silicon transistor with β

varying from 100 to 600.

AEI302.22 80

All the above factors can cause the bias point to shift

from the values originally fixed.

AEI302.22 81

THERMAL RUNAWAY

• The collector current IC increases with increase in temperature.

• This increases power dissipation and further increases the temperature, and it will increase icbo and hence finally ic.

• Being a cumulative process it can result in burn –out of transistor.

AEI302.22 82

The self destruction of an un-stabilized transistor is called

THERMAL RUNWAY

AEI302.22 83

Means of achieving stability for operating point

• Stabilization techniques.

• Compensation techniques.

AEI302.22 84

STABILIZATION TECHNIQUES

• Use a resistive biasing circuit.

• It permits variation of base current IB to maintain

collector current Ic constant.

• IC is made constant against variations in ICO,VBE and β

AEI302.22 85

COMPENSATION TECHNIQUES

• They use temperature sensitive devices such as diodes, transistors & thermisters

• They produce compensating voltages and currents and make operating point stable.

AEI302.23 86

On what factors operating point is dependent?

• ICO Reverse current

• VBE Base Emitter voltage

Current amplification factor

AEI302.23 87

The degree of stability of IC against variations in ICO ,VBE &

β is expressed in terms of stability factors.

Stability factor

AEI302.23 88

The different stability factors

• s

• sv (s|)

• s (s||)

AEI302.23 89

Stability factor S

• Stability factor “S” is defined as the rate of change of

collector current IC with respect to change in ICO keeping

and VBE constant.

• S = dIC / dICO (At constant and VBE)

AEI302.23 90

The General expression for S

The expression for collector current Ic is

IC= β *IB + (1+ β) ICO

Differentiating w.r.t. IC

1 = β * dIB/dIC + (1+ β) * dICO / dIC

1 = β * dIB/dIC + (1+ β) / S

S = (1+ β) / (1 – (β * dIB/dIC))

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• The ideal value of S is unity.

• The smaller the value of S the higher is the stability.

AEI302.23 92

In CB amplifier the output current IC is given by

IC = *IE + ICO

Differentiating w.r.t ICO

dIC / dICO = 1.

C.B amplifier achieves the lowest value of ‘S’.

So C.B amplifier does not require stabilization.

AEI302.23 93

Stability factor SV

• It is defined as the rate of change of collector current IC

with respect to change in VBE keeping ICO and constant.

• SV = dIC / dVBE (at constant ICO and )

AEI302.23 94

Stability factor S

• Stability factor S is defined as the rate of change of

collector current ICwith keeping ICO and VBE constant.

• S = dIC/ d (at constant ICO & VBE)

AEI302.23 95

• The expression for collector current IC is

• IC = * IB + (1+ )ICO

• Differentiating w.r.t. IC

• 1 = *dIB / dIC + IB * d /dIC + ICO d /dIC

• 1 - * dIB / dIC = d /dIC (IB + ICO)

• (1/S) (IB + ICO) = 1 – ( *dIB /dIC)

• S = (IB + ICO) / 1 – ( * dIB /dIC)

General Expression for S