timing analysis
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George Mason University
Timing Analysis
ECE 545Lecture 8a
2
Required reading• P. Chu, RTL Hardware Design using VHDL
Chapter 8.6 Timing Analysis of a Synchronous Sequential Circuit
Chapter 16.1 Overview of a Clock DistributionNetwork
Chapter 16.2 Timing Analysis with Clock Skew
3ECE 448 – FPGA and ASIC Design with VHDL
Hold & Setup TimeMetastability
4
Violation of Hold or Setup Time
5
Response of a Flip-Flop to Timing Violation
There exists a third and unstable point of equilibrium between the two stable states representing the binary states 0 and 1 respectively.
6
Points of Equilibrium in Flip-Flops and Latches
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Patterns of Metastable Behavior
8
Response to Timing Violation
9
Impact on Downstream Circuitry
10ECE 448 – FPGA and ASIC Design with VHDL
Clock Skew
11
Clock Skew
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Clock Skew Map for a Cell Processor
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Incorrect Clock Tree Layout – Narrow Meander
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Optimized Clock Tree Layout – H Tree
15
Clock Skew - Summary
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