tila: timing-driven incremental layer assignmentbyu/papers/c40-iccad2015-lplan-slides.pdf · 1...

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TILA: Timing-Driven Incremental Layer Assignment

Bei Yu1,2, Derong Liu1, Salim Chowdhury3, and David Z. Pan1

1ECE Department, University of Texas at Austin, Austin, TX, USA 2CSE Department, Chinese University of Hong Kong

3Oracle Corp., Austin, TX, USA

Overview

t  Introduction t Problem Formulation t Algorithms t Experimental Results t Conclusion

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Introduction t  VLSI technology scales to deep submicron

›  Interconnect delay

t  Interconnect synthesis ›  Timing-driven routing ›  Global routing -- part of a timing convergence flow

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Global Routing Flow

3D Global Routing

2D Global Routing Layer Assignment

Introduction t  Layer assignment:

›  Assign segments to metal layers ›  Impossible to assign all segments on higher layers

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Wire

Via

Metal 1

LowerMetal Layers

IntermediateMetal Layers

TopMetal Layers

Previous Works on GR and LA

t  Many papers on global routing and layer assignment, e.g.

›  Routability-driven GR [Cho+, TCAD’07] ›  Timing-driven GR [Liu et al. TCAD’13] ›  Via count and overflow minimization during

layer assignment - NVM [Liu+, ASPDAC’11] ›  Delay-driven layer assignment [Ao+,

ISPD’13]

t  Limitations of previous layer assignment: ›  Most focus on via minimization ›  Via delays are often ignored ›  Net-by-net method may lead to local

optimality

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Layer Assignment

Timing Optimization (Buffering)

Detailed Routing

Post-Routing Optimization

Global Routing

Contributions of this Work

t  The first timing-driven incremental layer assignment (TILA) that integrates via delay

t  Solve multiple nets simultaneously

t  Incremental approach to provide fast turn-around-time

t  Lagrangian relaxation based optimization to improve total wire and via delay via min-cost flow iteratively

t  Multi-processing of K*K partitions for speed-up

t  Effectiveness demonstrated by ISPD’08 and industry benchmarks

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Model Description t  Timing model:

›  Elmore Delay (Cdown, R) ›  Consider both segment delay and via delay

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Via Delay Driver

Sink

Problem Formulation t  Timing-driven Incremental Layer Assignment (TILA)

›  Given initial layer assignment solution and critical ratio α  ›  Minimize: sum of segment and via delays of selected nets ›  Subject to: via capacity and edge capacity constraints

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n1

n2

n3 n1n2

n3

Non-Critical Nets: n1 n2 ; Critical Net: n3

One Example

TILA Algorithm t  Mathematical Formulation

t  Constraints: ›  Each segment should be assigned on one and only one layer

›  Edge capacity constraint:

›  Via capacity constraint:

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Segment Delay Via Delay

TILA Algorithm t  Lagrangian Relaxation Subproblem (LRS)

›  Solve the LRS iteratively

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Integrate via capacity constraint with Lagrangian Multipliers (LMs)

t  Linearize the quadratic term approximately:

›  Based on the values in previous iteration

t  Solve the LRS through a min-cost network flow model t  Satisfy the edge capacity constraint t  Guarantee one segment on one layer

TILA Algorithms t  Min-cost Flow Model

›  Inherent uni-modular property to ensure integer solutions ›  Directed Graph G (V,E)

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Pseudo Start Vertex Pseudo End Vertex

Segment Vertices Layer Vertices

Capacity: 1 Cost: 0 Capacity: edge capacity

Cost: 0 Capacity: 1 Cost: assigning penalty

TILA Algorithm

t Algorithm Flow

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Critical Ratio αInitial Layer Assignment

Solution

Initialize Cdown and LMs

Select nets with α

Solve LRS

Update Cdown and LMs

converge?

NY

End

Min-cost flow model

Improvement < Specified Ratio

Or Iteration number > MaxIter

Incremental Approach

t Critical & Non-critical Net Selection ›  Most Critical nets: improve the timing ›  Most non-critical nets: release more high layers

resources

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Most critical nets selection

Most non-critical nets selection

Select α%#nets withworst delay

Select#nets based ondelay and sharing edges

Re-assign selected nets

Nets Selection Flow

Calculate Net Delay

Speed-up Techniques

t Parallel Scheme ›  Divide grid model into K x K partitions ›  Recent results by peer threads can be considered

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4*4 partitions

Experimental Results t  Implemented the framework in C++ t  Tested on Linux machine with eight 3.3GHz CPUs t  Min-cost flow solver

›  LEMON open source graph library

t  Parallel computation with OpenMP ›  Default thread number as 6 and K set as 6

t  Evaluation on both academia and industrial benchmarks t  Performance Metrics

›  Average Delay ›  Maximum Delay ›  Via capacity violation# ›  Via#

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Evaluation on ISPD’08 Benchmarks t  Initial global routing input:

›  Generated by NCTU-GR 2.0 [Liu et al. TCAD’13]

t  Initial layer assignment: ›  From NVM [Liu et al. ASPDAC’11]

›  Targeting via number and overflow minimization

t  Wire resistance and capacitance values obtained from [Hsu et al. ICCAD’14]

t  Via resistance and capacitance normalized from industry t  Release 1% and 5% critical and non-critical nets

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Delay Comparison Results t  ISPD’08 Global Routing Benchmarks t  TILA-1%:

›  53% improvement by Dmax and 10% improvement by Davg

t  TILA-5%: ›  53% improvement by Dmax and 18% improvement by Davg

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Via Comparison Results t  ISPD’08 Global Routing benchmarks t  TILA-1%

›  OV# decreases by 7% and Via# increases by 3%

t  TILA-5% ›  OV# decreases by 11% and Via# increases by 12%

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Experimental Results t  Impact of different critical/non-critical ratio

›  Releasing 1% is enough for maximum delay ›  Trade-off between average delay and speed

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Dmax: max delay; Davg: average delay; run time

Industrial Benchmarks Results t  Industry tool to generate initial routing solution t  Use industry resistance and capacitance

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OV#: overflow number; Davg: average delay; Dmax: max delay; via#: total via number

Conclusion

t  We proposed a new Timing-driven Incremental Layer Assignment (TILA) algorithm

›  Select a subset of critical and non-critical nets

›  Lagrangian relaxation based global optimization

›  Min-cost network flow to solve iteratively

›  Multi-threading

t  TILA can work smoothly with any global router and adapt easily to future heterogeneous layer structures

t  New research needed to shed light on “classical” EDA problems

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