the von neumann architecture
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7/17/2019 The Von Neumann Architecture
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The Von Neumann The Von Neumann
ArchitectureArchitecture
Chapter 5.1-5.2Chapter 5.1-5.2
Von NeumannVon Neumann
ArchitectureArchitecture
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CMPUT101 Introduction (c) Yngvi Bjorns 2
Designing ComputersDesigning Computers
• All computers more or less based on the sameAll computers more or less based on the same
basic design, thebasic design, the Von Neumann ArchitectureVon Neumann Architecture!!
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CMPUT101 Introduction (c) Yngvi Bjorns 3
The Von Neumann The Von Neumann
ArchitectureArchitecture• Model or designing and building computers,Model or designing and building computers,
based on the olloing three characteristics"based on the olloing three characteristics"
1#1# $he computer consists o our main sub-s%stems"$he computer consists o our main sub-s%stems"• Memor%Memor%
• A&' (Arithmetic)&ogic 'nit#A&' (Arithmetic)&ogic 'nit#
• Control 'nitControl 'nit
• *nput)+utput %stem (*)+#*nput)+utput %stem (*)+#
2#2# rogram is stored in memor% during eecution.rogram is stored in memor% during eecution.
/#/# rogram instructions are eecuted se0uentiall%.rogram instructions are eecuted se0uentiall%.
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CMPUT101 Introduction (c) Yngvi Bjorns 4
The Von Neumann The Von Neumann
ArchitectureArchitecture
Memor%
rocessor (C'#
*nput-+utput
Control 'nit
A&'
tore data and programtore data and program
ecute programecute program
o arithmetic)logic operationso arithmetic)logic operations
re0uested b% programre0uested b% program
Communicate ithCommunicate ith
3outside orld3, e.g.3outside orld3, e.g.• creencreen• 4e%board4e%board• torage deicestorage deices• ......
6us
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CMPUT101 Introduction (c) Yngvi Bjorns 5
Memory SubsystemMemory Subsystem
• Memor%, also calledMemor%, also called 7AM7AM ((77andomandom AAccessccess MMemor%#,emor%#,
8 Consists o man% memor% cells (storage units# o a ied si9e.Consists o man% memor% cells (storage units# o a ied si9e.
ach cell has an address associated ith it" :, 1, ;ach cell has an address associated ith it" :, 1, ;
8 All accesses to memor% are to a speciied address.All accesses to memor% are to a speciied address.A cell is the minimum unit o access (etch)store a complete cell#.A cell is the minimum unit o access (etch)store a complete cell#.
8 $he time it ta<es to etch)store a cell is the same or all cells.$he time it ta<es to etch)store a cell is the same or all cells.
• =hen the computer is running, both=hen the computer is running, both8 rogramrogram
8 ata (ariables#ata (ariables#
are stored in the memor%.are stored in the memor%.
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CMPUT101 Introduction (c) Yngvi Bjorns
RAMRAM
• Need to distinguish beteenNeed to distinguish beteen8 thethe addressaddress o a memor% cell ando a memor% cell and
thethe contentcontent o a memor% cello a memor% cell
• Memor% idth (Memor% idth (==#"#"
8 >o man% bits is each memor%>o man% bits is each memor%cell, t%picall% onecell, t%picall% one b%teb
%te (?@ bits#(?@ bits#
• Address idth (Address idth (NN#"#"8 >o man% bits used to represent>o man% bits used to represent
each address, determines theeach address, determines themaimum memor% si9e ?maimum memor% si9e ? addressaddressspaces
pace
8 * address idth is* address idth is NN-bits, then-bits, thenaddress space isaddress space is 22NN (:,1,...,2(:,1,...,2NN-1#-1#
...
::
1122
22NN-1-1
1 bit1 bit
==
:::::::::::::::1:::::::::::::::1
NN
22NN
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Memory Size / SpeedMemory Size / Speed
• $%pical memor% in a personal computer (C#"$%pical memor% in a personal computer (C#"8 BM6 - 25M6BM6 - 25M6
• Memor% si9es"Memor% si9es"
8 4ilob%te4ilob%te (46#(46# ? 2? 21:1: ?? 1,:2B b%tes 1 thousand 1,:2B b%tes 1 thousand8 Megab%te(M6#Megab%te(M6# ? 2? 22:2: ?? 1,:B@,5D b%tes 1 million 1,:B@,5D b%tes 1 million
8 Eigab%teEigab%te (E6#(E6# ? 2? 2/:/: ?? 1,:D/,DB1,@2B b%tes 1 billion1,:D/,DB1,@2B b%tes 1 billion
• Memor% Access $ime (read rom) rite to memor%#Memor% Access $ime (read rom) rite to memor%#
8 5:-D5 nanoseconds (1 nsec. ? :.::::::::1 sec.#5:-D5 nanoseconds (1 nsec. ? :.::::::::1 sec.#
• 7AM is7AM is8 olatile (can onl% store hen poer is on#olatile (can onl% store hen poer is on#
8 relatiel% epensierelatiel% epensie
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Operations on MemoryOperations on Memory
• Fetch (address#"Fetch (address#"8 Fetch a cop% o the content o memor% cell ith the speciiedFetch a cop% o the content o memor% cell ith the speciied
address.address.
8 Non-destructie, copies alue in memor% cell.Non-destructie, copies alue in memor% cell.
• tore (address, alue#"tore (address, alue#"
8 tore the speciied alue into the memor% cell speciied b% address.tore the speciied alue into the memor% cell speciied b% address.
8 estructie, oerrites the preious alue o the memor% cell.estructie, oerrites the preious alue o the memor% cell.
• $he memor% s%stem is interaced ia"$he memor% s%stem is interaced ia"8 Memor% Address 7egister (MA7#Memor% Address 7egister (MA7#
8 Memor% ata 7egister (M7#Memor% ata 7egister (M7#
8 Fetch)tore signalFetch)tore signal
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Structure of the MemoryStructure of the Memory
SubsystemSubsystem• Fetch(address#Fetch(address#8 &oad address into MA7.&oad address into MA7.
8 ecode the address in MA7.ecode the address in MA7.
8 Cop% the content o memor% cell ithCop% the content o memor% cell ithspeciied address into M7.speciied address into M7.
• tore(address, alue#tore(address, alue#8 &oad the address into MA7.&oad the address into MA7.
8 &oad the alue into M7.&oad the alue into M7.8 ecode the address in MA7ecode the address in MA7
8 Cop% the content o M7 into memor%Cop% the content o M7 into memor%cell ith the speciied address.cell ith the speciied address.
MAR MDR
...
Memory
decoder
circuit
Fetch/Storecontroller
F)
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nput/Output Subsystemnput/Output Subsystem
• >andles deices that allo the computer s%stem to">andles deices that allo the computer s%stem to"
8 Communicate and interact ith the outside orldCommunicate and interact ith the outside orld
• creen, <e%board, printer, ...creen, <e%board, printer, ...
8 tore inormation (mass-storage#tore inormation (mass-storage#
• >ard-dries, loppies, C, tapes, ;>ard-dries, loppies, C, tapes, ;
• Mass-torage eice Access Methods"Mass-torage eice Access Methods"
8 irect Access torage eices (As#irect Access torage eices (As#• >ard-dries, lopp%-dis<s, C-7+Ms, ...>ard-dries, lopp%-dis<s, C-7+Ms, ...
8 e0uential Access torage eices (As#e0uential Access torage eices (As#• $apes (or eample, used as bac<up deices#$apes (or eample, used as bac<up deices#
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/O Contro!!ers/O Contro!!ers
• peed o *)+ deices is slo compared to 7AMpeed o *)+ deices is slo compared to 7AM8 7AM 5: nsec.7AM 5: nsec.
8 >ard-rie 1:msec. ? (1:,:::,::: nsec#>ard-rie 1:msec. ? (1:,:::,::: nsec#
• olution"olution"8 *)+ Controller, a special purpose processor"*)+ Controller, a special purpose processor"
• >as a small memor% buer, and a control logic to control *)+>as a small memor% buer, and a control logic to control *)+deice (e.g. moe dis< arm#.deice (e.g. moe dis< arm#.
• ends an interrupt signal to C' hen done read)rite.ends an interrupt signal to C' hen done read)rite.8 ata transerred beteen 7AM and memor% buer.ata transerred beteen 7AM and memor% buer.
8 rocessor ree to do something else hile *)+ controllerrocessor ree to do something else hile *)+ controllerreads)rites data rom)to deice into *)+ buer.reads)rites data rom)to deice into *)+ buer.
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*)+ controller
Structure of the /OStructure of the /O
SubsystemSubsystem
I/O Buffer
Control/Loic
*)+ deice
Data from/to memoryInterru!t "inal #to !roce""or$
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The A"# Subsystem The A"# Subsystem
• $he A&' (Arithmetic)&ogic 'nit# perorms$he A&' (Arithmetic)&ogic 'nit# perorms
8 mathematical operations (G, -, , ), ;#mathematical operations (G, -, , ), ;#
8 logic operations (?, H, I, and, or, not, ...#logic operations (?, H, I, and, or, not, ...#
• *n toda%Js computers integrated into the C'*n toda%Js computers integrated into the C'
• Consists o"Consists o"
8 Circuits to do the arithmetic)logic operations.Circuits to do the arithmetic)logic operations.
8 7egisters (ast storage units# to store intermediate7egisters (ast storage units# to store intermediate
computational results.computational results.
8 6us that connects the to.6us that connects the to.
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Structure of the A"#Structure of the A"#
• 7egisters"7egisters"8 Ver% ast local memor% cells, thatVer% ast local memor% cells, that
store operands o operations andstore operands o operations andintermediate results.intermediate results.
8 CC7CC7 (condition code register#, a(condition code register#, aspecial purpose register that storesspecial purpose register that storesthe result o H, ? , I operationsthe result o H, ? , I operations
• A&' circuitr%"A&' circuitr%"
8 Contains an arra% o circuits to doContains an arra% o circuits to domathematical)logic operations.mathematical)logic operations.
• 6us"6us"8 ata path interconnecting theata path interconnecting the
registers to the A&' circuitr%.registers to the A&' circuitr%.
A&' circuitr%
E$ K &$
7:
71
72
7n
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The Contro! #nit The Contro! #nit
• rogram is stored in memor%rogram is stored in memor%
8 as machine language instructions, in binar%as machine language instructions, in binar%
• $he tas< o the$he tas< o the control unitcontrol unit is to eecute programsis to eecute programs
b% repeatedl%"b% repeatedl%"
8 FetchFetch rom memor% the net instruction to be eecuted.rom memor% the net instruction to be eecuted.
8 ecodeecode it, that is, determine hat is to be done.it, that is, determine hat is to be done.
8 ecuteecute it b% issuing the appropriate signals to theit b% issuing the appropriate signals to the
A&', memor%, and *)+ subs%stems.A&', memor%, and *)+ subs%stems.
8 Continues until the >A&$ instructionContinues until the >A&$ instruction
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Machine "anguageMachine "anguage
nstructionsnstructions• A machine language instruction consists o"A machine language instruction consists o"
8 +peration code+peration code, telling hich operation to perorm, telling hich operation to perorm
8 Address ield(s#Address ield(s#, telling the memor% addresses o the, telling the memor% addresses o the
alues on hich the operation or<s.alues on hich the operation or<s.
• ample" A L, ample" A L, (Add content o memor% locations L(Add content o memor% locations L
and , and store bac< in memor% location #.and , and store bac< in memor% location #.
• Assume" opcode or A is , and addresses L?, ?1::Assume" opcode or A is , and addresses L?, ?1::
::::1::1 :::::::::11:::11 :::::::::11::1::
+pcode (@ bits#+pcode (@ bits# Address 1 (1 bits#Address 1 (1 bits# Address 2 (1 bits#Address 2 (1 bits#
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nstruction Set Designnstruction Set Design
• $o dierent approaches"$o dierent approaches"
8 7educed *nstruction et Computers (7*C#7educed *nstruction et Computers (7*C#
•*nstruction set as small and simple as possible.*nstruction set as small and simple as possible.
• Minimi9es amount o circuitr% --I aster computersMinimi9es amount o circuitr% --I aster computers
8 Comple *nstruction et Computers (C*C#Comple *nstruction et Computers (C*C#
• More instructions, man% er% compleMore instructions, man% er% comple
• ach instruction can do more or<, but re0uire moreach instruction can do more or<, but re0uire morecircuitr%.circuitr%.
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Typica! Machine Typica! Machine
nstructionsnstructions• Notation"Notation"
8 =e use L, , O to denote 7AM cells=e use L, , O to denote 7AM cells
8 Assume onl% one register 7 (or simplicit%#Assume onl% one register 7 (or simplicit%#
8 'se nglish-li<e descriptions (should be binar%#'se nglish-li<e descriptions (should be binar%#
• ata $ranser *nstructionsata $ranser *nstructions
8 &+A&+A LL &oad content o memor% location L to 7&oad content o memor% location L to 7
8 $+7 L$+7 L &oad content o 7 to memor% location L&oad content o 7 to memor% location L
8 M+VM+V L, L, Cop% content o memor% location L to loc. Cop% content o memor% location L to loc.
(not absolutel% necessar%#(not absolutel% necessar%#
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Machine nstructionsMachine nstructions
$cont%&$cont%&• ArithmeticArithmetic
8 A L, , OA L, , O C+N(O# ? C+N(L# G C+N(#C+N(O# ? C+N(L# G C+N(#
8 A L, A L, C+N(# ? C+N(L# G C+N(#C+N(# ? C+N(L# G C+N(#
8A LA L
7 ? C+N(L# G 77 ? C+N(L# G 7
8 similar instructions or other operators, e.g. '6$7,+7, ...similar instructions or other operators, e.g. '6$7,+7, ...
• CompareCompare
8 C+MA7 L, C+MA7 L, Compare the content o memor% cell L to the content o memor%Compare the content o memor% cell L to the content o memor%
cell and set the condition codes (CC7# accordingl%.cell and set the condition codes (CC7# accordingl%.
8 .g..g. * C+N(L# ? 7 then set K?1, E$?:, &$?:* C+N(L# ? 7 then set K?1, E$?:, &$?:
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CMPUT101 Introduction (c) Yngvi Bjorns 20
Machine nstructionsMachine nstructions
$cont%&$cont%&• 6ranch6ranch
8 P'M LP'M L &oad net instruction rom memor% loc. L&oad net instruction rom memor% loc. L
8 P'ME$ LP'ME$ L &oad net instruction rom memor% loc. L&oad net instruction rom memor% loc. Lonl% i E$ lag in CC7 is set, otherise loadonl% i E$ lag in CC7 is set, otherise load
statement rom net se0uence loc. asstatement rom net se0uence loc. as
usual.usual.
•P'MK, P'M&$, P'ME, P'M&,P'MNKP'MK, P'M&$, P'ME, P'M&,P'MNK
• ControlControl
8 >A&$>A&$ top program eecution.top program eecution.
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'(amp!e'(amp!e
• seudo-code"seudo-code" et A to 6 G Cet A to 6 G C
• Assuming ariable"Assuming ariable"
8 A stored in memor% cell 1::, 6 stored in memor% cellA stored in memor% cell 1::, 6 stored in memor% cell
15:, C stored in memor% cell 15115:, C stored in memor% cell 151
• Machine language (reall% in binar%#Machine language (reall% in binar%#
8 &+A 15:&+A 15:
8 AA 1511518 $+7 1::$+7 1::
8 oror
8 (A(A 15:, 151, 1::#15:, 151, 1::#
S f h C !St t f th C t !
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Structure of the Contro!Structure of the Contro!
#nit#nit• C (rogram Counter#"C (rogram Counter#"
8 stores the address o net instruction to etchstores the address o net instruction to etch
• *7 (*nstruction 7egister#"*7 (*nstruction 7egister#"
8 stores the instruction etched rom memor%stores the instruction etched rom memor%
•*nstruction ecoder"*nstruction ecoder"8 ecodes instruction and actiates necessar% circuitr%ecodes instruction and actiates necessar% circuitr%
In"truction
Decoder
IR
%&
'C
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(on Neumann(on Neumann
ArchitectureArchitecture
(on Neumann(on Neumann
ArchitectureArchitecture
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CMPUT101 Introduction (c) Yngvi Bjorns 24
)o* does this a!! *or+)o* does this a!! *or+
together,together,• rogram ecution"rogram ecution"
8 C is set to the address here the irst programC is set to the address here the irst program
instruction is stored in memor%.instruction is stored in memor%.8 7epeat until >A&$ instruction or atal error7epeat until >A&$ instruction or atal error
Fetch instructionFetch instruction
ecode instructionecode instruction
ecute instructionecute instruction
nd o loopnd o loop
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-rogram '(ecution $cont%&-rogram '(ecution $cont%&
• Fetch phaseFetch phase
8 C --I MA7C --I MA7 (put address in C into MA7#(put address in C into MA7#
8 Fetch signalFetch signal (signal memor% to etch alue into M7#(signal memor% to etch alue into M7#8 M7 --I *7M7 --I *7 (moe alue to *nstruction 7egister#(moe alue to *nstruction 7egister#
8 C G 1 --I CC G 1 --I C (*ncrease address in program counter#(*ncrease address in program counter#
• ecode haseecode hase8 *7 -I *nstruction decoder*7 -I *nstruction decoder (decode instruction in *7#(decode instruction in *7#
8 *nstruction decoder ill then generate the signals to*nstruction decoder ill then generate the signals to
actiate the circuitr% to carr% out the instructionactiate the circuitr% to carr% out the instruction
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CMPUT101 Introduction (c) Yngvi Bjorns 2
-rogram '(ecution $cont%&-rogram '(ecution $cont%&
• ecute haseecute hase8 iers rom one instruction to the net.iers rom one instruction to the net.
• ample"ample"8 &+A L (load alue in addr. L into register#&+A L (load alue in addr. L into register#• *7Qaddress -I MA7*7Qaddress -I MA7
• Fetch signalFetch signal
• M7 --I 7M7 --I 78 A LA L
• let as an eerciselet as an eercise
t ti S t f O V t ti S t f O V
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CMPUT101 Introduction (c) Yngvi Bjorns 2!
nstruction Set for Our Vonnstruction Set for Our Von
Neumann MachineNeumann Machine+pcode+pcode +peration+peration MeaningMeaning
)))) LOAD * CON#*$ ++, R)))& S-OR * R ++, CON#*$
))&) CLAR * ) ++, CON#*$
))&& ADD * R % CON#*$ ++, R
)&)) INCRMN- * CON#*$ % & ++, CON#*$
)&)& SB-RAC- * R + CON#*$ ++, R)&)& DCRMN- * CON#*$ + & ++, CON#*$
)&&&
COM'AR * If CON#*$ , R then 0- 1 & el"e )
If CON#*$ 1 R then 2 1 & el"e )
If CON#*$ 3 R then L- 1 & el"e )
&))) 4M' * 0et ne5t in"truction from memory location *&))& 4M'0- * 0et ne5t in"truction from memory loc. * if 0-1&
... 4M'55 * 55 1 L- / 2 / N2
&&)& IN * In!ut an inteer (alue and "tore in *
&&&) O- * Out!ut6 in decimal notation6 content of mem. loc. *
&&&& 7AL- Sto! !roram e5ecution
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