the process flow for fabrication the resister ic
Post on 12-Feb-2016
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The Process flow for fabrication the resister IC
Step I: The Beginning-Choosing a substrate
Before actual wafer fabrication, we must choose the starting wafers. The major choices are the type (N or P), resistivity, and orientation.
In most IC circuits, the substrate has a resistivity in the range of 25-50cm, which corresponds to a doping level on the order of 1015cm-3.
The other major parameter we need to specify in the starting substrate is the crystal orientation. Virtually all modern silicon integrated circuits are
manufactured today from wafer with a (100) surface orientation. The principal reason for this is that the properties of Si/Sio2 interface are significantly better when a (100) crystal is used.
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Lecture # 2
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CMOS Process Flow
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Cross section of the final CMOS integrated circuit.
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3SiH4+4NH3Si3N4+12H2
Silicon nitride form a barrier against the impurities moving toward the Si surface.
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Photolithography
• In order to transfer resister information from the design to the wafer, a process known as photolithography is used.
• For this process a material known as photoresist is first spread on the wafer. It is usually baked at about 100oC in order to drive off
• solvants from the layer (photolithographic process will be covered in chapter 5 through.
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Lecture # 2
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Open windows for thick oxidation
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Bird’s beak
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P Well Formation
1016 -1017 cm-3
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N Well Formation
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High temperature Drive-In
2-3 micron
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NMOS gate formation and adjusting VTH
The single most important parameter in the both NMOS and PMOS devices is the threshold voltage
To adjust VTH , two terms that are important are the doping concentration and the oxide capacitance.
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PMOS Gate Formation
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Why oxide layer is stripped and then regrown?
Regrown of gate oxide
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SiH4 Si+2H2
Low ploy sheet resistivity and low gate resistance is required.
Deposition of polysilicon layer
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Selective Etching: to locate MOS gates
Selectivity and anisotropy are big deal hare
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Tip or extension (LDD) formation
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Tip or extension (LDD) formation
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Sidewall Spacer fabrication
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Aniostropic Etching
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Formation of NMOS source and Drain region
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Formation of PMOS source and Drain region
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High temperature Drive-In
TED is a big issue hare!
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Contact and local Interconnect formation
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TiSi2
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Multilevel metal formation
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Basic NMOS process flowchart.8
Lecture # 2
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Basic bipolar process flowchart.9
Lecture # 2
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