the front-end asic for the atlas pixel detector
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A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
K. Einsweiler Lawrence Berkeley National LabATLAS Pixel FE Overview, Sept 10 2002 1 of 50
The Front-end ASIC for the ATLAS Pixel Detector
K. Einsweiler, LBNL
Overview of FE specifications and design
History of ATLAS Pixel FE ASIC
The first 0.25µ generation of the FE ASIC, FE-I1
Wafer probe results and yield issues
Second generation 0.25µ FE ASIC, FE-I2
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S Pixel FE Overview, Sept 10 2002 2 of 50
nnections to
rd, up to 1m away.e HV bias supply.DS I/O
K. Einsweiler Lawrence Berkeley National LabATLA
System Design of Pixel ModuleOverall system architecture, including intercoopto-link and all power supplies:
•Optical package and DORIC/VDC mount on separate opto-ca•Module itself uses two LV supplies (analog and digital) and on•Communication between module and opto-card uses 3mA LV
A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
S Pixel FE Overview, Sept 10 2002 3 of 50
r chip (MCC), and 16
K. Einsweiler Lawrence Berkeley National LabATLA
Block diagram of module itself:
•Two chip design, including a single controller and event-buildefront-end chips bumped to a single silicon substrate.
•Flex hybrid is used to provide interconnections above.
A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
S Pixel FE Overview, Sept 10 2002 4 of 50
, SerialOut, XCK),
nals. Slow control will S. All fast signals use nals use 0.5 mA A drivers.erial output lines are allel inputs on MCC). at this time. All FE to control analog
accept is present ation for the given ssings to allow gether. properly.
K. Einsweiler Lawrence Berkeley National LabATLA
Features:•Basic interface to the outside uses a 3-wire protocol (SerialIn
which maps onto the SCT opto-link protocol•Basic interconnections between FE and MCC use bussed sig
not operate when recording events, so it uses full-swing CMOlow-swing differential “LVDS-like” signaling. Point-to-point sigdrivers (FE chips only), external or bussed signals use 3.5 m
•To provide enhanced speed and robust module design, the sconnected from the FE to the MCC in a star topology (16 par
•There are no remaining analog signals between MCC and FEchips have internal current references and adjustment DACsoperating points, as well as calibration.
•Architecture is “data-push” style: each crossing for which LV1causes all FE chips to autonomously transmit back hit informcrossing. LV1 signal may remain set for many contiguous croreadout of longer time intervals. MCC merges such events to
•Synchronization signal available to ensure FE chips label LV1
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S Pixel FE Overview, Sept 10 2002 5 of 50
µ): orst-case current and e total current budget
0mA worst-case. For mA (28µA/pixel)
ystem is very ith the reduced
ing are much less
7.2 x 8.0mm is FE chips must l logic and I/O
s possible in one chievable. In the long f 300µ - 400µ. The
K. Einsweiler Lawrence Berkeley National LabATLA
Requirements SummaryPower budget (actually current budget for 0.25
•Present design of services and cooling based on typical and wpower analyses for DMILL chips. The FE-I should fit the samfor the VDDA (analog) and VDD (digital) supplies.
•The present budgets for the digital supply are 25mA typical, 4the analog supply, they are 60mA (21µA/pixel) typical and 80worst-case. The design of the low-mass power distribution schallenging, and we must stay safely within these budgets. Wvoltage used for the 0.25µ process, the total power and cooldifficult issues than they were in the past.
Geometry:•The active die area for the FE chip is 7.2 x 10.8 mm, of which
sensitive area for particle detection. The sensitive area of theextend to the edge of the die along 3 sides, with all additionaconcentrated on the remaining side.
•Physics studies indicate that the pixels should be as narrow adimension, and a 50µ pitch has been chosen as reasonably adirection, adequate resolution is obtained with a dimension opresent prototyping program has frozen the length at 400µ.
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S Pixel FE Overview, Sept 10 2002 6 of 50
w compatible, parallel
pixels arranged in 18
for pixels in column 0 es us 9 column pairs, on the sides.uble row of 50µ pitch
2µ opening in the
of the active area on uitry is allowed on
allowed 2800µ,
200µ wire-bond pad, as frozen. for connections due gnostics.
K. Einsweiler Lawrence Berkeley National LabATLA
Basic FE Chip Geometry•Agreement on pixel size was struck in Sept 96, in order to allo
detector and electronics development. •The geometry adopted was 50µ x 400µ for the pixel size, with
columns of 160 pixels per column.•The geometry was mirrored between columns, so that inputs
and 17 are on the outside. All other inputs are paired. This givwith a common digital readout in the center, and analog cells
•The input pad geometry in the inner column pairs is then a dopads. The metal pad is specified to be 20µ octagon, with a 1passivation for the bump-bonding.
•The cut die size must not extend beyond 100µ from the edgethree sides of the die. Hence, nothing outside of the pixel circthree sides of the chip, to allow module construction.
•The bottom of the chip (all peripheral logic and I/O pads) are making the total active die region 7.2mm x 10.8mm.
•An I/O pad structure of 48 pads, each consisting of a 100µ x and a group of 4 bump-bond pads for MCM-D applications, w
•For final modules, only the central 30 bond pads are availableto mechanical envelopes. Other 18 pads are available for dia
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S Pixel FE Overview, Sept 10 2002 7 of 50
-HE-A/C). FE-B (HP in lab and testbeam. and VDC chips, and
ut in July 99. in two circuit blocks. technology problems isolating the problem,
In one version, all c logic blocks which ced low-yield blocks
to make room. Run hips as well.blems. Yield on static was terminated.mit when we received afer cost of 20-30K$, el chip.5µ approach, based tarted in Sept 2000.
K. Einsweiler Lawrence Berkeley National LabATLA
Brief History: FE-B, FE-D, and FE•Rad-soft prototyping delivered functional chips in 98 (FE-B, F
0.8µ) demonstrated all basic ATLAS pixel performance goals•Submitted FE-D1 run, containing FE-D1 front-end chip, DORIC
prototype MCC-D0 chip (plus test chips). Submission went o•FE-D1 suffered from minor design errors, and very poor yield
After considerable investigation, the low yield was related to (low rate of very leaky NMOS). Foundry never succeeded in but proposed a series of special corner runs.
•Submitted FE-D2 run in Aug 00, with two versions of FE-D2. design errors were fixed, but basic design (including dynamisuffered low yield) was left unchanged. Second version replawith static versions, and removed other circuitry (trim DACs)included full MCC-D2 (100mm2) and new DORIC and VDC c
•Corner runs gave no new information on yield/technology prochip was better, but still unacceptable. Work with this vendor
•Began work on FE-H in Dec 99. Chip was almost ready to subnotification of massive cost increases from Honeywell. With weffort was abandoned before actually building a complete pix
•The failure of both traditional rad-hard vendors left us with 0.2on commercial process and rad-tolerant layout. Major effort s
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S Pixel FE Overview, Sept 10 2002 8 of 50
essS6SF process::
n can be streamed
ek turnaround to
ough TSMC has not have been performed MRad and 120MRad.
TSMC rules.f digital ground and
tion in individual of column, and both
), so that problems do
K. Einsweiler Lawrence Berkeley National LabATLA
Design Methodology for 0.25µ ProcBegin with CERN/RAL design kit for IBM CMOSimilarity between IBM and TSMC design rules
•Implement common design environment where a single desigout and submitted to either vendor for fabrication.
•Cost of both is similar, but have frequent access with 8-10 weTSMC foundry via MOSIS.
•In case of problems with one vendor, we have a back-up. Althbeen as thoroughly qualified for radiation as IBM, many testsby FNAL group, and we have also irradiated prototypes to 60
Updated CERN/RAL Standard Cell Library:•Minor layout modifications made to provide compatibility with•Low noise mixed-mode design goals suggested separation o
substrate connection in the cells. •We have also separated analog ground and substrate connec
analog blocks. Two substrate connections are joined at bottomare connected to analog ground at the pad frame.
•Prefer to “over-fill” cells in non-routing layers (poly and activenot arise later during integration.
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S Pixel FE Overview, Sept 10 2002 9 of 50
designs.eration):xcellent leakage for TOT, and very
led to the preamp. block, and should ld control is applied cond amplifier stage,
tor which provides the
ach pixel, plus a 5-bit . There are four ntry of hit into readout nable injection of of a current mp, allowing nt from the sensor.
K. Einsweiler Lawrence Berkeley National LabATLA
Feature List for FE-IDesign is logical evolution from FE-D and FE-HAnalog Front-end (designed for VDDA=1.6V op
•The FE uses a DC-feedback preamp design which provides ecurrent tolerance, close to constant-current return to baselinestable operation with different shaping times.
•It is followed by a differential second amplifier stage, DC-coupThe reference level (VReplica) is generated in the feedback match the DC offset of the preamp with no input. The threshousing two currents to modify the offsets on the inputs to the seallowing a large range for threshold control.
•The two-stage amplifier is followed by a differential discriminadigital output sent to the control logic.
•The control logic provides a 5-bit threshold trim capability in efeedback current trim capability for tuning the TOT responsecontrol bits, including Kill (shut down preamp), Mask (block elogic), HitBus (enable output to global FastOR) and Select (echarge for testing). The HitBus bit also controls the summingproportional to the feedback plus leakage current in the preamonitoring of the feedback current, and of the leakage curre
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Pixel FE Overview, Sept 10 2002 10 of 50
s type of readout, and
d by internal DACs. ditional DAC for the rnal CMOS current gister, and controlled
tion):us as a timing ir leading and trailing
Ms.ls as soon as the
column pair. This bus requirements. d to achieve this.or hit storage during available for each he L1 trigger is ediately cleared.
K. Einsweiler Lawrence Berkeley National LabATLAS
•A global FastOR net is created using all pixels enabled for thiprovides a self-trigger and diagnostic capability.
•All critical bias currents and voltages on the chip are controlleThere are 12 8-bit DACs for the analog front-end, and an adcharge injection. The current DACs are referenced to an intereference, and the DAC values are loaded from the Global Revia the Command Register.
Digital Readout (designed for VDD=2.0V opera•It uses an 8-bit Grey-coded 40 MHz differential “timestamp” b
reference throughout the active matrix. All pixels measure theedge timing by asynchronously latching this reference in RA
•Hits (address plus LE/TE timing) are transferred from the pixetrailing edge occurs, using a shared bus structure in the pixeloperates at transfer rates up to 20 MHz in order to meet our Differential signal transmission and sense amplifiers are use
•Significant buffering is provided in the end of column region fthe L1 latency (up to 6.4µs in this chip). Sixty four buffers arecolumn pair (one for each five pixels). The coincidence with tperformed in this buffer. Hits from rejected crossings are imm
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S Pixel FE Overview, Sept 10 2002 11 of 50
ending readout. As pending event ing a request for the ich are then pushed
and protocol. A Load and control, or as is register implement
bal).C values, enabled
egister is eadback capability. nfiguration
es access to the 14 >, TDAC<0:4>). ion back into the long U-tolerant. entity is controlled by also supported.
K. Einsweiler Lawrence Berkeley National LabATLA
•A readout sequencer stores information on up to 16 events psoon as the output serial link is empty, transmission of a newbegins. Essentially, sending a L1 trigger corresponds to makall hits associated with the corresponding beam crossing, whoff the FE chip to the MCC.
Control Logic:•Global control of the chip is implemented using a simple comm
signal controls whether input bits are interpreted as address data. There is a 20-bit Command Register. Individual bits in thspecific commands (e.g. ClockGlobal, WriteGlobal, ReadGlo
•A Global Register, consisting of 202 bits, controls Latency, DAcolumns, clock speeds, and several other parameters. This rimplemented as a shift register and a shadow latch with full rThe shadow latch is SEU-tolerant since it contains critical coinformation.
•A Pixel Register which snakes through the active array providcontrol bits in the pixel (Select, Mask, HitBus, Kill, FDAC<0:4Readback capability is supported by transferring FF informatshift register for readout. The 14 latches in each pixel are SE
•Each chip on a module is geographically addressed, and its idexternal wire-bonds to avoid confusion. A broadcast mode is
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Pixel FE Overview, Sept 10 2002 12 of 50
le diagram:
(RSTb, DI, CCK, LD), , SYNC, DO).erential strobe (STR) ovides external ixel output.
e pixel, there is the d (preamp/
inator), the control nd the readout
ow the active pixel s the biassing and for the front-end and the data ing and buffering for dout blocks.there is the overall t control and the nd decoding.
K. Einsweiler Lawrence Berkeley National LabATLAS
FE-I Block Diagram:Basic FE block diagram, expanded from modu
•Basic Digital I/O shown on bottom: 4 CMOS inputs for control and 4 fast, differential I/O’s for timing and readout (XCK, LV1
•Calibration and monitoring are shown on the right. A fast, diffsupplies calibration timing. An analog voltage input (VCal) prcalibration. Monitoring pins include FastOR, DACs and test p
•Within thfront-endiscrimblock, ablock.
•Just belmatrix icontrol blocks,formattthe rea
•Finally, readoucomma
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Pixel FE Overview, Sept 10 2002 13 of 50
try of die:
K. Einsweiler Lawrence Berkeley National LabATLAS
FE-I Pinout and GeometrySketch of pin assignments and overall geome
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Pixel FE Overview, Sept 10 2002 14 of 50
l
to ground (parasitic) ance should still be provide negative
e charge sharing).ld be 200µ.
m2 is about 10Ke with d of the detector works well.. This requirement is ce charge (100Ke) of n channels on a chip
ieved by for example r a timewalk of 20ns or our front-end. than about 200e,
500e.
K. Einsweiler Lawrence Berkeley National LabATLAS
Front-end, biassing and controSummary of the requirements:
•A nominal capacitive load of 400 fF is expected, roughly half and half to the nearest neighbors (inter-pixel). Good performobtained with loads above 500fF. The n+ on n-bulk detectorssignals.
•Pixels are oriented to maximize signal and efficiency (minimiz•The outer layers should be 280µ silicon, and the B-layer shou
•The worst-case signal after the lifetime dose of 1015 n-equiv/c600V bias. We propose to operate at the 600V bias at the enlifetime, and have real prototype experience to show that this
•This leads to an in-time threshold requirement of about 4-5Kedefined using a maximum timewalk relative to a large referen20ns, in order to allow for additional timing dispersion betweeand module, as well as between modules. This could be achsetting a 3Ke threshold, and having the required overdrive fobe less than 2Ke. This is the most challenging requirement f
•Noise should be less than 450e and threshold dispersion lessleading to an overall threshold “variation” of less than about
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Pixel FE Overview, Sept 10 2002 15 of 50
without significant ved for each pixel.
0%, where this is hich must be injected
rs, and 0.5µs for the
est analog resolution e impact on the other
40fF should be oise measurements alk measurments.d for the preamps. In
no identifiable
K. Einsweiler Lawrence Berkeley National LabATLAS
•Leakage current tolerance should be at least 50nA per pixel, changes in operating performance, and independently achie
•Noise occupancy should be less than 10-6 hits/crossing/pixel.•Crosstalk between neighboring pixels should be less than 5-1
defined as the ratio between the threshold and the charge winto a pixel to fire its neighbors.
•A double pulse resolution of 2µs is required for the outer layeB-layer, in order to achieve our total deadtime requirements.
•It is required to provide binary readout of each pixel, but a mod(4-5 bits) is very desirable if it can be achieved without a largperformance specifications.
•A threshold range of at least 0 - 6Ke is needed.•Two calibration injection capacitors of roughly 5-10fF and 30-
included in each pixel, giving a low range for threshold and nand a high range for charge calibration, timewalk, and crosst
•We have no evidence that real diode input protection is needeall present chips, no explicit input protection is provided, andproblems have been observed.
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Pixel FE Overview, Sept 10 2002 16 of 50
setime. Input about 8µA bias.l second stage line and 20Ke input.ut of the second
rrent of about 5µA.
K. Einsweiler Lawrence Berkeley National LabATLAS
FE and Control Blocks:
•Preamp has roughly 5-10fF DC feedback design, and 15ns ritransistor is a PMOS with W/L of 25.2/0.6µ, and operates at
•Feedback circuit generates reference voltage for a differentia(VReplica). Feedback current is 2nA for a 1µs return to base
•Threshold control operates by modifying the offsets at the inpamplifier. Second amplifier bias is about 4µA.
•Discriminator is DC-coupled and differential. It uses a bias cu
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Pixel FE Overview, Sept 10 2002 17 of 50
to the current mode
ood linearity. A 9-bit
and mirror the current nt. The biasses are el.
column pair. It allows ssing a column pair in out and buffer
K. Einsweiler Lawrence Berkeley National LabATLAS
FE Biassing and Control Blocks:
•A reference circuit is used to supply a 4µA reference current DACs (1µA/bit, but two LSB generated by simple mirrors).
•The current mode DACs are a rad-tolerant 8-bit design with gversion is used for the VCal calibration DAC.
•The biassing circuits are located directly on top of the DACs, down so that 64 DAC counts provides the nominal bias curredistributed as Vgs voltages, with matching mirrors in each pix
•A single column enable bit controls the major operations of abypassing a column pair in the pixel shift register chain, bypathe HitBus FastOR net, plus bypassing the sparse scan readoverflow generation of a column pair.
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Pixel FE Overview, Sept 10 2002 18 of 50
am crossing.d up to 3.2µs.es between leading
GEANT simulation of perate with a 20 MHz er to provide safe ore stringent, and
verflow of the EOC lumn pair overflows,
s stretched to cover a lost hits due to this rd.
phase lies between
K. Einsweiler Lawrence Berkeley National LabATLAS
Digital readoutSummary of the requirements:
•Make a unique association of each hit pixel with a 40 MHz be•Store hits in pixel array for L1 latency period, which can exten•Make a modest TOT measurement by counting time differenc
and trailing edges in 40 MHz units.•Simulations for the current architecture exist, driven by the full
ATLAS. This suggests that the current architecture needs to ocolumn clock rate and have 25 buffers per column pair in ordoperation of the outer layers. The B-layer requirements are mrequire something like 40 buffers.
•There is only a single error condition which occurs, namely obuffers. In the case where the EOC buffer block in a given cohits are lost until a free buffer exists, and the error condition ifull L1 latency (covering all possible events which could havecondition). The error status is then transmitted in the EOE wo
Specifications:•Clock duty cycle specified to be between 40% and 60% (high
10ns and 15ns, or nominal +/- 2.5ns).
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Pixel FE Overview, Sept 10 2002 19 of 50
ut:
K. Einsweiler Lawrence Berkeley National LabATLAS
Block diagram of the basic column-pair reado
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Pixel FE Overview, Sept 10 2002 20 of 50
ta:address) into an EOC criminator trailing
d by the CEU in the Hz.
TOT calculation d may be applied to below correction operation are r faster than 20MHz.r a corresponding sing LE timestamp of er number. Otherwise
ll no longer be empty. re scanned for the
its are found, they are umber have been
e, with all column
K. Einsweiler Lawrence Berkeley National LabATLAS
Summary of basic steps in readout of pixel da•Transfer hit information (LE and TE timestamp, plus pixel row
buffer. This operation begins when data is complete (after disedge). The transfer of hits from a column pair is synchronizebottom of column, which operates at a speed of 5, 10, or 20M
•Hit information is formatted by the CEU. Formatting includes (TE-LE subtraction) in all cases. Optionally, a digital thresholTOT, a timewalk correction may be applied (write hit twice if threshold, once with LE and once with LE-1), or both. Thesepipelined to minimize deadtime, but EOC writes cannot occu
•Hit information is written to the EOC buffer, and waits there foLVL1 trigger. If a trigger arrives at the correct time (checked uhit), the data is flagged as belonging to a particular 4-bit triggit is reset and the buffer is freed.
•Once the chip has received LVL1 triggers, the trigger FIFO wiThis initiates a readout sequence in which the EOC buffers apresence of hits belonging to a particular trigger number. If htransmitted to the serializer. After all hits for a given trigger nsent, an End-of-Event word is appended to the data stream.
•All of these operations occur concurrently and without deadtimpairs operating independently and in parallel.
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Pixel FE Overview, Sept 10 2002 21 of 50
al Register:
ld, after which LD ports 20 different,
e of the critical special SEU-tolerant EU flip rate for these
K. Einsweiler Lawrence Berkeley National LabATLAS
Block diagram of Command Decoder and Glob
•Simple command protocol, based on a 5+20-bit command fiegoes high and associated data may be transmitted. This supindependent commands.
•Global Register controls overall operation of FE chip. Becausimportance of its bits, the actual latched values are stored inFF. First measurements with 0.25µ prototypes indicate the Sbits is less than one flip per bit during the lifetime of ATLAS.
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Pixel FE Overview, Sept 10 2002 22 of 50
iphery:
T pin, or the width of et signals. same trigger number the “empty” state for , the HardReset also
K. Einsweiler Lawrence Berkeley National LabATLAS
Block diagrams of remaining blocks in the per
•There is a reset generator that either uses the external RESEthe SYNC input in XCK clocks, to generate three internal res
•The Resync makes sure that all FE on a module are using the(it resets the trigger FIFO). The SoftReset puts the chip into data, but does not alter any configuration information. Finallyresets all configuration information to zero.
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of the chip is powered n particular, clears the ut circuitry. The result A digital), suitable for
operation of liquid log power.t LV1 through to the l to generate its own p to be used in self-ce it has been armed l FastOR.
internal signal or data e first eight inputs are entical multiplexor d for the MONHIT
nt reference to define s referenced to the
er. Circuits are very meet specifications
K. Einsweiler Lawrence Berkeley National LabATLAS
•There is a Power-on Reset which makes sure the digital part up into the Reset state. This clears the Global Register, and iEnableReadout bit, blocking XCK distribution to digital readois low analog and digital power consumption (4mA analog, 8mperforming basic module connectivity tests without requiring cooling system. Basic connectivity checks do not require ana
•There is a self-trigger generator, which either passes the inputrigger processing circuits, or uses the internal FastOR signaLV1 signal after a programmable latency. This allows the chitrigger mode with a source, and it will produce output data onby a previous LVL1 trigger, and it sees a signal on the interna
•There is a dual 8-fold output multiplexor which selects which stream is transmitted off the chip through the serial output. Thsynchronized with XCK, while the second eight are not. An idcircuit is used both for the standard serial output pin (DO), anmonitoring output pin.
•The LVDS driver/receiver circuits use a second internal curredrive current and receiver bias. The common mode voltage iVdd supply using resistors. Output drive is 0.5mA for low powstable under process and power supply variations, and easilyat 2V supply voltage.
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Pixel FE Overview, Sept 10 2002 24 of 50
ign: is not necessarily g time. Below is TOT
Symbol
5u 50u
Symbol
0
K. Einsweiler Lawrence Berkeley National LabATLAS
Features of new FE-I front-end des•TOT performance is almost linear to very large charges. This
desirable, as a heavily ionizing particle can kill a pixel for a lonscan from 0 to 1Me signal, giving TOT of 40µs.
Wave
D0:A0:v(out)
Type
Transient
Design
D0: CELL16V_NEWFB_TOT
Voltages (lin)
0
500m
1
1.5
Time (lin) (TIME)
0 5u 10u 15u 20u 25u 30u 35u 40u 4
ibm cell, vdd=1.6v, typ params, newfb, cdet=400ff, cf=10ff, if=2
Wave
D0:A0:tot
D0:A1:tot
D0:A2:tot
D0:A3:tot
File
cell16v_newfb_tot.mt0
cell16v_newfb_tot.mt1
cell16v_newfb_tot.mt2
cell16v_newfb_tot.mt3
Type
Transient
Transient
Transient
Transient
Design
D0: CELL16V_NEWFB_TOT
D0: CELL16V_NEWFB_TOT
D0: CELL16V_NEWFB_TOT
D0: CELL16V_NEWFB_TOT
Measures (lin)
0
20u
40u
Outer Result (lin) (lev)
-10 -8 -6 -4 -2
ibm cell, vdd=1.6v, typ params, newfb, cdet=400ff, cf=10ff, if=2
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Pixel FE Overview, Sept 10 2002 25 of 50
Det from 0fF to 400fF:
500e for 20ns
Wave
D0:A8:4:timewalk
D0:A9:4:timewalk
D0:A10:4:timewalk
D0:A11:4:timewalk
D0:A12:4:timewalk
6k
K. Einsweiler Lawrence Berkeley National LabATLAS
•Timewalk performance (relative to 100Ke) with Cfb=5ff, for C
•Overdrive for Cfb=5fF and CDet=200fF predicted to be only 1timewalk. For CDet=400fF, this deteriorates to 2500e.
File
cell16v_twalk_newfet_alldiode_cdet.mt8
cell16v_twalk_newfet_alldiode_cdet.mt9
cell16v_twalk_newfet_alldiode_cdet.mta
cell16v_twalk_newfet_alldiode_cdet.mtb
cell16v_twalk_newfet_alldiode_cdet.mtc
Type
Transient
Transient
Transient
Transient
Transient
Design
D0: CELL16V_TWALK_NEWFET_ALLDIODE_CDET
D0: CELL16V_TWALK_NEWFET_ALLDIODE_CDET
D0: CELL16V_TWALK_NEWFET_ALLDIODE_CDET
D0: CELL16V_TWALK_NEWFET_ALLDIODE_CDET
D0: CELL16V_TWALK_NEWFET_ALLDIODE_CDET
Measures (lin)
0
10n
20n
30n
40n
50n
60n
70n
80n
Outer Result (lin) (lev2)
2k 3k 4k 5k
ibm cell, vdd=1.6v, alldiodes, cdet=400ff, cf=5ff, if=2na
A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
Pixel FE Overview, Sept 10 2002 26 of 50
o 50nA):
kage, destroying the r the case.
Symbol
)
)
)
)
)
)
1u
K. Einsweiler Lawrence Berkeley National LabATLAS
•Variation in shaping as a function of leakage current (from 0 t
•Previous FE-B shaping was much stronger in presence of leacharge measurement for irradiated sensors. This is no longe
Wave
D0:A0:v(out1
D0:A1:v(out1
D0:A2:v(out1
D0:A3:v(out1
D0:A4:v(out1
D0:A5:v(out1
File
cell16v_newfb_leak.tr0
cell16v_newfb_leak.tr1
cell16v_newfb_leak.tr2
cell16v_newfb_leak.tr3
cell16v_newfb_leak.tr4
cell16v_newfb_leak.tr5
Type
Transient
Transient
Transient
Transient
Transient
Transient
Design
D0: CELL16V_NEWFB_LEAK
D0: CELL16V_NEWFB_LEAK
D0: CELL16V_NEWFB_LEAK
D0: CELL16V_NEWFB_LEAK
D0: CELL16V_NEWFB_LEAK
D0: CELL16V_NEWFB_LEAK
Voltages (lin)
1
1.05
1.1
1.15
1.2
1.25
1.3
1.35
Time (lin) (TIME)
0 200n 400n 600n 800n
ibm cell, vdd=1.6v, typ params, newfb, leak, cdet=400ff, cf=10ff
A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
Pixel FE Overview, Sept 10 2002 27 of 50
o cap groups:
al of 8640 in the chip, claimed by IBM to
capacitors in the
K. Einsweiler Lawrence Berkeley National LabATLAS
Layout of pixel, showing two FE blocks and tw
•A total of 3 smart capacitors are placed in each pixel, for a totgiving roughly 15nF of total decoupling. These capacitors arehave excellent properties up into the GHz region.
•Capacitor size is roughly 40x50µ, allowing the placement of 3remaining empty space in the pixel.
A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
Pixel FE Overview, Sept 10 2002 28 of 50
rant latches.ack for 14 FF in pixel w more than 40K
-tolerant latches.
iring datanted in TOT field of hit
nLeak DACach pixel, plus
of Clo, Clo+Chi, and sure feedback current
K. Einsweiler Lawrence Berkeley National LabATLAS
Control Features:Command Register:
•FE-I contains 20-bit Command Register made up of SEU-tole•Mostly just strobes for writing all pixel FF. New feature is readb
control block. This was thought necessary since there are noconfiguration bits in the pixels of one FE chip.
Global Register:•FE-I contains a 202 bit long Global Register made up of SEU•Too many highlights to mention: •Enable bit for TSI/TSC to reduce digital power when not acqu•EOC MUX control to choose whether LE, TE, or TOT is prese
output data•Total of 14 DACs, including new 9-bit VCal DAC and 9-bit Mo•Dual injection capacitors and improved internal chopper for e
independent external injection path for good cross-calibration•Special additional blocks like CapMeasure to measure values
Cfb directly, and simple DAC-based comparator ADC to meaand leakage current in each pixel.
A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
Pixel FE Overview, Sept 10 2002 29 of 50
f SEU-tolerant
noise
ster, but is a separate
dback current
of analog and digital
f output data for
K. Einsweiler Lawrence Berkeley National LabATLAS
Pixel Control bits:•FE-I contains 14 bits of configuration in each pixel, made up o
latches.•Highlights include: •Kill bit to turn off pixel preamplifier to avoid injection of analog•Separate enables for HitBus and Digital Readout•Select for calibration which is no longer stored in the shift regi
FF. •A 5-bit TDAC for threshold trimming and a 5-bit FDAC for fee
trimming.
Testability features:•Digital injection of Str signal into each pixel, allows decoupling
parts of the chip, and creation of well-defined data pattens.•MUX to allow capturing LE and TE RAM data into TOT field o
testing purposes.
A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
Pixel FE Overview, Sept 10 2002 30 of 50
nd ROM blocks in the swings of VDD/2.y.lculates the TOT for ss writing small g timewalk correction shold are written leading edge time of ly if desired.
buffering
et to 0 disables all clocking of EOC it. By default all of tial digital power
rd. BCID increments missed/excess L1 ber, so no ambiguities
K. Einsweiler Lawrence Berkeley National LabATLAS
Digital Readout Features•All differential timestamp distribution, and differential SRAM a
pixels, combined with new differential senseamp design with•Use of 8-bit timestamps to provide 6.4µs maximum L1 latenc•TOT processor block at bottom of each column. This block ca
each hit. It can apply a simple threshold to the TOT to supprecharges into the EOC buffers. It can also apply a one crossinto all hits below a settable TOT threshold. Hits below the thretwice, once with the raw leading edge time, and once with a one crossing earlier. Both features can operate simultaneous
•Implementation of 64 EOC buffers, exceeding known B-layerrequirements even at design luminosity.
•Global control of clocking in column pair (CEU clock control soperations in column pair), by column enable bit (suppressesbuffers for disabled column pairs), and by TSI/TSC disable bthese bits are off when chip is powered on, leading to low iniconsumption.
•Replacement of 4-bit trigger number with 4-bit BCID in hit woevery crossing, and provides more robust protection againsttriggers. Internal event building always based on trigger numare introduced.
A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
Pixel FE Overview, Sept 10 2002 31 of 50
ion: are included, one for oft threshold of about to ground. Note that
t clamps, which are e power rails when no mps, there are two e circuit as the ear regulator using a
gulator is intended for ies. The linear digital supply voltage, ere is little risk posed cing them inside the with and without
Cs for
d in the same way as feedback current and s already proven very
K. Einsweiler Lawrence Berkeley National LabATLAS
New features and pins outside the bonding reg•Power Management features: Two overvoltage clamp circuits
each power supply. They use a diode and a resistor to set a s2.7V, after which a large PFET is used to sink excess voltagethe power pads also include the recommended IBM transiendesigned to protect the chip from sharp spike transients on thpower is applied to the chip. In addition to the overvoltage clasimple regulators. One is a shunt regulator, based on the samclamp, but with a threshold of 2.0V. The second is a simple linband-gap reference, and set for 1.6V operation. The shunt restudy of powering schemes based on constant current supplregulator would generate the analog supply voltage from the allowing operation of the FE chip on a single power supply. Thby these circuits if the wire-bonds are not connected, and plaFE chips allows the performance of modules to be comparedthese circuits, without changes to the Flex design.
•MonDAC provides multiplexed access to all of the internal DAcharacterization during testing.
•MonLeak provides access to a current summing tree (controllethe HitBus) that allows a direct measurement of the preamp the sensor leakage current: I(OutLeak) = 2*If + ILeak. This ha
A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
Pixel FE Overview, Sept 10 2002 32 of 50
on a 9-bit DAC, is
d for the LVDS I/O E chip.ted internally on the y a 9-bit current DAC current reference,
preamp waveform, This is followed by a f test amplifiers,
ircuitry, which uses a al capacitors used in ring a single DC ip, and can provide el. The circuit used to be measured, as urement. This gives
K. Einsweiler Lawrence Berkeley National LabATLAS
useful in chip characterization. A simple internal ADC, basedalso provided.
•MonRef allows direct monitoring of the current reference usepads, without requiring any other circuitry to operate on the F
•MonVCal allows direct monitoring of the VCal voltage generaFE chip for charge injection calibrations. VCal is generated band a resistor. The resistor is matched to the one used in theproviding first-order cancellation of process variations.
•MonAmp includes an analog MUX which allows us to see thethe two sides of the second amplifier, and the chopper input.100Ω buffer amplifier, which can drive a daisy-chained bus oprovided only one is enabled at any time.
•CapMeasure pin is attached to new capacitor measurement ccharge pump circuit to measure accurate values for the criticthe front-end (C(feedback), C(inj-low), C(inj-high)) by measucurrent. This circuit has been used in the DMILL CapTest chaccurate measurements of capacitor arrays at the sub-fF levhere allows selection of 0, 1, 2, or 4 copies of each capacitorwell as selection of 4 different clock frequencies for the measgood control of systematics in the measurements.
A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
Pixel FE Overview, Sept 10 2002 33 of 50
K. Einsweiler Lawrence Berkeley National LabATLAS
Brief tour of the layout:•Top level view of the chip (all 5 metals displayed):
A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
Pixel FE Overview, Sept 10 2002 34 of 50
thesized command
K. Einsweiler Lawrence Berkeley National LabATLAS
•Zoom showing EOC blocks and bottom of chip, including syndecoder and readout controller blocks:
•Note that the bottom of the chip is still largely empty.
A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
Pixel FE Overview, Sept 10 2002 35 of 50
or a column pair
at bottom.
K. Einsweiler Lawrence Berkeley National LabATLAS
•Zoom into EOC buffer blocks, each containing 64 hit buffers f(requiring a total vertical height of about 1mm):
•TOT processor blocks feed into EOC blocks, horizontal bus is
A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
Pixel FE Overview, Sept 10 2002 36 of 50
Cs and bias cells with ns:
ht has pair of 8-bit s).
K. Einsweiler Lawrence Berkeley National LabATLAS
•Zoom into bottom of column region, showing integration of DAanalog columns, and CEU+TOT processor with digital colum
•Left analog column has current reference and register bits, rigDACs and register bits (all registers use SEU-tolerant latche
A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
Pixel FE Overview, Sept 10 2002 37 of 50
low bump is preamp, ght end includes d logic for control of
K. Einsweiler Lawrence Berkeley National LabATLAS
•Zoom into Pixel FE block:
•Left of bump, can see 10 SEU-tolerant latches. Lower right becenter is feedback, top is second stage and discriminator. Rileakage compensation capacitors and additional 4 latches anhits, calibrations, and digital injection.
A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
Pixel FE Overview, Sept 10 2002 38 of 50
):
d TE information for stamp input, plus
aking with CEU for
K. Einsweiler Lawrence Berkeley National LabATLAS
•Zoom into readout region of pixel (two back-to-back columns
•Central region includes dual 8-bit differential SRAM for LE aneach pixel plus address ROM. Everything is differential (timeRAM and ROM output).
•Left and right sides contain hit logic, sparse scan, and handshdata transfer.
A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
Pixel FE Overview, Sept 10 2002 39 of 50
le includes two ent FE-I chips.
is FE-I1A, with 10fF, the second is B, with Cfb=5fF.
le also includes -I1, Analog Test , LVDS Buffer chip, IC and VDC opto-, and several other l test chips.
e are 112 potentially reticles on a wafer.
K. Einsweiler Lawrence Berkeley National LabATLAS
Reticle for FE-I1 engineering run:
Reticdiffer
OneCfb=FE-I1
ReticMCCChipDORchipssmal
Thergood
A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
Pixel FE Overview, Sept 10 2002 40 of 50
esrived in Jan 02: for 2.5M transistor
e performed close to d by large HSPICE
d problem. Yield to egisters working, and ore striking, the good r, or along the
(few percent of analog tests, so
nd fault analysis was d at back-end yield (3%), and very ostly supply shorts).
tern seen in first 12 , but very large
K. Einsweiler Lawrence Berkeley National LabATLAS
FE-I1 Performance and Yield IssuFirst wafers from 12-wafer Engineering Run ar
•All blocks worked roughly as expected. Remarkable successchip submitted in new process !
•All performance features, even for new analog front-end, havexpectations. Even threshold dispersion and timewalk, studiesimulations, agree reasonably well with the simulations.
•However, it was quickly realized that there was a serious yielpass simple selection criteria (analog/digital currents OK, all rbasic digital inject test working) was only about 15%. Even mchips were all confined to a small area in the core of the wafeextreme edges.Finally, chips that passed basic register teststransistors tested), would usually be perfect for full digital anddefect density was not an issue.
•Extensive investigations of failure modes have been made, aperformed by the foundry. Four additional wafers, initially helprocessing, were sent for evaluation. They showed very low basic failure modes consistent with metallization problems (m
•Example of wafer map of first wafer probed shows typical patwafers. We find very little variation within a lot or wafer groupvariations in yield between groups !
A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
Pixel FE Overview, Sept 10 2002 41 of 50
r A chips):
ed, and othe colors s with working Global r.
-2
0
2
4
6
8
olumns12
t = 110 t = 110
K. Einsweiler Lawrence Berkeley National LabATLAS
Wafer Map for SESB23T (good column pairs fo
•Chips with no data appear White, bad Global Registers are Rrepresent the Pixel Register test results. There are 18 (3) chipRegisters and 9 (8) column pairs working in the Pixel Registe
C2 4 6 8 10
Ro
ws
2
4
6
8
10
12Nen
FE-IA Number of Good Columns wafer 23 map
Nen
A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
Pixel FE Overview, Sept 10 2002 42 of 50
r B chips):
ed, and othe colors s with working Global r.
-2
0
2
4
6
8
olumns12
= 112 = 112
K. Einsweiler Lawrence Berkeley National LabATLAS
Wafer Map for SESB23T (good column pairs fo
•Chips with no data appear White, bad Global Registers are Rrepresent the Pixel Register test results. There are 17 (2) chipRegisters and 9 (8) column pairs working in the Pixel Registe
C2 4 6 8 10
Ro
ws
2
4
6
8
10
12
Nent
FE-IB Number of Good Columns wafer 23 map
Nent
A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
Pixel FE Overview, Sept 10 2002 43 of 50
, and some fault nd two new lots were
significant investment etallization stage. No endor claims no other nular NMOS (unique brication issues ay be relevant, and is year. behavior. For eight currents and register ts, including perfect ield was 64%.r a single wafer
ge “donut of death” in usually showed
ld. This seems ween lots. nsistent from wafer to ntities (about 2K$).
K. Einsweiler Lawrence Berkeley National LabATLAS
•Concurrent and similar problems seen with CMS APV25 chipanalysis clues were found. Two new lots were run for CMS arun for ATLAS, with delivery in May/June.
•The vendor has not uncovered anything very useful, despite of resources. At this stage, I believe basic problems are in mclear evidence for real problems with our design. However, vcustomers, besides CERN, see such wild yield variations. AnCERN feature) extensively investigated by foundry, but no fauncovered. Recent change of metallization fill rules by IBM mwe will see what happens with our next run of two lots late th
•First of the two replacement ATLAS lots had “expected” yieldwafers recently sent for bump-bonding, “simple” cuts (supplytests) give an average yield was 79%. For more complete cudigital operation of every pixel and EOC buffer, the average y
•Second of the replacement lots had intermediate behavior. Foprobed so far, the yield for complete cuts was 25%, with a larthe wafer where all chips failed even basic register tests, andsupply shorts on one or both supplies.
•The basis for our production planning is an assumed 50% yieachievable, but there will apparently be large fluctuations betFortunately, within one lot, the yield behavior seems fairly cowafer. In addition, the wafer cost is relatively low in large qua
A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
Pixel FE Overview, Sept 10 2002 44 of 50
isters, DACs, perfect is wafer.
1002A
1003A9
1103A1103B2
1004A0
1104A1104B99
1005A9
1105A1105B99
1205A1205B9
1006A9
1106A1106B99
1206A1206B8
1007A9
1107A1107B99
1207A1207B99
1008A9
1108A1108B99
1208A1208B9
1009A9
1109A1109B99
1010A9
1110A1110B9
1011A
S-Pixel(LBL) - Fri Sep 06 12:17:50 2002avedra
K. Einsweiler Lawrence Berkeley National LabATLAS
Typical wafer from good replacement lot:
•Map shows chips passing complete cuts (supply surrents, regdigital pixels and EOC buffers). This has a yield of 73% for th
0501A0501B 0601A0601B 0701A0701B 0801A0801B
0302A0302B92
0402A0402B99
0502A0502B99
0602A0602B99
0702A0702B99
0802A0802B99
0902A0902B99
1002B
0203A0203B90
0303A0303B99
0403A0403B99
0503A0503B99
0603A0603B99
0703A0703B89
0803A0803B99
0903A0903B99
1003B9
0204A0204B89
0304A0304B9
0404A0404B99
0504A0504B99
0604A0604B99
0704A0704B99
0804A0804B99
0904A0904B99
1004B9
0105A0105B9
0205A0205B99
0305A0305B99
0405A0405B99
0505A0505B99
0605A0605B99
0705A0705B99
0805A0805B99
0905A0905B99
1005B9
0106A0106B99
0206A0206B99
0306A0306B99
0406A0406B99
0506A0506B99
0606A0606B99
0706A0706B99
0806A0806B99
0906A0906B99
1006B9
0107A0107B99
0207A0207B99
0307A0307B99
0407A0407B99
0507A0507B99
0607A0607B99
0707A0707B99
0807A0807B99
0907A0907B99
1007B9
0108A0108B99
0208A0208B99
0308A0308B99
0408A0408B99
0508A0508B99
0608A0608B99
0708A0708B99
0808A0808B99
0908A0908B99
1008B9
0209A0209B99
0309A0309B99
0409A0409B99
0509A0509B99
0609A0609B99
0709A0709B99
0809A0809B99
0909A0909B99
1009B9
0210A0210B9
0310A0310B98
0410A0410B99
0510A0510B99
0610A0610B99
0710A0710B99
0810A0810B99
0910A0910B99
1010B9
0311A0311B9
0411A0411B99
0511A0511B99
0611A0611B99
0711A0711B99
0811A0811B99
0911A0911B99
1011B9
0512A0512B 0612A0612B9
0712A0712B 0812A0812B
0405A0405B97
04 05 BCOLUMN ROW FE TYPE
Number of good column pairs
Chosen chip
NOTCH
Wafer WE8P5WT
ATLAA. Sa
Summary:
Selected FE-IA: 79
Selected FE-IB: 83
A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
Pixel FE Overview, Sept 10 2002 45 of 50
Entries 95
Amplitude 2.389± 12.76
Median 0.1643± 47.99
Sigma 0.2045± 1.249
(mA)2 54 56 58 60
Entries 95
Amplitude 2.389± 12.76
Median 0.1643± 47.99
Sigma 0.2045± 1.249
WT)
Entries 83
Amplitude 5.302± 28.18
Median 0.0184± 6.039
Sigma 0.01372± 0.09416
(fF)7 7.5 8
Entries 83
Amplitude 5.302± 28.18
Median 0.0184± 6.039
Sigma 0.01372± 0.09416
T)
K. Einsweiler Lawrence Berkeley National LabATLAS
Examples of plots from wafer probing:Entries 79
Amplitude 5.093± 23.96
Median 0.03467± 35.2
Sigma 0.03863± 0.2215
(mA)30 31 32 33 34 35 36 37 38 39 400
5
10
15
20
25
Entries 79
Amplitude 5.093± 23.96
Median 0.03467± 35.2
Sigma 0.03863± 0.2215
FE-I1AOperating Digital Current map(mA) (Wafer WE8P5WT)
40 42 44 46 48 50 50
2
4
6
8
10
12
14
16
FE-I1AOperating Analogue Current map(mA) (Wafer WE8P5
Entries 95
Amplitude 1.524± 11.07
Median 0.7836± 210.6
Sigma 0.6581± 6.481
(uA)180 190 200 210 220 230 240 2500
2
4
6
8
10
12
Entries 95
Amplitude 1.524± 11.07
Median 0.7836± 210.6
Sigma 0.6581± 6.481
FE-I1A Average DAC current at 255 map(mA) (Wafer WE8P5WT)
5 5.5 6 6.50
5
10
15
20
25
30
FE-I1B Av FeedBack Capacitor(fF) map(Wafer WE8P5W
A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
Pixel FE Overview, Sept 10 2002 46 of 50
E-I2) by the end of this s that if all goes well, .
resolved.
itial dispersion was fetime of the chip has sigma of better than
mperature from +20C ilarly, a total dose of
gma. Measurements te at high total dose.
o cause re-dispersion.m matching errors has been performed, pproach predicted the timize the sizing of all e-offs between speed sent design should erformance.
K. Einsweiler Lawrence Berkeley National LabATLAS
Improvements for next generation (F•Upgrade program is underway, and new submission expected
year. This should be a pre-production quality chip. This meanmodules built with this chip can (and will ?) be used in ATLAS
•A number of minor problems were uncovered, and are easily
Serious issues for FE-I2:•Threshold dispersion and “re-dispersion”: Although the in
roughly as expected, managing this dispersion through the liproven challenging. Can typically tune a given assembly to a100e for a given set of conditions. However, changing the teto -10C re-disperses the thresholds to about 300e sigma. Simabout 300KRad re-disperses the thresholds to about 300e siat LBL Cyclotron show that this re-dispersion does not saturaFinally, small changes in the global threshold adjustment als
•Threshold dispersion and re-dispersion in our design arise frobetween identical transistors. A careful Monte Carlo analysisusing the CERN matching data for IBM (Anelli thesis). This aobserved threshold dispersion, and has now been used to optransistors in the front-end. In some cases, there are real trad(timewalk) and threshold dispersion. Modifications to the prereduce the dispersion by a further 20-30% with little loss in p
A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
Pixel FE Overview, Sept 10 2002 47 of 50
thesis of G. Anelli:
s in matched dicates some large
in the timewalk s on AGND, which in IP (the preamplifier ur design are in weak sitive to small n is VDDA, which mainly used as a
bias scheme, which liminate this problem.
∆
1 1.2
]
0.28
EnclosedNMOS VT matchingversusdevice size
K. Einsweiler Lawrence Berkeley National LabATLAS
•Each device had its VT modified using sigma taken from the
•Very little is known about additional differential threshold shifttransistors that can occur after irradiation, etc. CERN data inirradiation effects that may be consistent with our results.
•Bias distribution: Significant top-bottom variations are seenperformance of FE-I1. These arise from internal voltage dropturn modify the Vgs used to distribute large bias currents likeinput transistor bias, typically 8µA). All mirror transistors in oinversion (sub-threshold), so the mirrored current is very senchanges in Vgs. In addition, the reference plane for our desiguses the LM top metal and is a low-resistivity plane. AGND iscurrent return, and has much higher resistivity. A new active distributes Vgs differentially has been designed, and should e
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
0 0.2 0.4 0.6 0.8 1 1.2
(Gate Area)-1/2 [1/µm]
∆V
th [
mV
]23.2 / 5
11.2 / 2
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A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
Pixel FE Overview, Sept 10 2002 48 of 50
-bit threshold adjust es mentioned above e predictability of the
he local DAC. New r to the ones used at rity and control. lobal Register, and chip !) Initial the 55MeV Cyclotron PS (20GeV protons)
. This would lead to global “periodic
layout of the latches in the Command and data even during
valuate or measure. nd individual bit flips dividual hits), so logic would be very
K. Einsweiler Lawrence Berkeley National LabATLAS
•Threshold control: The very compact local DACs used for 5have very poor linearity. In addition, the bias distribution issucause significant top/bottom variations. In order to optimize ththreshold tuning process, we need to improve the quality of tdesign will use 6-bit DAC based on identical unit cells (similathe bottom of column), and should result in much better linea
•SEU-tolerance: All configuration data (Command Register, GPixel Register) is stored in SEU-tolerant latches (40,547 per measurements of upset rates of our SEU-tolerant latches at showed very low cross-sections. Measurements at the CERNshowed more than an order of magnitude higher upset ratessomewhat unreliable operation at the LHC, despite proposedreset” every few hundred seconds in ATLAS TDAQ.
•We will improve the SEU-tolerance of FE-I2 by improving thein the Pixel latches, and by using a triple-redundancy schemeGlobal latches. This should result in very stable configurationoperation of B-layer at design luminosity.
•SEU effects in the data paths (dynamic) are much harder to eAll state machines were designed to use no hidden states, awill normally have very localized effects (corruption/loss of ineffects are expected to be small. Further hardening of all thischallenging, and is not believed to be necessary.
A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
Pixel FE Overview, Sept 10 2002 49 of 50
els, in order to
e top are ganged. pixels overlapped by ing modified front-alk for all pixels.
K. Einsweiler Lawrence Berkeley National LabATLAS
•Special pixels: ATLAS pixel sensor contains four types of pixprovide 100% coverage in multi-chip module:
•Pixels at the two edges are 600µ instead of 400µ. Pixels at th•Capacitive loads for the ganged pixels, as well as the normal
ganging traces, are much higher. Plan to deal with this by usends with 2*IP and 4*IP, in order to provide acceptable timew
A T L A S F E O v e r v i e w , P i x e l 2 0 0 2 , C a r m e l , S e p t e m b e r 2 0 0 2
Pixel FE Overview, Sept 10 2002 50 of 50
h performance pixel
f readout. It is ion-tolerant layout ness without latch-up
S requirements. version of FE chip, to
xperience with four ried from 3% yield to
K. Einsweiler Lawrence Berkeley National LabATLAS
Summary•Lengthy design program has led to very sophisticated and hig
arrays meeting all ATLAS pixel detector requirements.•Present design contains 2.5M transistors for 2880 channels o
implemented in a commercial 0.25µ technology, using radiattechniques to achieve 60MRad tolerance and good SEU hardor other fatal effects.
•First prototypes now extensively evaluated and meet all ATLAModest improvements being implemented in pre-production be submitted by the end of 2002.
•There remain uncertainties in the yield for the FE chip. Our egroups of wafers, all made using the same mask set, has va79% yield for simple selection criteria.
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