testing stt-mram: manufacturing defects, fault models, and
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Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions
TTTC’s McCluskey Doctoral Thesis Award Contest
PhD graduate: Lizhou Wu1
Promotor: Prof. Said Hamdioui1
Co-supervisors:Mottaqiallah Taouil1Erik Jan Marinissen2
Siddharth Rao21 2
© Lizhou Wu, TU Delft McCluskey Award Contest @ITC’21: Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions© Lizhou Wu, TU Delft
Motivation
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• Industry is commercializing STT-MRAM• Testing is the last chance to check and
guarantee the required IC quality
<Samsung>
No dedicated test solutions exist
• Today’s commercial test solutions Assumption: ideal device & use a linear resistor
R-V curve
Real measurement data @IMEC Good STT-MRAM device
?Defective STT-MRAM device
Need to close the gap
<Everspin>
© Lizhou Wu, TU Delft McCluskey Award Contest @ITC’21: Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions© Lizhou Wu, TU Delft
Contributions• Part 1:
• Survey on manufacturing process and defects• Conventional test for interconnect defects
• Part 2:• Device-Aware Test (DAT) approach• DAT for pinhole defects• DAT for synthetic anti-ferromagnet flip (SAFF) defects• DAT for intermediate (IM) state defects
• Part 3: • Magnetic coupling model• Magnetic-field-aware compact model of pMTJ
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Fault space
© Lizhou Wu, TU Delft McCluskey Award Contest @ITC’21: Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions© Lizhou Wu, TU Delft
Part1-C1: Survey on Manufacturing Process and Defects
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• STT-MRAM manufacturing process
CMOS FEOL
CMOS BEOL
MTJ fabrication& integration
FEOL BEOL
Transistor Interconnect/ contact
MTJ device
Material impurity Crystal imperfection Pinholes in gate
oxides Shifting of dopants Patterning proximity etc.
Open vias/contacts
Irregular shapes Big bubbles Small particles etc.
Pinhole defects in MgO barrier
SAFF defects Intermediate
state defects Extreme thickness
variation of TB MgO/CoFeB interface
roughness Atom inter-diffusion Redepositions on
MTJ sidewalls Magnetic layer
corrosion etc.
• STT-MRAM manufacturing defects
[L. Wu et al., ITC, 2018]
© Lizhou Wu, TU Delft McCluskey Award Contest @ITC’21: Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions© Lizhou Wu, TU Delft
Part1-C2: Conventional Test for Interconnect Defects
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• All defects are modeled as linear resistors • Resistive defects in a 1T-1MTJ cell
[L. Wu et al., TETC, 2019]
• Fault modeling results: e.g., bridges (subset)
Defect-free MTJ
Resistive defects Easy-to-detect faults March test: e.g. March C-
© Lizhou Wu, TU Delft McCluskey Award Contest @ITC’21: Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions© Lizhou Wu, TU Delft
Part2-C1: Device-Aware Test (DAT) Approach
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Defect modeling
Fault modeling(fault analysis)
Test solutiongeneration
Defects
Algorithms
DFT
BIST/R
1 2 3
Fault space
[Patent NLO ref: P6086853NL]
Optimized Defective Device Model
[L. Wu et al. ITC, 2019 ]
© Lizhou Wu, TU Delft McCluskey Award Contest @ITC’21: Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions© Lizhou Wu, TU Delft
Part2-C2: DAT for Pinhole Defects in MgO Tunnel Barrier
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1. Defect char. & modeling 2. Fault modeling 3. Test solution generation• Easy-to-Detect (EtD) faults:
• March test: {⇑(w1); ⇑(r1)}
• Hard-to-Detect (HtD) faults• Stress test: e.g., hammering w1
Aph>0.35% Aph≤0.35%Easy-to-detect faults:<1/0/–>,<1/L/–><0w1/L/–>,<0w1/0/–> <1w1/0/–>,<1w1/L/–><1r1/0/0>,<1r1/L/0>
Hard-to-detect faults:<0/L/–>,<1/U/–><1w0/L/–>,<0w1/U/–><0w0/L/–>,<1w1/U/–><1r1/U/1>,<1r1/U/?><1r1/U/0>,<0r0/L/0>
[L. Wu et al., ETS, 2019] (BPA nomination)
Device-aware test Conventional test
Unique & realistic faults
Reduced escapes & optimized tests Test escapes
Wrong sensitized faults
© Lizhou Wu, TU Delft McCluskey Award Contest @ITC’21: Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions© Lizhou Wu, TU Delft
Part2-C2: DAT for Synthetic Anti-Ferromagnet Flip (SAFF) Defects
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1. Defect char. & modeling 2. Fault modeling• Lead to an intermittent fault:
PNPSF1i=<1;1;1;1;1;1;1;1;1w0/1i/–>
3. Test solution generation• March algorithm with magnetic
writes• {⇑(w0H); ⇑(r0)}
[L. Wu et al., ITC, 2020] (Distinguished paper & BPA candidate)
Good VS. Defective
Flipped RL and HL
Horizontally flippedR-H loop
© Lizhou Wu, TU Delft McCluskey Award Contest @ITC’21: Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions© Lizhou Wu, TU Delft
Part2-C3: DAT for Intermediate (IM) State Defects
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1. Defect char. & modeling• RIM in addition to RP and RAP• RP<RIM<RAP• Probabilistic (intermittent)
2. Fault modeling• Lead to intermittent write
transition faults: W1TFUi=<0w1/Ui/–>W0TFUi=<1w0/Ui/–>
3. Test solution generation• Test with weak write operations• {⇕ (w0); ⇑(w1,r1); ⇑(�w0,r1)}}
[L. Wu et al., DATE, 2021] (BPA nomination) [L. Wu et al., Trans. Comput., 2021]
© Lizhou Wu, TU Delft McCluskey Award Contest @ITC’21: Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions© Lizhou Wu, TU Delft
Part3-C1: Magnetic Coupling Model• Magnetic field interference is a problem to STT-MRAMs!
10[L. Wu et al., DATE, 2020] (Best Paper Award)
• External magnetic fields• Vulnerable to external field• Counter-measures: In-package magnetic
shield enhances magnetic immunity
[K. Lee et al., Global foundries, VLSI, 2018]
Shield
• Internal magnetic fields• STT-MRAM device consists of dozens of
ferromagnetic layers• Each layer generates a stray field, leading to
intra- and inter-cell magnetic coupling
© Lizhou Wu, TU Delft McCluskey Award Contest @ITC’21: Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions© Lizhou Wu, TU Delft
Part3-C1: Magnetic Coupling Model• Intra-cell stray field measurement
• Size dependence of 𝐻𝐻s_intraz
• electrical Critical Diameter
• eCD= 4𝜋𝜋� 𝑅𝑅𝑅𝑅𝑅𝑅𝑃𝑃
, (𝑅𝑅𝑅𝑅 = 4.5 Ω∙𝜇𝜇m2)
11[L. Wu et al., DATE, 2020] (Best Paper Award)
• Inter-cell stray field simulation• All direct neighbors are in symmetric positions,
same for diagonal neighbors• 𝐻𝐻s_inter varies with the number of 1s in direct
and diagonal neighbors
Largest 𝐻𝐻s_interz when all 8
neighboring cells are in state 1
NP8=255
NP8=0
Smallest 𝐻𝐻s_inter when all 8 neighboring cells are in state 0
Smaller MTJ size (eCD) higher 𝐻𝐻s_intra
z
© Lizhou Wu, TU Delft McCluskey Award Contest @ITC’21: Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions© Lizhou Wu, TU Delft
Part3-C2: Magnetic-Field-Aware Compact Model of pMTJ
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[L. Wu et al., IEEE TCAD, 2021] (under review)
• Magnetic-field-aware compact model of pMTJ
• Physics-based, PVT variations• Different magnetic field configurations• Electrical/magnetic co-simulation of
MTJ/CMOS hybrid circuits
• MTJ electrical characteristics under various magnetic configurations
R-V loop vs. Hext
Write error rate vs. Hext
© Lizhou Wu, TU Delft McCluskey Award Contest @ITC’21: Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions© Lizhou Wu, TU Delft
Part3-C2: Magnetic-Field-Aware Compact Model of pMTJ
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[L. Wu et al., IEEE TCAD, 2021] (under review)
• SPICE-based circuit simulations• 1T-1MTJ cell• 3x3 STT-MRAM array • Peripheral circuits• PVT variations + various magnetic configurations
• Design space exploration• eCD=35nm, pitch=3xeCD
10
20
30
40
t p(1
w0)
(ns)
10
20
30
40
t p(0
w1)
(ns)
Hext= 0Oe Hext= 500Oe
© Lizhou Wu, TU Delft McCluskey Award Contest @ITC’21: Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions© Lizhou Wu, TU Delft
Industrial Impact• Fast and robust STT-MRAM design and verification
• Magnetic coupling model maximize STT-MRAM density• Compact pMTJ model fast and efficient Spintronic circuit designs
• Test escape reduction and quality improvement• Accurate defect and fault models• High-quality test solutions
• Efficient yield learning• Defects have unique fault signatures
• Test time optimization• Reduced functional test
• General applicability of DAT• Other memories; e.g., RRAM, PCM, FeRAM• Logic circuits at advanced technology nodes
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DAT
Detectedfails
Realfails
Testescapes(DPM)
Yieldloss
($$$)Detected defects
Detectedfails
Realfails
Testescapes(DPM)
Yieldloss
($$$)
Detected defects
Better defect/fault modelling
Better Test solutions
© Lizhou Wu, TU Delft McCluskey Award Contest @ITC’21: Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions© Lizhou Wu, TU Delft
Summary • 14 peer-reviewed papers
• 9 conference papers:
• 5 journal papers:
• 5 awards/nominations • 1 best paper award: DATE’20• 1 distinguished paper & BPA candidate: ITC’20 (BPA to be announced at ITC’21)• 2 BPA nominations: ETS’19, DATE’21• Graduated Cum Laude (less than 3% of TUD PhDs get this honor)
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International Test Conference ITC 2018, 2019, 2020Design Automation & Test in Europe Conference DATE 2020 (x2), 2021European Test Symposium ETS 2019, 2020VLSI Test Symposium VTS 2020
IEEE Trans. Emerg. Topics Comput. TETC 2019IEEE Trans. Very Large Scale Integr. Syst. TVLSI 2021IEEE Trans. Computer TC 2021 IEEE Trans. Comput.-Aided Design Integr. Circuits Syst. TCAD 2021 (under review)
ACM J. Emerg. Technol. Comput. Syst. JETC 2021 (under review)
[Ref: L. Wu, doctoral thesis, TU Delft, 2021]
© Lizhou Wu, TU Delft McCluskey Award Contest @ITC’21: Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions© Lizhou Wu, TU Delft
List of Publications• International Conferences:
[1] L. Wu et al., “Characterization and fault modeling of intermediate state defects in STT-MRAM,” IEEE/ACM DATE,2021, pp. 1-6. [2] L. Wu et al., “Characterization, modeling and test of synthetic anti-ferromagnet flip defect in STT-MRAMs,” in IEEE ITC, 2020, pp. 1-10. [3] L. Wu et al., “Device-aware test for emerging memories: enabling your test program for DPPB level,” in IEEE ETS, 2020, pp. 1-2.[4] R. Bishnoi, L. Wu et al., “Special session–emerging memristor based memory and CIM architecture: test, repair and yield analysis,” in IEEE VTS, 2020, pp. 1-10.[5] L. Wu et al., “Impact of magnetic coupling and density on STT-MRAM performance,” in IEEE/ACM DATE, 2020, pp. 1211-1216. [6] G. C. Medeiros, L. Wu et al., “A DFT scheme to improve coverage of hard-to-detect faults in FinFET SRAMs,” in IEEE/ACM DATE, 2020, pp. 792-797. [7] M. Fieback, L. Wu et al., “Device-aware test: a new test approach towards DPPB level,” in IEEE ITC, 2019, pp. 1-10.[8] L. Wu et al., “Pinhole defect characterization and fault modeling for STT-MRAM testing,” in IEEE ETS, 2019, pp. 1-6. [9] L. Wu et al., “Electrical modeling of STT-MRAM defects,” in IEEE ITC, 2018, pp. 1-10.
• International Journals:[1] L. Wu et al., “Characterization, Fault Modeling, and Test of Intermediate State Defects in STT-MRAM,” IEEE TC, pp. 1-14, 2021. [2] L. Wu et al., “A Field-Aware Compact Model of Perpendicular Magnetic Tunnel Junction for STT-MRAM,” IEEE TCAD, pp. 1-14, 2021. (Under review)[3] G.C. Medeiros, M. Fieback, L. Wu et al., “Hard-to-Detect Faults in FinFET SRAMs: Analyses and Test Solutions,” IEEE TVLSI, pp. xx-xx, 2021. [4] M. Fieback, G.C. Medeiros, L. Wu et al., “Defect and fault modeling, and test development framework for RRAM,” ACM JETC, pp. xx-xx, 2021. (Under review)[5] L. Wu et al., “Defect and fault modeling framework for STT-MRAM testing,” IEEE TETC, pp. 1-15, 2019.
• Other Publications[1] L. Wu et al., “Survey on STT-MRAM testing: failure mechanisms, fault models, and tests,” arXiv preprint, pp. 1-24, Jan. 2020.
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© Lizhou Wu, TU Delft McCluskey Award Contest @ITC’21: Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions© Lizhou Wu, TU Delft
Acknowledgement
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Guilherme C. Medeiros
Moritz Fieback
MottaqiallahTaouil
SiddharthRao
Erik Jan Marinissen
Gouri Sankar Kar
Said Hamdioui
WoojinKim
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Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions
PhD graduate: Lizhou Wu1
Promotor: Prof. Said Hamdioui1
Co-supervisors:Mottaqiallah Taouil1Erik Jan Marinissen2
Siddharth Rao21 2
TTTC’s McCluskey Doctoral Thesis Award Contest
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