steven koelmeyer bds(hons)1 reconfigurable hardware for use in ad hoc sensor networks supervisors...

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Reconfigurable Hardware for use in Ad Hoc Sensor NetworksSupervisorsCharles Greif Nandita Bhattacharjee

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Introduction

Overview

Project Aim

Ad Hoc sensor motes

What was Achieved

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Overview

The Smart Dust Project was started at Berkeley University sponsored by DARPA

The aim was to create the smallest possible Ad-Hoc sensor nodes

Small enough that releasing thousands into an environment would be insignificant

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Duck Island

Over 190 nodes including temperature, humidity, barometric pressure, infra-red and cameras

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Overview

Current Technology allows for extremely small wireless devices

Capable of basic packet transmission, limited processing ability and taking sensor samples

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Sensor Motes: Structure

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Sensor Motes: Structure The CPU is an Atmel ATmega128 RISC architecture, internal SRAM, Flash memory

and EEPROM, internal analogue to digital converter

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Sensor Motes: Software

Nodes each run an embedded Operating System called TinyOS

Applications are written in NesC Tools and Utilities are java based

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Limitations

Limiting factors Power Storage Processor size Communication Range

Reconfigurable hardware offers increased processing ability without severely impacting on power

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Reconfigurable Hardware

Reconfigurable hardware comes in the form of: Programmable Logic Devices (PLDs) Complex PLDs Field Programmable Gate Arrays (FPGAs)

FPGAs being the choice for this project

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FPGA Performance Reconfigurable hardware allows for the

flexibility of Microprocessors while providing the speed of an Application Specific Integrated Circuit

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The Reconfigurable Hardware Field Programmable Gate Array (FPGA) Programmed with VHDL After being compiled you end up with a bitstream

entity BUFFERx8 is port ( in1: in STD_LOGIC;

out1: out STD_LOGIC);end bufferx8;

architecture STRUCTURE of BUFFERx8 is begin buf1 : process (in1) begin

if ( in1 = '1' ) thenout1 <= '1';

elseout1 <= '0';

end if; end process;

end STRUCTURE;

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Bit stream format

Xilinx ASCII BitstreamCreated by Bitstream D.27Design name: statemachine_5_out.ncdArchitecture: spartan2Part: 2s200pq208Date: Tue Sep 28 13:58:32 2004Bits: 13358401111111111111111111111111111111110101010100110010101010101100110001100000000000010000000000000010000000000000000000000000000011100110000000000010110000000000001000000000000000000000000000100010011000000000001001000000000000100000000100000000011111100101101001100000000000011000000000000010000000000000000000000000000000000110000000000001000000000000001

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Boundary Scan

Boundary Scan was originally developed by the Joint Test Action Group (JTAG) for in-circuit testing of complex logic

Replace “Bed of Nails” on single layer circuits Serial interface using instructions for different

operations JTAG is controlled on devices through a Test

Access Port

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Example Instruction Set

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TAP Controller

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Testing

Initial testing was done using a newer Spartan 2 XS200 digilab board

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Design and Development

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Simulation

Simulation can be performed by compiling the TinyOS code for PC instead of sensor motes

Can be run in real time Also able to use file I/O functions FPGA was attached to the parallel port

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Simulation

Before downloading the bit stream the FPGA must be reset

A specific pattern of signals into the chip must be followed down to hundreds of nanoseconds.

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Simulation

A bit stream download in simulation takes 3 minutes

Does not wait for transmissions No errors or retransmissions Runs at computers CPU speed

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Implementation

FPGA is mounted onto a circuit board Sit on top as a daughter board

<Picture of board here>

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Implementation

Bit stream is downloaded to the Base Station and broadcast over the wireless link

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Applications

Image analysis Car Number Plates Data Compression Face Recognition

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Insert demonstration here