status report 2010/10/5 atsushi nukariya. revision of control manager (1) ・ the things which...
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Status report
2010/10/5
Atsushi Nukariya
Revision of control manager (1)
・ The things which control manager controls are as follows.
1. Double buffer on FPGA and GEMFE2 ( FIFO selection )
2. FIFOx3 on FPGA
3. Initialization of DAC
4. Clock
5. SiTCP
・ Control manager shouldn’t control too many things, so these function must be allocated on smaller parts.
→ Design became more complicated, so I decided to revise control manager.
・ At first, I noticed that code of VHDL had mixed variable and signal.
→ I rewrote all VHDL code by signal.
→ Double buffer didn’t work correctly in Test Bench.
→ I rewrote all VHDL code by variable.
→ The big change couldn’t be seen.
Revision of control manager (2)
Revision of control manager (3)
・ At the same time when double buffer enables writing, double buffer enables reading.
・ Case that data is sent from the second double buffer of GEMFE2-A is as follows.
・ FIFOx3 didn’t write 0x061222, on the other hand double buffer read 0x061222 correctly. (○)
・ Input data
http://www.cns.s.u-tokyo.ac.jp/~nukariya/GEMFE2/20101001-2.txt
Revision of control manager (4)
・ Case that data is sent from the first double buffer of GEMFE2-B is as follows.
・ FIFOx3 wrote 0x061222 correctly, but buffer read 0x000000. (○)
・ From this result, I notice that FIFOx3 spends 3 RCLK (150 ns) to read data from double buffer, and the first data of double buffer can’t be written.
Revision of control manager (5)
・ I rewrote code of VHDL so that behavior of counter 6+1 bits will be seen.
・ I doubt that problem takes place immediately after changing RSTB and CRST.
・ Input data immediately after changing RSTB and CRST is as follows.
Revision of control manager (6)
・ Output data when input data is sent from the second double buffer of GEMFE2-A is as follows.
・ FIFO can’t read data from double buffer correctly.
Revision of control manager (7)
・ Output data when input data is sent from the first double buffer of GEMFE2-B is as follows.
・ FIFO can read data from double buffer correctly.
・ After this time, wave form is same to this.
Revision of control manager (8)
・ I make state “STATE_WAIT” that make FPGA wait after changing RCLK and CRST.
・ State which Input data is sent from the first double buffer of GEMFE2-A is as follows.
Revision of control manager (9)
・ Output data when input data is sent from the second double buffer of GEMFE2-A is as follows.
・ FIFO can’t read data from double buffer correctly.
Revision of control manager (10)
・ Output data when input data is sent from the first double buffer of GEMFE2-B is as follows.
・ FIFO can read data from double buffer correctly.
・ After this time, wave form is same to this.
→ RCLK and CRST aren’t important.
Revision of control manager (11)
・ Until now, when signal of double buffer empty becomes 0, FIFOx3 enables writing.
→ Even if double buffer empty is 0, FIFOx3 doesn't enable writing while 1 clock after changing "double buffer empty" 1 into 0.
→ I revised code, and I found that data could be sent correctly.
Changing input data (1)
・ Until now, number of input data is same.
→ Changing number of input data randomly.
・ An example of input data is as follows.
・ 0x200000 is inputted 8 times continuously.
・ Input data
http://www.cns.s.u-tokyo.ac.jp/~nukariya/GEMFE2/20101001-1.txt
Changing input data (2)
・ Output data is as follows.
・ Data is outputted correctly.
Changing input data (3)
・ Next I think that data is sent from double buffer before all data of FIFOx3 are outputted.
・ An example of input data is as follows.
・ Input data
http://www.cns.s.u-tokyo.ac.jp/~nukariya/GEMFE2/20101001-3.txt
Changing input data (4)
・ Output data is as follows.
・ Data isn’t outputted correctly.
・ Sent data is stopped.
Changing input data (5)
・ Part of sent data which is stopped is as follows.
・ ○ represents last data which is outputted.
Changing input data (6)
・ I rewrote code taking account of delay of double buffer.
・ An example of input data is as follows.
・ Input data
http://www.cns.s.u-tokyo.ac.jp/~nukariya/GEMFE2/20101001-4.txt
Changing input data (7)
・ Output data is as follows.
・ Data isn’t outputted correctly.
Implementation of Chip Full (1)
・ I implement status of Chip Full.
・ An example of Input data is as follows.
・ Input data
http://www.cns.s.u-tokyo.ac.jp/~nukariya/GEMFE2/20101005-1.txt
Implementation of Chip Full (2)
・ Output data which is changed by status of Chip Full.
・ Data has changed correctly.
→ Ex. 0x200000 + 0x800000 = 0xa00000
Plan・ I finished making socket libraries used in Windows and Linux, so I will
make software that displays data on PC.
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