spring 2006 1 ee 437 lillevik 437s06-l21 university of portland school of engineering advanced...
Post on 01-Jan-2016
214 Views
Preview:
TRANSCRIPT
Spring 2006
Lillevik 437s06-l21 1University of Portland School of Engineering
EE 437
Advanced ComputerArchitecture
Lecture 21
MSP shared cachedMSI protocol
MESI protocol
Spring 2006
Lillevik 437s06-l21 2University of Portland School of Engineering
EE 437
Symmetric multiprocessor (SMP)
Memory
...CPU
Memory Controller
CPU
I/O Hub/Bridge
Key Board
Mouse
Monitor
BIOS
EtherNet
PowerSupply
CoolingFan
One address space, uniform access time
Spring 2006
Lillevik 437s06-l21 3University of Portland School of Engineering
EE 437
A simpler model
Each processor has a local cache, one main memory
P1 transactions Pn transactions
Bus transactions
Spring 2006
Lillevik 437s06-l21 4University of Portland School of Engineering
EE 437
Coherency through snooping
Controllers monitor bus to manage local cache
Single shared memory
Local controller
Local controller
Spring 2006
Lillevik 437s06-l21 5University of Portland School of Engineering
EE 437
Coherency requirements
1. Memory operations occur in the order they were issued
2. All reads return the most current value
Spring 2006
Lillevik 437s06-l21 6University of Portland School of Engineering
EE 437
Cache coherency solution
• Monitor bus to see when things change
• Must maintain the “state” of each cache line– Modifed (as in write-back)– Others
Spring 2006
Lillevik 437s06-l21 7University of Portland School of Engineering
EE 437
Two solutions
• Both write-back invalidation: snooped write (another writer) invalidates local copy
• MSI protocol– Three states– Simpler, uses bus a bit more
• MESI protocol: most popular– Four states– Slightly more complex, uses bus less
Spring 2006
Lillevik 437s06-l21 8University of Portland School of Engineering
EE 437
WB invalidation protocol
• Cache states– Modified: dirty, memory inconsistent, local cache has
only valid copy, only one CPU in this state
– Shared: clean, one or more copies, memory consistent
– Invalid: local data is not current, stale
• State transitions– Determined by local controller– States may vary across caches
MSI
Spring 2006
Lillevik 437s06-l21 9University of Portland School of Engineering
EE 437
Processor transactions
• Read (PrRd): read instruction
• Write (PrWr): write instruction
• Misses: if modified, must write back data to memory
Spring 2006
Lillevik 437s06-l21 10University of Portland School of Engineering
EE 437
Bus transactions
• Read (BusRd): memory read
• Write (BusWr): memory write
• Read Exclusive (BusRdX)– Used to request an exclusive copy of data– Generated by a PrWr if data Invalid or Shared– Data returned may be ignored
• Flush: Modified cache performs a WB, resolves inconsistency
Spring 2006
Lillevik 437s06-l21 11University of Portland School of Engineering
EE 437
Processor hits and misses
Action Processor BusRead hit PrRd none
Write hit PrWr none
Read miss PrRd BusRd
Write miss PrWr BusRdX
Invalidates other local copies
Spring 2006
Lillevik 437s06-l21 12University of Portland School of Engineering
EE 437
Bus snooping
Bus ActionBusRd Another processor wants to read line
BusRdX Another processor wants to write line
Spring 2006
Lillevik 437s06-l21 13University of Portland School of Engineering
EE 437
MSI protocol
Bus/snoop generatedProcessor generated
Controller
Observes/Actionwrite miss
read miss
write hitread hit
read hit
Another reader
Another writer
Spring 2006
Lillevik 437s06-l21 14University of Portland School of Engineering
EE 437
Find the coherency?
Action P1 State P2 State P3 State BusData source
P1 read u S I I BusRd mem
P3 read uS I S BusRd
C1 or mem
P3 writes uI I M
BusRdX/Flush
P3
P1 read u S I S BusRd C3
P2 read u S S S BusRd C3
Spring 2006
Lillevik 437s06-l21 15University of Portland School of Engineering
EE 437
MSI performance
• Consider single read-write– Read results in Shared state, BusRd– Write results in Modified state, BusRdX
• Unfortunate Result– Two bus actions– Second, BusRdX, not necessary if line is not
shared with other processors– Suggest a new state, exclusive-clean
Spring 2006
Lillevik 437s06-l21 16University of Portland School of Engineering
EE 437
WB invalidation protocol
• Improved performance vs. MSI
• States– Modified: dirty, memory inconsistent, local cache has
only valid copy
– Exclusive (clean): local cache owns, but not written, one CPU in this state
– Shared: clean, one or more copies, memory consistent
– Invalid: data is not current, stale
MESI
Spring 2006
Lillevik 437s06-l21 17University of Portland School of Engineering
EE 437
Processor transactions
• Read (PrRd): read instruction
• Write (PrWr): write instruction
• Misses: if modified, must write back data to memory
Spring 2006
Lillevik 437s06-l21 18University of Portland School of Engineering
EE 437
Bus transactions
• Read (BusRd): memory read
• Write (BusWr): memory write
• Read Exclusive (BusRdX)• Flush: only one need provide WB data
• Shared (S): new signal– Determines if data already shared– Used with BusRd(S) or BusRd(S#)
Spring 2006
Lillevik 437s06-l21 19University of Portland School of Engineering
EE 437
MESI protocol
Controller
Observes/Action
Bus/snoop generatedProcessor generated
Spring 2006
Lillevik 437s06-l21 20University of Portland School of Engineering
EE 437
MESI protocol
Controller
Observes/Action
Bus/snoop generatedProcessor generated
write hitread hit
read miss
one cache does WB
Another writerAnother readerno bus cycle
write miss
Spring 2006
Lillevik 437s06-l21 21University of Portland School of Engineering
EE 437
Find the coherency?
Action P1 State P2 State P3 State BusData source
P1 read u E I I BusRd(S#) Mem
P3 read uS I S BusRd(S)
C1 or mem
P3 writes uI I M BusRdX/Flush
C3 or mem
P1 read u S I S BusRd(S)
P2 read u S S S
Spring 2006
Lillevik 437s06-l21 23University of Portland School of Engineering
EE 437
Find the coherency?
Action P1 State P2 State P3 State BusData source
P1 read u S I I BusRd Memory
P3 read u S I S BusRd Memory
P3 writes u I I M BusRdX P3
P1 read uS I S
BusRd/Flush
P3 cache
P2 read u S S S BusRd Memory
Spring 2006
Lillevik 437s06-l21 24University of Portland School of Engineering
EE 437
Find the coherency?
Action P1 State P2 StateP3 State
BusData source
P1 read u E I I BusRd(S#) Memory
P3 read u S I S BusRd(S)/Flush P1 cache
P3 writes u I I M BusRdX/Flush’ P3
P1 read u S I S BusRd(S)/Flush P3 cache
P2 read uS S S BusRd(S)/Flush’
P1 or P3 cache
top related