snapv1 top side - casper · snapv1 bottom side fpga 2 sfp+ p2 p1 3 2 1 0 7 6 5 4 11 10 9 8 analog...
Post on 27-Sep-2018
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SNAPv1 Top side
U25: FPGAXC7K160T-2FFG676C
2 SFP+P1 P2
P3: Z-Dok+Host Board
J2: input power1,4: GND3,6: +12VDC
+12VDC FPGA FanRed=+12VDC
J3: JTAG verticalJ11: JTAG right angle
SW3: net sw2 SW4: net sw1
SW2: net sw0 SW5: net sw3
SW1: net program_b
Pi2: 2x20 HDRJTAG, PMBUS, GPIO
U42 U40
U38 U37U36 U35
VCCINT 1.0V
U205V
U18U34
1.8V
3.3V
2.5V
1.0V
1.0V
BRAM
MGTA
MGTA
1.2V
1.8V ADC
1.8V MGT
GND
+12VDC
U2ADC
U5ADC
U12ADC
T9
T11
T5
T7
T1
T3
Analog inputs: 8 10 9 11 4 5 6 7 0 1 2 3
Sample CLK
SynthRef
1PPSin
1PPSout
SynthOut
U23CLKDRV
U23 CLK SEL
U32 CLK SYNTH
J1PMBUS
VCCAUX
2
1 40
39
F1
A1
F20
A20
GN
DV
CC
AU
X_I
O =
1.8
VV
AD
J_F
PG
A =
2.5
V
VC
C3V
3 =
3.3
VV
CC
5V
0 =
5.0
VG
ND
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