sequential logic circuits

Sequential Logic Circuits

CS2052 Computer Architecture

Computer Science & Engineering

University of Moratuwa

Dilum BandaraDilum.Bandara@uom.lk

Blocks of a Microprocessor

2

Literal

Address

Operation

Program

Memory

Instruction

Register

STACK Program CounterInstruction

Decoder

Timing, Control and Register selection

Accumulator

RAM &

Data

Registers

ALU

IO

IOFLAG &

Special

Function

Registers

Clock

Reset

Interrupts

Program Execution Section Register Processing Section

Set upSet up

Modify

Address

Internal data bus

Source: Makis Malliris & Sabir Ghauri, UWE

Sequential Circuits

Binary values of outputs are a function of binary

combination of inputs & previous outputs

Outputs at any given time are dependent on

inputs that are present at that time as well as

previous outputs3

Source: www.electronics-tutorials.ws/sequential/seq_1.html

Sequential Circuits (Cont.)

4

Combinational

Circuitsn inputs

m outputs

Flip-flops

Clock

Source: www.eeweb.com/electronics-quiz/j-k-flip-flop

Flip-Flops

Binary cell capable of storing 1 bit information

Usually has 2 outputs

Output (Q)

Complement of output (Q/)

Output changes only when a clock pulse is applied

State is then maintained

Types

SR Flip-Flop

D Flip-Flop

JK Flip-Flop

T Flip-Flop 5

SR Flip-Flop

S – Set, R – Reset

Output changes only when a clock pulse is applied

When input is 11, output is unpredictable

May change to 0 or 1 depending internal delays

SR should not be pulsed when input is 11

Preventing this is difficult rarely used in circuits 6

S R Qt+1

0 0 Qt No change

0 1 0 Clear to 0

1 0 1 Set to 1

1 1 ? Indeterminate

How SR Flip-Flop Works

7

Source: wikimedia.org

SR Flip-Flop – Logic Representation

8

Source: http://www.circuitstoday.com/flip-flops

D Flip-Flop

D – Data

Inverter is added between S & R inputs

11 input combination is avoided 9

D Qt+1

0 0 Clear to 0

1 1 Set to 1

Responds to falling edge of clock signal

Edge-Triggered Flip-Flops

Change states on either positive-edge (rising edge)

or negative-edge (falling edge) of clock pulse

10

Source: www.electronics-tutorials.ws/counter/count_3.html

JK Flip-Flop

11 input combination is now defined

11

J K Qt+1

0 0 Qt No change

0 1 0 Clear to 0

1 0 1 Set to 1

1 1 Q/t Complement

T Flip-Flop

Toggles output

12

T Qt+1

0 Qt No change

1 Q/t Complement

Registers

Capable of storing a set of bits

Built using Flip Flops

13

CLK – Clock

CD – Clear/Reset

LD – Load

4-bit Register

This is called a parallel-in, parallel-out register

14

Source: http://virtual-labs.ac.in/labs/cse10/reg_cnt_design.html

4-bit Register (Cont.)

15Source: www.edwardbosworth.com

4-bit Serial-In, Serial-Out Register

16

Source: http://virtual-labs.ac.in/labs/cse10/reg_cnt_design.html

Blocks of a Microprocessor

17

Literal

Address

Operation

Program

Memory

Instruction

Register

STACK Program CounterInstruction

Decoder

Timing, Control and Register selection

Accumulator

RAM &

Data

Registers

ALU

IO

IOFLAG &

Special

Function

Registers

Clock

Reset

Interrupts

Program Execution Section Register Processing Section

Set upSet up

Modify

Address

Internal data bus

Source: Makis Malliris & Sabir Ghauri, UWE

Sift Registers

Multiply 5 by 2, 5 by 4, 5 by 8

Divide 48 by 2, by 4, by 8

Can sift bits either to left or right

Basic shift register is same as serial-in, serial-

out register

18

Source: http://virtual-labs.ac.in/labs/cse10/reg_cnt_design.html

Serial-In, Parallel-Out Shift Register

There are also

Parallel-in, serial out shift registers

Bidirectional shift registers

19

Source: http://virtual-labs.ac.in/labs/cse10/reg_cnt_design.html

Binary Counters

Register that goes through a predetermined

sequence of states is called a counter

e.g., 000, 001, 010, …. 110, 111

e.g., 001, 010, 100, 001, 010, …

Useful in counting, timing, generating patterns, etc.

20

Example – 3-bit Binary Counter

Suppose we want to count from 0 to 7

21Source: http://osp.mans.edu.eg/cs212/Seq_circuits_counter-design_ex_1_5.htm

Example – Counter (Cont.)

Suppose we want to count from 0 to 7

000

001

010

011

100

101

110

111

000

…22

Alternate

Change if all lower order bits

(in previous round) were 1s

Build counter using JK Flip Flops

Excitation Tables

Truth tables tell us what will be the output for a

given combination of inputs

Sometimes we want to find what inputs to give to

achieve a desired output

Can be achieved via excitation tables

23

J K Qt+1

0 0 Qt

0 1 0

1 0 1

1 1 Q/t

Qt Qt+1 J K

0 0

0 1

1 0

1 1

Excitation Table – JK Flip Flop

24

Qt Qt+1 J K

0 0

0 1

1 0

1 1

J K Qt+1

0 0 Qt

0 1 0

1 0 1

1 1 Q/t

Qt Qt+1 J K

0 0 0 X

0 1 1 X

1 0 X 1

1 1 x 0

Qt Qt+1 J K

0 0 0 0/1

0 1 1 0/1

1 0 0/1 1

1 1 0/1 0

Excitation Table – Other Flip Flops

25

Qt Qt+1 S R

0 0 0 X

0 1 1 0

1 0 0 1

1 1 x 0

Qt Qt+1 D

0 0 0

0 1 1

1 0 0

1 1 1

Qt Qt+1 T

0 0 0

0 1 1

1 0 1

1 1 0

Example – Counter (Cont.)

26

Qt Qt+1 Q2 Q1 Q0

Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

0 0 0 0 0 1

0 0 1 0 1 0

0 1 0 0 1 1

0 1 1 1 0 0

1 0 0 1 0 1

1 0 1 1 1 0

1 1 0 1 1 1

1 1 1 0 0 0

Example – Counter (Cont.)

27

Qt Qt+1 Q2 Q1 Q0

Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

0 0 0 0 0 1 0 X 0 X 1 X

0 0 1 0 1 0 0 X 1 X X 1

0 1 0 0 1 1 0 X X 0 1 X

0 1 1 1 0 0 1 X X 1 X 1

1 0 0 1 0 1 X 0 0 X 1 X

1 0 1 1 1 0 X 0 1 X X 1

1 1 0 1 1 1 X 0 X 0 1 X

1 1 1 0 0 0 X 1 X 1 X 1

Example – Counter (Cont.)

Now draw K-maps for all 6 inputs

28Source: http://osp.mans.edu.eg/cs212/Seq_circuits_counter-design_ex_1_5.htm

J0 = K0 = 1

J1 = K1 = Q0

J2 = K2 = Q1 * Q0

Example – Counter (Cont.)

29

Source: http://osp.mans.edu.eg/cs212/Seq_circuits_counter-design_ex_1_5.htm

Exercise – Counter

Build a 0 to 7 counter using T Flip Flops. Show

all steps

Your circuit should be similar to following

30

Source: http://osp.mans.edu.eg/cs212/Seq_circuits_counter-design_ex_1_6.htm

Example – Counter With External

Input

Suppose we want to build a 0 to 3 counter that

increments only when a push button is pressed

31

00

1101

10

01

00

11

10

Pressed

Pressed Pressed

Pressed

! Pressed

! Pressed

! Pressed

! Pressed

Example – Counter With External

Input (Cont.)

32

Qt Qt+1 Q1 Q0

Q1 Q0 B Q1 Q2 J1 K1 J0 K0

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 1 0

1 0 1 1 1

1 1 0 1 1

1 1 1 0 0

Example – Counter With External

Input (Cont.)

33

Qt Qt+1 Q1 Q0

Q1 Q0 B Q1 Q0 J1 K1 J0 K0

0 0 0 0 0 0 X 0 X

0 0 1 0 1 0 X 1 X

0 1 0 0 1 0 X X 0

0 1 1 1 0 1 X X 1

1 0 0 1 0 X 0 0 X

1 0 1 1 1 X 0 1 X

1 1 0 1 1 X 0 X 0

1 1 1 0 0 X 1 X 1

J1 = K1 = Q0B

J0 = K0 = B

Example – Counter With External

Input (Cont.)

Another solution

Use a normal 0-3 counter & connect push button to

clock input

34

State Diagrams

State transition diagram for a washing machine

35

Source: http://courses.cs.washington.edu/courses/cse370/96au/assignments/hw8/hw8_soln/hw8_soln.html