sequential circuits - circuits systems - imperial college london

Lecture 4 - 1Introduction to Digital Integrated Circuit DesignSequential Circuits

Lecture 4

Sequential Circuits

Konstantinos MasselosDepartment of Electrical & Electronic Engineering

Imperial College London

URL: http://cas.ee.ic.ac.uk/~kostasE-mail: k.masselos@imperial.ac.uk

Lecture 4 - 2Introduction to Digital Integrated Circuit DesignSequential Circuits

Based on slides/material by…

P. Cheung http://www.ee.ic.ac.uk/pcheung/teaching/ee4_asic/index.html

J. Rabaey http://bwrc.eecs.berkeley.edu/Classes/IcBook/instructors.html“Digital Integrated Circuits: A Design Perspective”, Prentice Hall

D. Harris http://www.cmosvlsi.com/coursematerials.htmlWeste and Harris, “CMOS VLSI Design: A Circuits and Systems Perspective”, Addison Wesley

W. Wolf http://www.princeton.edu/~wolf/modern-vlsi/Overheads.html“Modern VLSI Design: System-on-Chip Design”, Prentice Hall

Lecture 4 - 3Introduction to Digital Integrated Circuit DesignSequential Circuits

Recommended Reading

J. Rabaey et. al. “Digital Integrated Circuits: A Design Perspective”: Chapter 7

Weste and Harris, “CMOS VLSI Design: A Circuits and Systems Perspective”: Chapter 1 (1.4.9), Chapter 7 (7.3.1 – 7.3.5)

Lecture 4 - 4Introduction to Digital Integrated Circuit DesignSequential Circuits

Outline

Bi – Stability / Meta – Stability

Latches

Flip – flops

Schmitt Trigger

Multivibrator circuits

Counters and sequential machines

Lecture 4 - 5Introduction to Digital Integrated Circuit DesignSequential Circuits

Combinational vs. Sequential Logic

Logic

Circuit

Logic

CircuitOut

OutInIn

(a) Combinational (b) Sequential

State

Output = f(In) Output = f(In, Previous In)

Lecture 4 - 6Introduction to Digital Integrated Circuit DesignSequential Circuits

Sequential Logic

FF’s

LOGIC

tp,comb

φ

InOut

2 storage mechanisms• positive feedback• charge-based

Lecture 4 - 7Introduction to Digital Integrated Circuit DesignSequential Circuits

Positive Feedback: Bi-Stability

Vi1

Vo1=Vi2Vo2

Vi1 Vo2

Vo1

Vi2

= V

o1

Vi2

= V

o1

Vi1 = Vo2

A

C

B

Lecture 4 - 8Introduction to Digital Integrated Circuit DesignSequential Circuits

Meta-Stability

Vi2

= V

o1

Vi1 = Vo2

C

Vi2

= V

o1

Vi1 = Vo2

B

δ δ

Gain should be larger than 1 in the transition region

Lecture 4 - 9Introduction to Digital Integrated Circuit DesignSequential Circuits

Outline

Bi – Stability / Meta – Stability

Latches

Flip – flops

Schmitt Trigger

Multivibrator circuits

Counters and sequential machines

Lecture 4 - 10Introduction to Digital Integrated Circuit DesignSequential Circuits

D Latch

When CLK = 1, latch is transparent• D flows through to Q like a buffer

When CLK = 0, the latch is opaque• Q holds its old value independent of D

transparent latch or level-sensitive latch

CLK

D Q

Latc

h D

CLK

Q

Lecture 4 - 11Introduction to Digital Integrated Circuit DesignSequential Circuits

D Latch Design

Multiplexer chooses D or old Q

1

0

D

CLK

QCLK

CLKCLK

CLK

DQ Q

Q

Lecture 4 - 12Introduction to Digital Integrated Circuit DesignSequential Circuits

D Latch Operation

CLK = 1

D Q

Q

CLK = 0

D Q

Q

D

CLK

Q

Lecture 4 - 13Introduction to Digital Integrated Circuit DesignSequential Circuits

Latch Design

Pass Transistor LatchPros+ Tiny+ Low clock load

Cons- Vt drop- nonrestoring- backdriving- output noise sensitivity- dynamic- diffusion input

D Q

φ

Used in 1970’s

Lecture 4 - 14Introduction to Digital Integrated Circuit DesignSequential Circuits

Latch Design

Transmission gate+ No Vt drop- Requires inverted clock

D Q

φ

φ

Lecture 4 - 15Introduction to Digital Integrated Circuit DesignSequential Circuits

Latch Design

Inverting buffer+ Restoring+ No backdriving+ Fixes either

Output noise sensitivityOr diffusion input

- Inverted output

D

φ

φ

X Q

D Q

φ

φ

Lecture 4 - 16Introduction to Digital Integrated Circuit DesignSequential Circuits

Latch Design

Tristate feedback+ Static- Backdriving risk

Static latches are now essential

φ

φ φ

φ

QD X

Lecture 4 - 17Introduction to Digital Integrated Circuit DesignSequential Circuits

Latch Design

Buffered input+ Fixes diffusion input+ Noninverting

φ

φ

QD X

φ

φ

Lecture 4 - 18Introduction to Digital Integrated Circuit DesignSequential Circuits

Latch Design

Buffered output+ No backdriving

Widely used in standard cells+ Very robust (most important)- Rather large- Rather slow- High clock loading

φ

φ

Q

D X

φ

φ

Lecture 4 - 19Introduction to Digital Integrated Circuit DesignSequential Circuits

Latch Design

Datapath latch+ Smaller, faster- unbuffered input

φ

φ φ

φ

Q

D X

Lecture 4 - 20Introduction to Digital Integrated Circuit DesignSequential Circuits

Outline

Bi – Stability / Meta – Stability

Latches

Flip – flops

Schmitt Trigger

Multivibrator circuits

Counters and sequential machines

Lecture 4 - 21Introduction to Digital Integrated Circuit DesignSequential Circuits

D Flip-flop

When CLK rises, D is copied to QAt all other times, Q holds its valuepositive edge-triggered flip-flop, master-slave flip-flop

Flop

CLK

D Q

D

CLK

Q

Lecture 4 - 22Introduction to Digital Integrated Circuit DesignSequential Circuits

D Flip-flop Design

Built from master and slave D latches

QMCLK

CLKCLK

CLK

Q

CLK

CLK

CLK

CLK

D

Latc

h

Latc

h

D QQM

CLK

CLK

Lecture 4 - 23Introduction to Digital Integrated Circuit DesignSequential Circuits

D Flip-flop Operation

CLK = 1

D

CLK = 0

Q

D

QM

QMQ

D

CLK

Q

Lecture 4 - 24Introduction to Digital Integrated Circuit DesignSequential Circuits

Flip-Flop: Timing Definitions

DATASTABLE

DATASTABLE

In

Out

t

t

t

φ

tsetup thold

tpFF

Lecture 4 - 25Introduction to Digital Integrated Circuit DesignSequential Circuits

Maximum Clock Frequency

FF’s

LOGIC

tp,comb

φ

Lecture 4 - 26Introduction to Digital Integrated Circuit DesignSequential Circuits

Flip-Flop Design

Flip-flop is built as pair of back-to-back latches

D Q

φ

φ

φ

φ

X

D

φ

φ

φ

φ

X

Q

Qφ

φ

φ

φ

Lecture 4 - 27Introduction to Digital Integrated Circuit DesignSequential Circuits

Enable

Enable: ignore clock when en = 0• Mux: increase latch D-Q delay• Clock Gating: increase en setup time, skew

D Q

Latc

h

D Q

en

en

φ

φLa

tchD

Q

φ

0

1

en

Latc

h

D Q

φ en

DQ

φ

0

1

enD Q

φ en

Flop

Flop

Flop

Symbol Multiplexer Design Clock Gating Design

Lecture 4 - 28Introduction to Digital Integrated Circuit DesignSequential Circuits

Reset

Force output low when reset assertedSynchronous vs. asynchronous

D

φ

φ

φ

φ

Q

Qφ

φ

φ

φ

reset

D

φ

φφ

φ

φ

φ

Qφ

φ

Dreset

φ

φ

Qφ

φ

Dreset

reset

φ

φ

reset

Synchronous R

esetA

synchronous Reset

Sym

bol FlopD Q

Latc

hD Q

reset reset

φ φ

φ

φ

Q

reset

Lecture 4 - 29Introduction to Digital Integrated Circuit DesignSequential Circuits

Set / Reset

Set forces output high when enabled

Flip-flop with asynchronous set and reset

D

φ

φ

φ

φφ

φ

Q

φ

φ

reset

set reset

set

Lecture 4 - 30Introduction to Digital Integrated Circuit DesignSequential Circuits

SR-Flip Flop

S

R

QS

R Q

S R Q Q

0101

0011

Q100

Q010

S

R

Q

Q

QS

R Q

S R Q Q

1010

1100

Q101

Q011

Q

Q

Lecture 4 - 31Introduction to Digital Integrated Circuit DesignSequential Circuits

JK- Flip Flop

S

R

Q

Q Q

J

K

φ

QJ

K Q

Jn Kn Qn+1

0011

0101

Qn01Qn

(b)

(c)

Q

(a)φ

Lecture 4 - 32Introduction to Digital Integrated Circuit DesignSequential Circuits

Other Flip-Flops

QJ

K Qφ

T

φQJ

K Qφφ

D

Q

Qφ

T Q

Qφ

D

Toggle Flip-Flop Delay Flip-Flop

Lecture 4 - 33Introduction to Digital Integrated Circuit DesignSequential Circuits

Master-Slave Flip-Flop

S

R

Q

Q Q

QS

R

Q

Q

J

K

φ

MASTER SLAVE

QJ

K Qφ

PRESET

CLEAR

SI

RI

Lecture 4 - 34Introduction to Digital Integrated Circuit DesignSequential Circuits

Edge Triggered Flip-Flop

φ

S

R

Q

Q

Q

J

K

Q

QJ

KQ

>φ

Lecture 4 - 35Introduction to Digital Integrated Circuit DesignSequential Circuits

Race Condition

Back-to-back flops can malfunction from clock skew• Second flip-flop fires late• Sees first flip-flop change and captures its result• Called hold-time failure or race condition

CLK1

D Q1

Flop

Flop

CLK2

Q2

CLK1

CLK2

Q1

Q2

Lecture 4 - 36Introduction to Digital Integrated Circuit DesignSequential Circuits

Nonoverlapping Clocks

Nonoverlapping clocks can prevent races• As long as nonoverlap exceeds clock skew

Can be used for safe design• Industry manages skew more carefully instead

φ1

φ1φ1

φ1

φ2

φ2φ2

φ2

φ2

φ1

QMQD

Lecture 4 - 37Introduction to Digital Integrated Circuit DesignSequential Circuits

CMOS Clocked SR- FlipFlop

VDD

Q

Q

RS

φφM1 M3

M4M2

M6

M5 M7

M8

Lecture 4 - 38Introduction to Digital Integrated Circuit DesignSequential Circuits

Flip-Flop: Transistor Sizing

0.0 1.0 2.0 3.0 4.0 5.00.0

2.0

4.0

V Q

(1.8/1.2)(3.6/1.2)(7.2/1.2)

Lecture 4 - 39Introduction to Digital Integrated Circuit DesignSequential Circuits

6 Transistor CMOS SR-Flip Flop

VDD

QQ

φ

M1 M3

M4M2

M5R

φ

S

Lecture 4 - 40Introduction to Digital Integrated Circuit DesignSequential Circuits

Charge-Based Storage

D

D

φ

φ

In

φ

φ

(a) Schematic diagram

(b) Non-overlapping clocks

Pseudo-static Latch

Lecture 4 - 41Introduction to Digital Integrated Circuit DesignSequential Circuits

Master-Slave Flip-Flop

φ

φ

φ

φ D

InA

B

φ

φ

Overlapping Clocks Can Cause• Race Conditions• Undefined Signals

Lecture 4 - 42Introduction to Digital Integrated Circuit DesignSequential Circuits

2 phase non-overlapping clocks

φ2

φ1

φ1

φ2 D

In

φ1

φ2

tφ12

Lecture 4 - 43Introduction to Digital Integrated Circuit DesignSequential Circuits

2-phase dynamic flip-flop

φ2φ1

DIn

Input Sampled

Output Enable

φ1

φ2

Lecture 4 - 44Introduction to Digital Integrated Circuit DesignSequential Circuits

Flip-flop insensitive to clock overlap

DIn

φ

φ φ

φ

VDDVDD

M1

M3

M4

M2 M6

M8

M7

M5

φ−section φ−section

CL1 CL2

X

C2MOS LATCH

Lecture 4 - 45Introduction to Digital Integrated Circuit DesignSequential Circuits

C2MOS avoids Race Conditions

DIn

1

M1

M3

M2 M6

M7

M5

1

DIn

VDDVDD

M1

M4

M2 M6

M8

M5

0 0

VDDVDD

(a) (1-1) overlap (b) (0-0) overlap

X X

Lecture 4 - 46Introduction to Digital Integrated Circuit DesignSequential Circuits

Pipelining

RE

G

φ

REG

φ

REG

φ

log.

RE

G

φ

REG

φ

RE

G

φ

.

RE

G

φ

RE

G

φ

logOut Out

a

b

a

b

Non-pipelined version Pipelined version

Lecture 4 - 47Introduction to Digital Integrated Circuit DesignSequential Circuits

Pipelined Logic using C2MOS

InF Out

φ

φ

VDD

φ

φ

VDD

φ

φ

VDD

C2C1

GC3

NORA CMOS

What are the constraints on F and G?

Lecture 4 - 48Introduction to Digital Integrated Circuit DesignSequential Circuits

NORA CMOS Modules

φ

φ

VDDVDD

PDN

φ

In1In2In3

φ

VDD

PUN

φ

φ

Out

φ

φ

VDD

Out

VDD

PDN

φ

In1In2In3

φ

VDD

In4

In4

VDD

(a) φ-module

(b) φ-module

Combinational logic Latch

Lecture 4 - 49Introduction to Digital Integrated Circuit DesignSequential Circuits

Doubled C2MOS Latches

φ

VDD

Out

φ

VDD

Doubled n-C2MOS latch

Inφ

VDD

Outφ

VDD

Doubled n-C2MOS latch

In

Lecture 4 - 50Introduction to Digital Integrated Circuit DesignSequential Circuits

TSPC - True Single Phase Clock Logic

φ

VDD

Outφ

VDD

φ

VDD

φ

VDD

InStaticLogic

PUN

PDN

Including logic intothe latch

Inserting logic betweenlatches

Lecture 4 - 51Introduction to Digital Integrated Circuit DesignSequential Circuits

Master-Slave Flip-flops

φ

VDD

D

VDD

φ

VDD

D

φ

VDD

φ

VDD

D

VDD

φ

φ

Dφ

VDD

φ

VDD

D

VDD

φ

φD

(a) Positive edge-triggered D flip-flop (b) Negative edge-triggered D flip-flop

(c) Positive edge-triggered D flip-flopusing split-output latches

XY

Lecture 4 - 52Introduction to Digital Integrated Circuit DesignSequential Circuits

Outline

Bi – Stability / Meta – Stability

Latches

Flip – flops

Schmitt Trigger

Multivibrator circuits

Counters and sequential machines

Lecture 4 - 53Introduction to Digital Integrated Circuit DesignSequential Circuits

Schmitt Trigger

In Out

Vin

Vout VOH

VOL

VM– VM+

VTC with hysteresisRestores signal slopes

Lecture 4 - 54Introduction to Digital Integrated Circuit DesignSequential Circuits

Noise Suppression using Schmitt Trigger

VM+

VM–

VoutVin

t tt0 t0 + tp

Lecture 4 - 55Introduction to Digital Integrated Circuit DesignSequential Circuits

CMOS Schmitt Trigger

VDD

Vin Vout

M1

M2

M3

M4

X

Lecture 4 - 56Introduction to Digital Integrated Circuit DesignSequential Circuits

Schmitt Trigger Simulated VTC

0.0 1.0 2.0 3.0 4.0 5.0Vin (V)

0.0

1.0

2.0

3.0

4.0

5.0

VX (V

)

0.0 1.0 2.0 3.0 4.0 5.0Vin (V)

0.0

2.0

4.0

6.0

Vou

t (V

)

VM-

VM+

Lecture 4 - 57Introduction to Digital Integrated Circuit DesignSequential Circuits

CMOS Schmitt Trigger (2)

In

VDD

VDD

Out

M1

M2

M3

M4

M5

M6

X

Lecture 4 - 58Introduction to Digital Integrated Circuit DesignSequential Circuits

Outline

Bi – Stability / Meta – Stability

Latches

Flip – flops

Schmitt Trigger

Multivibrator circuits

Counters and sequential machines

Lecture 4 - 59Introduction to Digital Integrated Circuit DesignSequential Circuits

Multivibrator Circuits

Bistable Multivibrator

Monostable Multivibrator

Astable Multivibrator

flip-flop, Schmitt Trigger

one-shot

oscillator

S

R

T

Lecture 4 - 60Introduction to Digital Integrated Circuit DesignSequential Circuits

Transition-Triggered Monostable

DELAY

td

In

Outtd

Lecture 4 - 61Introduction to Digital Integrated Circuit DesignSequential Circuits

Monostable Trigger (RC-based)

VDD

InOutA B

C

R

In

B

Out t

VM

t2t1

(a) Trigger circuit.

(b) Waveforms.

Lecture 4 - 62Introduction to Digital Integrated Circuit DesignSequential Circuits

Astable Multivibrators (Oscillators)

0 1 2 N-1

0 1 2 3 4 5

t (nsec)

-1.0

1.0

3.0

5.0V

(Vol

t)

V1 V3 V5

Ring Oscillator

simulated response of 5-stage oscillator

Lecture 4 - 63Introduction to Digital Integrated Circuit DesignSequential Circuits

Voltage Controller Oscillator (VCO)

In

VDD

M3

M1

M2

M4

M5

VDD

M6

Vcontr Current starved inverter

Iref Iref

Schmitt Triggerrestores signal slopes

0.5 1.5 2.5Vcontr (V)

0.0

2

4

6

t pH

L (n

sec)

propagation delay as a functionof control voltage

Lecture 4 - 64Introduction to Digital Integrated Circuit DesignSequential Circuits

Relaxation Oscillator

Out2

CR

Out1

Int

I1 I2

T = 2 (log3) RC

Lecture 4 - 65Introduction to Digital Integrated Circuit DesignSequential Circuits

Outline

Bi – Stability / Meta – Stability

Latches

Flip – flops

Schmitt Trigger

Multivibrator circuits

Counters and sequential machines

Lecture 4 - 66Introduction to Digital Integrated Circuit DesignSequential Circuits

One-bit counter implementation

Lecture 4 - 67Introduction to Digital Integrated Circuit DesignSequential Circuits

One-bit counter operation

All operations are performed as sφ2.XOR computes next value of this bit of counter.NAND/inverter compute carry-out.

Lecture 4 - 68Introduction to Digital Integrated Circuit DesignSequential Circuits

n-bit counter structure

Lecture 4 - 69Introduction to Digital Integrated Circuit DesignSequential Circuits

Sequential machines

Use memory elements to make primary output values depend on state + primary inputs.Varieties:• Mealy—outputs function of present state, inputs;• Moore—outputs depend only on state.

Lecture 4 - 70Introduction to Digital Integrated Circuit DesignSequential Circuits

Sequential machine definition

Machine computes next state N, primary outputs O from current state S, primary inputs I.Next-state function:• N = δ(I,S).

Output function (Mealy):• O = λ(I,S).

Lecture 4 - 71Introduction to Digital Integrated Circuit DesignSequential Circuits

FSM structure

Lecture 4 - 72Introduction to Digital Integrated Circuit DesignSequential Circuits

Summary

Bi-stable sequential circuits • Latches (level sensitive circuits)• Flip – flops (edge triggered circuits)

Non bi-stable sequential circuits• Schmitt Trigger (responds fast to a slowly changing input)• Multivibrator circuits

Monostable (only one stable state – generates pulse of predetermined width)Astable (no stable states – output oscillates between two quasi stable states)