semiconductor manufacturing...

Yau - 1SMT

DepositionDeposition

Yau - 2SMT

Objectives

After studying the material in this chapter, you will be able to:

1. Describe multilayer metallization. Discuss the acceptable characteristics of a thin film. State and explain the three stages of film growth.

2. Provide an overview of the different film deposition techniques.3. List and discuss the 8 basic steps to a chemical vapor deposition

(CVD) reaction, including the different types of chemical reactions.4. Describe how CVD reactions are limited, reaction dynamics and the

effect of dopant addition to CVD films.5. Describe the different types of CVD deposition systems, how the

equipment functions and the benefits/limitations of a particular tool for film applications.

6. Explain the importance of dielectric materials for chip technology, with applications.

7. Discuss epitaxy and three different epi-layer deposition methods8. Explain spin on dielectrics.

Yau - 3SMT

Film Layers for an MSI Era NMOS Transistor

p+ silicon substrate

p- epi layer

Field oxiden+ n+ p+ p+

n-well

ILD OxidePad

Oxide

NitrideTopside

Gate oxideSidewall oxide

Pre-metal oxide

Poly

Metal

Poly Metal

Figure 11.1

Yau - 4SMT

Process Flow in a Wafer Fab

Test/Sort Implant

Diffusion Etch

Polish

PhotoCompleted wafer

Locations where thin films are deposited

Unpatterned wafer

Wafer startThin Films

Wafer fabrication (front-end)

Used with permission of Advanced Micro Devices

Figure 11.2

Yau - 5SMT

Introduction

• Film Layering in Wafer Fab– Diffusion– Thin Films

• Film Layering Terminology• Multilayer Metallization

– Metal Layers– Dielectric Layers

Yau - 6SMT

Multilevel Metallization on a ULSI Wafer

Figure 11.3

Passivation layer Bonding pad metal

p+ Silicon substrate

Via

ILD-2

ILD-3

ILD-4

ILD-5

M-1

M-2

M-3

M-4

p- Epitaxial layer

p+p+

ILD-6

LI oxide

STI

n-well p-well

ILD-1

Poly gate

n+ p+p+ p+p+ n+n+

LI metal

Yau - 7SMT

Metal Layers in a Chip

Micrograph courtesy of Integrated Circuit Engineering

Photo 11.1

Yau - 8SMT

Film Deposition

Thin Film Characteristics• Good step coverage

• Ability to fill high aspect ratio gaps (conformality)

• Good thickness uniformity

• High purity and density

• Controlled stoichiometries

• High degree of structural perfection with low film stress

• Good electrical properties

• Excellent adhesion to the substrate material and subsequent films

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Solid Thin Film

Silicon substrate

Oxide

WidthLen

gth

Thickness

Thin films are very thin in comparison to the substrate.

Figure 11.4

Yau - 10SMT

Film Coverage over Steps

Conformal step coverage Nonconformal step coverage

Uniform thickness

Figure 11.5

Yau - 11SMT

Aspect Ratio for Film Deposition

Aspect Ratio = Depth Width

=2 1

Aspect Ratio = 500 Å250 Å

500 Å

D

250 ÅW

Figure 11.6

Yau - 12SMT

High Aspect Ratio Gap

Photograph courtesy of Integrated Circuit Engineering

Photo 11.2

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Stages of Film Growth

Continuous film

Gas molecules

Nucleation Coalescence

Substrate

Figure 11.7

Yau - 14SMT

Techniques of Film Deposition13

Chemical Processes Physical Processes

Chemical VaporDeposition (CVD) Plating

Physical VaporDeposition

(PVD orSputtering)

Evaporation Spin OnMethods

Atmospheric PressureCVD (APCVD) or

Sub-Atmospheric CVD(SACVD)

Electrochemicaldeposition (ECD),

commonly referred toas electroplating

DC Diode Filament andElectron Beam

Spin onglass (SOG)

Low Pressure CVD(LPCVD) Electroless Plating Radio Frequency

(RF)Molecular BeamEpitaxy (MBE)

Spin ondielectric

(SOD)Plasma Assisted CVD: Plasma Enhanced

CVD (PECVD) High Density

Plasma CVD(HDPCVD)

DC Magnetron

Vapor Phase Epitaxy(VPE) and

Metal-organic CVD(MOCVD)

Ionized metalplasma (IMP)

Dielectrics: Chapter 11Metals: Chapter 12 Chapter 12 Chapter 12 Chapter 12 Chapter 11

Table 11.1

Yau - 15SMT

Chemical Vapor Deposition

The Essential Aspects of CVD1. Chemical action is involved, either through chemical

reaction or by thermal decomposition (referred to as pyrolysis).

2. All material for the thin film is supplied by an external source.

3. The reactants in a CVD process must start out in the vapor phase (as a gas).

Yau - 16SMT

Chemical Vapor Deposition Tool

Photograph courtesy of Novellus, Sequel CVD

Photo 11.3

Yau - 17SMT

CVD Chemical Processes

1. Pyrolosis: a compound dissociates (breaks bonds, or decomposes) with the application of heat, usually without oxygen.

2. Photolysis: a compound dissociates with the application of radiant energy that breaks bonds.

3. Reduction: a chemical reaction occurs by reacting a molecule with hydrogen.

4. Oxidation: a chemical reaction of an atom or molecule with oxygen.

5. Reduction-oxidation (redox): a combination of reactions 3 and 4 with the formation of two new compounds.

Yau - 18SMT

CVD Reaction

• CVD Reaction Steps• Rate Limiting Step• CVD Gas Flow Dynamics• Pressure in CVD• Doping During CVD

– PSG– BSG– FSG

Yau - 19SMT

Schematic of CVD Transport and Reaction Steps

CVD Reactor

Substrate

Continuous film

8) By-product removal

1) Mass transport of reactants

By-products2) Film precursor

reactions

3) Diffusion of gas molecules

4) Adsorption of precursors

5) Precursor diffusion into substrate 6) Surface reactions

7) Desorption of byproducts

Exhaust

Gas delivery

Figure 11.8

Yau - 20SMT

Gas Flow in CVD

Gas flow

Deposited film

Silicon substrate

Reaction product

Diffusion of reactants

Figure 11.9

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Gas Flow Dynamics at the Wafer Surface

Gas flow

Boundary layer

Gas flow

Stagnant layer

Figure 11.10

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CVD Deposition Systems

• CVD Equipment Design– CVD reactor heating– CVD reactor configuration– CVD reactor summary

• Atmospheric Pressure CVD, APCVD • Low Pressure CVD, LPCVD• Plasma-Assisted CVD• Plasma-Enhanced CVD, PECVD• High-Density Plasma CVD, HDPCVD

Yau - 23SMT

CVD Reactor Types

CVD Reactor Types Atmospheric Low-pressure Batch Single-waferHot-wall √ √ √Cold-wall √ √ √ √Continuous motion √ √Epitaxial √ √Plenum √ √Nozzle √ √Barrel √ √Cold-wall planar √ √ √Plasma-assisted √ √ √Vertical-flow Isothermal √ √ √

Figure 11.11

Yau - 24SMT

Types of CVD Reactors and Principal Characteristics

Process Advantages Disadvantages Applications

CVDAtmospheric Pressure

D)

Simple reactor, fastdeposition, lowtemperature.

Poor step coverage,particle contamination,and low throughput.

Low-temperature oxides(both doped and undoped).

PCVDLow Pressure CVD)

Excellent purity anduniformity, conformalstep coverage, large wafercapacity.

High temperature, lowdeposition rate, moremaintenance intensiveand requires vacuumsystem.

High-temperature oxides(both doped and undoped),silicon nitride, polysiliconW, WSi2.

lasma Assisted CVD: Plasma Enhanced

CVD (PECVD) High Density Plasma

CVD (HDPCVD)

Low temperature, fastdeposition, good stepcoverage, good gap fill.

Requires RF system,higher cost, stress ismuch higher with atensile component, andchemical (e.g., H2) andparticle contamination.

High aspect ratio gap fill,low-temperature oxides ovmetals, ILD-1, ILD, coppeseed layer for dualdamascene, passivation(nitride).

AP(CV

L( ,

Perr

Table 11.2

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Continuous-Processing APCVD Reactors

WaferFilmReactant gas 2

Reactant gas 1

Inert separator gas

(a) Gas-injection type

N2

Reactant gases

Heater

N2 N2 N2N2 N2

Wafer

(b) Plenum typeFigure 11.12

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Excellent Step Coverage of APCVD TEOS-O3

Liner oxide

p Silicon substrate

p Epitaxial layer

n-well p-well

Trench CVD oxide

TEOS-O3

Trench fill by chemical vapor deposition

Nitride

-

+

Figure 11.3

Yau - 27SMT

Planarized Surface after Reflow of PSG

After reflow

PSG

Before reflow

PSG

Metal or polysilicon

Figure 11.14

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Boundary Layer at Wafer Surface

Continuous gas flow

Deposited film

Silicon substrate

Boundary layer

Diffusion of reactants

Figure 11.15

Yau - 29SMT

LPCVD Reaction Chamber for Deposition of Oxides, Nitrides, or Polysilicon

Three-zone heating element

Spike thermocouples (external, control)

Pressure gauge

Exhaust tovacuum pump

Gas inletProfile thermocouples

(internal)

Figure 11.16

Yau - 30SMT

Oxide Deposition with TEOS LPCVD

Pressure controllerThree-

zone heater

Heater TEOSN2 O2 Vacuum

pump

Gas flow controller

LPCVDFurnace

Temp. controller

Computer terminal operator interface

Furnace microcontroller

Exhaust

Figure 11.17

Yau - 31SMT

Key Reasons for the Use of DopedPolysilicon in the Gate Structure

1. Ability to be doped to a specific resistivity.2. Excellent interface characteristics with silicon dioxide.3. Compatibility with subsequent high temperature

processing.4. Higher reliability than possible metal electrodes (e.g.,

aluminum)5. Ability to be deposited conformally over steep

topography.6. Allows for self-aligned gate process (see Chapter 12).

Yau - 32SMT

Doped Polysilicon as a Gate electrode

n-well p-well

p- Epitaxial layer

p+ Silicon substrate

Polysilicon gate

p+ p+ p+n+n+n+

Figure 11.18

Yau - 33SMT

Advantages of Plasma Assisted CVD

1. Lower processing temperature (250 – 450°C).

2. Excellent gap-fill for high aspect ratio gaps (with high-density plasma).

3. Good film adhesion to the wafer.

4. High deposition rates.

5. High film density due to low pinholes and voids.

6. Low film stress due to lower processing temperature.

Yau - 34SMT

Film Formation during Plasma-Based CVD

PECVD reactor

Continuous film

8) By-product removal

1) Reactants enter chamber

Substrate

2) Dissociation of reactants by electric fields

3) Film precursors are formed

4) Adsorption of precursors

5) Precursor diffusion into substrate 6) Surface reactions

7) Desorption of by-products

Exhaust

Gas delivery

RF generator

By-products

Electrode

Electrode

RF field

Figure 11.19

Yau - 35SMT

General Schematic of PECVD for Deposition of Oxides, Nitrides, Silicon Oxynitride or Tungsten

Process gases

Gas flow controller

Pressure controller

Roughingpump

Turbopump

Gas panel

RF generatorMatching network

Microcontroller operator Interface

Exhaust

Gas dispersion screen

Electrodes

Figure 11.20

Yau - 36SMT

Properties of Silicon Nitride for LPCVD Versus PECVD

Property LPCVD PECVD

Deposition temperature (°C) 700 – 800 300 – 400

Composition Si3N4 SixNyHz

Step coverage Fair Conformal

Stress at 23°C on silicon(dyn/cm-2)

1.2 – 1.8 x 1010

(tensile)1 – 8 x 109

(tensile or compressive)

Table 11.3

Yau - 37SMT

High Density Plasma Deposition Chamber• Popular in mid-1990s• High density plasma• Highly directional due to

wafer bias• Fills high aspect ratio

gaps• Backside He cooling to

relieve high thermal load• Simultaneously deposits

and etches film to prevent bread-loaf and key-hole effects

Photograph courtesy of Applied Materials, Ultima HDPCVD Centura

Photo 11.4

Yau - 38SMT

Dep-Etch-Dep Process

Film deposited with PECVD creates pinch-off at the entrance to a gap resulting in a void in the gap fill.

Key-hole defect

Bread-loaf effect

Metal

SiO2

The solution begins here

1) Ion-induced deposition of film precursors

2) Argon ions sputter-etch excess film at gap entrance resulting in a beveled appearance in the film.

3) Etched material is redeposited. The process is repeated resulting in an equal “bottom-up” profile.

Cap

Figure 11.21

Yau - 39SMT

Five Steps of HDPCVD Process

1. Ion-induced deposition

2. Sputter etch

3. Redeposition

4. Hot neutral CVD

5. Reflection

Yau - 40SMT

HDPCVD with Wafer at Throat of Turbo Pump

To roughing pump

Microwave 2.45 GHz

Electromagnet

Turbopump

Gate valve

Gas shower head

Wafer on electrostatic chuck

Figure 11.22

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Dielectrics and Performance

• Dielectric Constant• Gap Fill• Chip Performance• Low-k Dielectric• High-k Dielectric• Device Isolation

– LOCOS– STI

Yau - 42SMT

3-Part Process for Dielectric Gap Fill

2) PECVD cap

Cap

1) HDPCVD gap fill

SiO2

Aluminum

3) Chemical mechanical planarization

Figure 11.23

Yau - 43SMT

Potential Low-k Materials for ILD of ULSI Interconnects

Potential low-kDielectric

DielectricConstant

(k)

Gap Fill(µm)

CureTemp.(°C)

Remarks

FSG (siliconoxyfluoride, SiXOFy)

3.4 – 4.1 <0.35 No issueFSG has almost the same k-value as SiO2 andreliability concern that fluorine will attack andcorrode tantalum barrier metal.

HSQ (hydrogensilsesquioxane) 2.9 <0.10 350 – 450

Silicon-based resin polymer available insolution as Fox (Flowable Oxide) for spin-oncoating application. May require surfacepassivation to reduce moisture absorption.Cure is done in nitrogen.

Nanoporous silica 1.3 – 2.5 <0.25 400

Inorganic material with tunable dielectricconstant that relies on pore density. Increasedporosity reduces mechanical integrity –porous material must withstand polishing,etching and heat treatments withoutdegradation.

Poly(arylene) ether(PAE) 2.6 – 2.8 <0.15 375 – 425 Spin-on aromatic polymer with excellent

adhesion and ability to be polished with CMP.

a-CF (fluorinatedamorphous carbon orFLAC)1

2.8 <0.18 250 – 350

Leading candidate for CVD deposition withhigh density plasma CVD (HDPCVD) toproduce film with good thermal stability andadhesion.

Parylene AF4 (aliphatictetrafluorinated poly-p-xylylene)

2.5 <0.18 420 – 450

CVD film that meets adhesion and viaresistance requirements with need to maintaingas delivery system at 200°C to controlparylene precursor flow rate.

1 P. Singer, Technology News: Wafer Processing, Semiconductor International, October, 1998, p. 44.

Table 11.4

Yau - 44SMT

Interconnect Delay (RC) vs. Feature Size (µm)2.5

2.0

1.5

1.0

0.5

00 .5 1.0 1.5 2.0

Feature size (µm)

Del

ay ti

me

(’10-9

sec)

Interconnect delay (RC)

Gate delay

Figure 11.24

Yau - 45SMT

Total Interconnect Wiring Capacitance

Cap

acita

nce

(10-1

2Fa

rads

/cm

)

7

6

5

4

3

2

1

00 0.5 1.0 1.5 2.0 2.5 3.0

Space (µm)

K = 4

K = 3

K = 2

K= 1

Redrawn with permission from Semiconductor International, September 1998

Figure 11.25

Yau - 46SMT

Low-k Dielectric Film Requirements

Electrical Mechanical Thermal Chemical Processing Metallization

Low dielectricconstant Good adhesion Thermal

stabilityResistant: acids

and bases Patternability Low contactresistance

Low dielectricloss Low shrinkage

Low coefficientof thermalexpansion

Etch selectivity Good gap fillLow

electromigration(corrosion)

Low leakage Crack resistant Highconductivity Low impurities Planarization Low stress

voiding

High reliability Low stress No corrosion Low pin hole Hillock (smoothsurface)

Good hardness Low moistureuptake Low particulate

Compatible withbarrier metals (Ta,

TaN, TiN, etc.)

Storage life

Table 11.5

Yau - 47SMT

General Diagram of DRAM Stacked Capacitors

SiO2 dielectric

Doped polysiliconcapacitor plate

Doped polysiliconcapacitor plate

Buried contactdiffusion

SiO2 dielectric Doped polysiliconcapacitor plate

Doped polysiliconcapacitor plate

Buried contactdiffusion

Figure 11.26

Yau - 48SMT

Shallow Trench Isolation

Photograph courtesy of Integrated Circuit Engineering

Photo 11.5

Yau - 49SMT

Spin-on Dielectrics

• Spin-on Glass (SOG)• Spin-on Dielectric (SOD)• Epitaxy

– Epitaxy growth methods• Vapor-phase epitaxy• Metalorganic CVD• Molecular-beam epitaxy

• Quality Measures• CVD Troubleshooting

Yau - 50SMT

2) SOG after curing1) Initial SOG gap fill 3) CVD oxide cap

Cap

Gap-Fill with Spin-On-Glass (SOG)

Figure 11.27

Yau - 51SMT

Proposed HSQ Low-k Dielectric Processing Parameters

Major Operation Process Step Parameter

Apply bowl speed 50 rpm

Maximum bowl speed 800 – 1500 rpm

Backside rinse 800 rpm, 5 sec

Topside edge bead removal 1000 rpm, 10 sec

Spin coating

Spin Dry 1000 rpm, 5 sec

Initial soft-bake cure 200°C, 60 sec, N2 purgeCure

In-line cure 475°C, 60 sec, N2 ambient

Table 11.6

Yau - 52SMT

Epitaxy

• Epitaxy Growth Model• Epitaxy Growth Methods

– Vapor-Phase Epitaxy (VPE)– Metalorganic CVD (MOCVD)– Molecular-Beam Epitaxy (MBE)

Yau - 53SMT

Silicon Epitaxial Growth on a Silicon Wafer

Si

Si

ClCl

HH

Si

Si

Si Si

Si Si

Si

Si

Si

Si

Si

ClH

Cl

H

Chemical reaction

By-products

Deposited siliconEpitaxial layer

Single silicon substrate

Figure 11.28

Yau - 54SMT

Illustration of Vapor Phase Epitaxy

Dopant (AsH3 or B2 H3)

H2

SiH2 Cl2

RF induction-heating coils

Susceptor

WafersVacuum puimp

Figure 11.29

Yau - 55SMT

Silicon Vapor Phase Epitaxy Reactors

ExhaustExhaust

Exhaust

RF heating

RF heating

Gas inletGas inlet

Horizontal reactor Barrel reactorVertical reactor

Figure 11.30

Yau - 56SMT

Effects of Keyholes in ILD on Metal Step Coverage

b) SiO2 is planarized

c) Next layer of aluminum is deposited

Metal void caused by keyhole defect in SiO2

a) SiO2 deposited by PECVDSiO2

Keyhole defect in interlayer dielectric

Aluminum

Figure 11.31