self-timed logic timing complexity growing in digital design -wiring delays can dominate timing...

Self-Timed Logic

• Timing complexity growing in digital design

- Wiring delays can dominate timing analysis (increasing interdependence between logical and physical views of system)

- Low-skew clock distribution consumes power and space

• Self-Timed Systems – systems that operate without clocks at speeds determined by their own internal parameters (also know as Delay-Insensitive Systems)

- requires completion signal feedback to the input source

Simple Handshake Example

SubsystemP2

SubsystemP1

Data

Request (R)

Acknowledge (A)

Four-Phase Handshake

Two-Phase Handshake

Request (R)

Acknowledge (A)

Request (R)

Acknowledge (A)

P1 says “send data” P1 says “send data”

P2 says “data available” P2 says “data available”

P1 says “send data”

P2 says “data available”

Return to 0

Return to 0

How to Apply to Clocked Systems?

Phased Logic Concepts

• Completion signal not restricted to simple handshake between two subsystems (rather a system with multiple feedback circuits)

• Conventional clocked systems can be replaced with networks of fine grain Phased Logic Gate Primitives that carry both time and value information simultaneously

• Clock (t) and Value (v)

- Encoding scheme used is Level-Encoded two-phase Dual-Rail (LEDR) scheme.

- Four-phase encoding avoided – no resetting transition that consumes power

LEDR Encoding

Phased Logic AND GateGate fires when phase of inputs match phase of gate

Normal output has opposite phase of gate

Arcs A & B: gate cannot “fire” until inputs reach proper phase

Arcs C & D: changes cannot occur until after gate has fired

Phase Logic Gate Timing with Multiple Outputs

Arc A: inputs can change as soon as any output changes phase

Arc B: environment of the gate must guarantee that all outputs have changed before gate is reenabled

Phased Logic GateNormal Firing Rules

1) Internal Constraint: the gate fires IFF it is enabled (all inputs match phase of gate). A requirement of the gate design.

2) External Constraint: The phase of each input and output toggles once between the nth and (n+1)th firing of the gate. A requirement on the system design.

Correspondence Between Phases and Tokens

Example of Token Movement

Initial Token Markings

Live and Safe Initial Token Marking

Phase inversion used to allow live and safe initial token making - output phase the same as the phase of the gate

Liveness and Safety Theorems

THEOREM 1. A marked graph is live IFF the initial token marking places at least one token on each directed circuit.

THEOREM 2. A live marked graph is safe IFF every edge belongs to some directed circuit with a token count of one in the initial token marking. Such a circuit is called a synchronizing loop.

Edges violate THM 2

C1 has no token

& violate THM 1

Self-Timed Arithmetic Speed-Up

• Normal phased logic circuits operate without worst-case timing margins

• Normal phased logic circuits average loop cycle times of differing lengths (ex. Two-stage pipeline of 40 and 20 delay units operates with 30 delay units on average)

• Eager (Early) Evaluation of phase logic circuits can allow generates and kills in arithmetic circuits to propagate sooner.

See handout “Phased Logic with Eager Evaluation”