samsung plasma training manual
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PDP Training (Alexander)
1.Explanation of Layout and
Function of Circuit Board
2.Operation Explanation per Board2-1 Drive Description on SMPS
2-2 Operation Explanation of Driving
Circuit
2-3 Logic-Main Board
2-4 Scaler Board
Agenda
1. Explanation of Layout & Function of Circuit Board1. Explanation of Layout & Function of Circuit Board
COF x 7
Y- MAIN
SMPSX- MAIN
Logic- Main
Y buffer "Upper"
Y buffer
"Lower"
E- buffer F- buffer G- buffer
[PDP Module Picture]
[ Function Description by board - 1 ]
■.SMPS(Switching Mode Power Supply)
: It is the supplier to provide voltage and current to work the drive voltage and panel in each board.
■.X-MAIN BOARD
: It makes the drive wave form by switching FETs to Timing Controlle coming from logic-board and
supplies X electrode of panel with the drive wave form via connector.
■.Y-MAIN BOARD
: It makes the drive wave form by switching FETs to Timing Controller coming from the logic-board and
provides Y electrode of panel with the drive wave form via Scan Driver IC on Y buffer board in order.
■.LOGIC MAIN BOARD
: It process image signal and performs buffering of the logic-main board (to create XY drive signal and
output) and the address driver output signal.
Then it supplies the output signal to the address driver IC(COF Module).
[ Function Description by board - 2 ]■.LOGIC BUFFER(E,F,G) : It delivers the data signal and control signal to the COF.
■.Y-BUFFER (Upper,Lower)
: It is the board to impress the scan waveform on the Y board and consist of 2 boards
(upper board and lower board).
8 Y-buffers are fixed at the scan driver (STV7617 of STC corp. : 64 or 65 Output).
■.AC Noise Filter
: It has functions to remove noise(low frequency) coming from AC LINE and prevent surge.
It gives serious effects on the safety regulations (EMC, EMI) according to AC filter.
■.COF(Chip on Flexible)
: It impress the Va pulse to the address electrode in the address section and forms the address
discharge by electric potential difference with scanning pulse to be dismissed by the Y electrode.
It is made in the form of COF and one COF consists of 4 Data Drive IC (STV7610A :96 Output),
otherwise single scan is made of 7 COF.
CELL STRUCTURE OF PDP
Bus electrode
Dielectric
ITO electrodeMgO layer
Barrier Phosphors
AddressElectrode
Front panel
Back panel
Electro Arrangement of SD PDP
Y1
Y2
Y480
X
X
X
∼
∼
∫
A1 A2 A3 A4 A5 A6 A7
Reference- A1,A2, , , : Address Electrode- Y1,Y2, , , : Scan & Sustain Electrode- X : Common & Sustain Electrode
ADDRESS OPERATION
In order to display picture,
select the cells.
In order to display picture,
select the cells.
SUSTAIN OPERATION
Display cells through strong
Sustain discharge.
Display cells through strong
Sustain discharge.
1 SUB-FIELD IMAGE PROCESS (ADS)
ResetReset AddressAddress SustainSustain
Function• Sustain Erase• Wall Charge Set
Issue• Operation margin• Contrast• Short Time
Function• Sustain Erase• Wall Charge Set
Issue• Operation margin• Contrast• Short Time
Function• Select On Cell
Issue• High Speed• Low Voltage• Low Failure
Function• Select On Cell
Issue• High Speed• Low Voltage• Low Failure
Function• Discharge On Cell
Issue• High Efficiency• Low Voltage• ERC Performance
Function• Discharge On Cell
Issue• High Efficiency• Low Voltage• ERC Performance
FRAME STRUCTURE (ADS)
SF1 SF2 SF3 SF4 SF5 SF6 SF7 SF8
1
.....2
480
128T64T32T16T8T4T2T1T
1TV field (time)scan
line
address
sustain
sub-field
ResetPeriod
AddressPeriod
SustainPeriod
X
Y1
Y2
Yn
D
1 Picture Structure by 8 sub-field
SF1 SF2 SF3 SF4 SF5 SF6 SF7 SF8Orig
inal Image
1
.....2
480
128T64T32T16T8T4T2T1T
1TV field (time)scan
line
address
sustain
sub-field
2. Explanation of Operation per Boards2. Explanation of Operation per Boards
PDP Panel
852 X 480 Pixels
853 X 3 X 480 Cells
Logic B'd Display
Data
Driver
Timing
Scan
Timing
Input
Data
Processor
Clock :
27MHz
Data
Controller
Clock :
60MHz
DRAM
Driver
Timing
Controller
Clock :
20MHz
40MHz
Y- Main B'd
Row
Driver
Y- Pulse
Generator
X- Main B'd
X- Pulse
Generator
Column Driver
Power B'd
Power Supply
Digital B'd Analog B'dLVDS
AC PowerSource220V
ImageEnhancer
ImageScalerr
ADConverterr
TMDSReceiverr
VideoDecoder
De-interlacer
Micom
Tuner
AudioProcessor
VideoS/W
CombFilter
[Whole Block Diagram]
1 Picture Structure by 8 sub-field
CN805(10P)
CN805(10P)
CN806)CN812(5P)
CN804(9P)
CN804(9P)
CN802(11P)
CN801(10P)
CN803(10P)
CN803(10P)
CN806)
LA03(31P)
CN201CN201 CN101CN101
CN801CN802CN601CN111 CN101
CN102
CN103
CN401 CN402 CN403
EF1 FE1 FG1 GF1
AC
Inlet
AnalogDigital
Y- MainX- Main
SMPS
Logic
[Wiring Diagram Schematic]
PIN CONFIGURATION
CN101(Control)
NO PIN Name
1 GND
2 SCL1
3 SDA1
4 GND
5 SAFT
6 GND
7 MUTE
8 GND
9 MAFT
10 GND
11 ANAL_CVBS
12 GND
CN102(Video/Sync)
NO PIN Name
1 ANAL_YCOMB
2 GND
3 ANAL_CCOMB
4 GND
5 ANAL_Y2
6 GND
7 ANAL_PB2
8 GND
9 ANAL_PR2
10 GND
11 ANAL_H
12 ANAL_V
CN103(Video/Sync)
NO PIN Name
1 ANAL_YCOMB
2 GND
3 ANAL_CCOMB
4 GND
5 ANAL_Y2
6 GND
7 ANAL_PB2
8 GND
9 ANAL_PR2
10 GND
11 ANAL_H
12 ANAL_V
NO PIN Name NO PIN Name
1 GND 16 Tx CLK Out+ / Rx CLK In+
2 GND 17 GND
3 Tx Out0- / Rx In0- 18 GND
4 Tx Out0+ / Rx In0+ 19 Tx Out0- / Rx In0-
5 GND 20 Tx Out0- / Rx In0-
6 GND 21 GND
7 Tx Out1- / Rx In1- 22 GND
8 Tx Out1+ / Rx In1+ 23 GND
9 GND 24 GND
10 GND 25 RESET_MN
11 Tx Out2- / Rx In2- 26 GND
12 Tx Out2+ / Rx In2+ 27 IIC SCL2
13 GND 28 GND
14 GND 29 IIC SDA2
15 Tx CLK Out- / Rx CLK In- 30 GND
31 GND
[ Scaler : Analog ↔ Dgital ] [ Scaler Dgital ↔ Logic (CN601) ]
PIN CONFIGURATION
CN802(Digital Tu)
NO Power
1 THEM_D
2 STD_5V
3 GND
4 PS_ON
5 N.C.
6 GND
7 GND
8 D3.3V
9 D3.3V
10 GND
11 D6V
CN801(Analog Tu)
NO Power
1 GND
2 A33V
3 GND
4 GND
5 AMP12V
6 AMP12V
7 GND
8 D12V
9 GND
10 D6V
CN803(Logic)
NO Power
1 D3.3V
2 D3.3V
3 GND
4 GND
5 D5V
6 GND
7 IC2
8 IC2
9 PS_ON
10 GND
CN804(X- Main)
NO Power
1 D5V
2 VG
3 GND
4 GND
5 VE
6 GND
7 GND
8 VS
9 VS
CN805(Y- Main)
NO Power
1 D5V
2 VG
3 GND
4 Vscan
5 GND
6 Vset
7 GND
8 GND
9 VS
10 VS
CN806/812(Buffer)
NO Power
1 Va
2 Va
3 N.C.
4 GND
5 GND
[ SMPS ↔ Analog/ Digital / Logic ] [ SMPS ↔ X,Y- Main/ Buffer ]
CN807/811(FAN)
NO Power
1 12V
2 GND
5 Fan_D
[FAN B+:For VMB]
2-1. Drive Description on SMPS2-1. Drive Description on SMPS
Vscan (+78V)
[SMPS Block Diagram]
EMI
FILTER
Boost PFC
Stage
Auxiliary
Stage
Vs_Switching
Stage
PWM control
Stage
Va_Switching
Stage
V_digital
V_analog
Switching Stage
AC input
90V∼264V
Reg.
Vs(+85V)
Return
Va(+79V)
D3.3V (+3.3V)
Vg (+15V)
12V(+12V 0.7A)
A6V(+6V)
VT (+33V 0.03A)
385Vdc bus
A12V(+12V)
12V Amp(+12v)
MAG- AMP
NOISEFILTER
Stand_By 5V
Vcc
HOT COLD
DC/DCConverter
DC/DCConverter
DC/DCConverter
Vset (+95V)
Ve (+110V)
HOTCOLD COLD
D5V (+5V))
Return
D6V(+6V)
PS- ON/Relay Signal
Vs Logic_ON
Active_High
Return
PWM control
Stage
Chopper REG
PWM control
Stage
Operation Description on SMPS
1. Overview
SMPS used in PDP 42" developed into the compact-sized with high efficiency.
The asymmetrical half bridge and the flyback converter are applied into all output. To comply with the
harmonic restrictions, it takes the power factor improvementcircuit, which converts AC into the high DC
and uses as the input of another converter controller.
2. Input controller
SMPS works in whole section of AC 90~264V. It is possible to start in the AC 90 and can restart with new
input voltage, even in interruption of electric power. STD_5V comes out when AC is impressed
3. Output Controller
Given SMPS have 15 output voltages. The following shows the specification of output voltage and output
current in case of their successive drive.
Operation Description on SMPS
Name Voltage Current(Max.) Using in PDP Driving
VS +75V ~ 100V 4.5A Sustain Voltage
VA +65V ~ 80V 0.6A Address Voltage
VSCAN +65V ~ 100V 0.1A
VSET +80V ~ 100V 0.1A
VE +100V ~ 120V 0.1A
VG +15V 1.5A Driving Voltage of Fet
D12V +12V 0.1A
Name Voltage Current(Max.) Using in PDP Driving
A12V +12V 0.3A
D6V +6V 0.1A
A6V +6V 0.1A
D5V +5V 1.0A IC Driving Voltage of Logic
D3.3V +3.3V 4.5A
12VAMP +12V 1.7A Amp Voltage of Audio
VT +33V 0.003A
STD_5V +5V 0.6AStandby for Remote
Control
3-1. Overvoltage protection
It has circuit to maintain normal voltage, additionally with circuit for sensing overvoltage, so it means any
overvoltage does not give impacts on other output controller. SMPS prevents overvoltage in the latch mode.
VS(85V) works protection function more than 100V, over 94V for VA(75V), over 8.2V for D6V,
over 4.7V for D3.3V
Operation Description on SMPS 3-2. Short circuit and overvoltage protection
It forms definition that in the short circuit of output controller the output impedance is lower than 300mohm.
If the VS output have a short circuit in case of given SMPS, SMPS stops its working.
Even in the case of short circuit between main output and STD_5V, SMPS does not break down.
When the short circuit is removed, it restarts.
4. Detail Description
① AC-DC Converter
It converts AC into DC by using the power factor improvementcircuit. This converter was designated to
control the high frequency noise, with the function to improve the power factor. This part becomes input
controller of another constant-voltage.
[ PFC Drive FET (SPW47N60) Drain Pulse ][ PFC Drive FET (SPW47N60) Gate Pulse ]
Operation Description on SMPS ② Auxiliary Power
It is the part to supply power of mycom for remote control. When the power is on, it will work,
which means that MICOM is on standby.
This output part is stand_by voltage. When the power-on signal from remote control impress,
it works main power panel of SMPS via stand_by voltage.
③ Configuration of VS output
Major part of PDF SMPS outputs 85V 5A. It takes asymmetrical half bridge converter and connects
2 converters with 85V output in parallel, which increases efficiency than one 85V converter,
on the other hand, decreases its size.
[ Driving FET(2SK2372) Drain Pulse&Current wave. ] [ Driving FET(2SK2372) Gate Pulse ]
Operation Description on SMPS
- PWM Part
It uses PWM part of ML4824, but there are some points to take cautions. As this part is synchronized with
the PFC part, PWM wave in the current mode drive is induced via the current sensor resistance or current
transformer, and shows the current flowing in the output controller.
④ DC-DC Converter : Input of VSCAN, VSET and VE belongs to the VS part
[ VSET Pulse ] [ VE Pulse ] [ Vscan Pulse ]
Operation Description on SMPS
⑤ Output (VA,Multi Outputs) Pulse
[ Va Main Pulse ] [ Multi Outputs Main Pulse ]
Trouble shooting on SMPS
STB_5V
Power ON
Check cord connection
PFC
PFC
PFC
NGCheck the IC2,D28
Check the IC1,Q1,Q2
OK
OK
OK OK
NG
NG
Check the IC35
Check the IC7
Trouble shooting on SMPS
VS
VscanVE,Vset
NGCheck the Q6,Q8
Check the IC16, IC17, IC18
OK
OK
Check the Other board ( Image Board or Driver Board ) or Cable.
2-2. 2-2. Operation Explanation of Driving CircuitOperation Explanation of Driving Circuit1. Overview of Driver Circuit
1) Definition of Driver Circuit
The driver circuit division drives the panel with the proper wave form (high voltage pulse) to develop image on
the outside terminal division (X electrode group, Y electrode group, Address electrode).
High voltage switching pulse is made by MOSFET combination.
2) Working Principle of Driver Circuit
To develop image on the PDP, the voltage should be impressed into the X, Y and ADDRESS electrodes
(which are component of each pictorial element) under the proper conditions. The driver wave form which is
currently applied to is ADS (Address & Display Separate: Driving method to work by dividing address and
constant-current section ) Based on this method, the discharge to be done in the pictorial element of PDP
can be divided into 3 types as follows.
● Address Discharge: to form the wall voltage within pictorial element by providing lighting pictorial
element with information(impressing data voltage)
: It is the discharge produced by difference between the positive electric potential of address electrode
(normally, Va impressed voltage of 70~75V +Positive Wall charge) and
negative electric potential of Y electrode
(GND level impression+ Negative Wall charge).
Operation Description on Driving Board
● Constant-current Discharge: It is the display section to form discharge voluntarily with the help of
wall voltage formed by address discharge. (It makes optical power to create image)
: It is the Self Sustaining Discharge made by combining the electric potential of coherent pulse, normally
160-170Volt, which alternates the X electrode with Y electrode in the sustain section, with the wall voltage
according to the pictorial element condition changed by if the former discharge exists or not. That is to say,
it works according to Memory characteristic (it means that former working condition defines the
current condition) as the basic feature of AC PDP.
If the wall voltage formerly exists in the pictorial element(i.e., the pictorial element is on), the discharge makes
forms again because the voltage higher than one of the discharging starting time is impressed by combination
of the wall voltage and of the next impressed constant-current.
While if the wall voltage does not exist in the pictorial element (i.e., the pictorial element is off), the discharge
does not form because the voltage could not reach to the level of the discharging starting time, only with
constant-current.
Operation Description on Driving Board ● Erasing discharge: To selectively perform the address discharge for respective pixel, pixels of all
panels must be on same conditions (same wall charge state and space charge state).
Therefore the erasing discharge zone is important factor to obtain driving margins.
There are various methods such as application of log waveform but the wall voltage control method
by the Ramp Waveform is now widely applied.
: The purpose of intialization (Erasing) discharge is to make wall voltage within the the whole of Pixels.
In other words, the erasing discharge must make difference between wall voltages uniform depending on
whether or not the sustain discharge exists in the previous state. Namely it must remove the wall voltage
formed by the sustain discharge and supply ions or elements by causing discharge for removing the wall
voltage. In the other words, To remove the wall voltage, limit the time when polarity of the wall voltage is
reversely charged by causing discharge or prevent polarity form being reversely charged by supplying
appropriate quantity of ions or elements through forming weak discharge [low voltage of erasing].
There are two types of the weak discharge [low voltage]as known so far. 1) Log Waveform adopted by
the F-company 2) Weak erasing discharge by the Ramp Waveform largely adopted by Matsushita
company, etc. Outside applied voltage is adjusted depending on difference of wall voltage within Pixel,
since discharge is formed when the sumof the existing wall voltage remained and the voltage on a
rising waveform exceed the driving beginning voltage, by slowly applying the
rising slope of the erased waveform for these two methods. In addition,
weak discharge is formed since the strength of applied voltage is small.
Operation Description on Driving Board
3) Essential factors for driving board operation
- Supplied from power board and the optimum value may somewhat differ from
the below cases.
● Vs : 85V - Sustain
● Vset : 60V ~ 70V - Y Rising Ramp
● Ve : 110V - Ve bias
● Vscan : 70V ~ 80V - Scan bias
● Vdd : 3.3V - Logic signal buffer IC
● Vcc : 15V - FET Gate drive IC
● Logic Signal
: Supplied from logic board
: Gate signal of each FET
Driving Waveform Specification Arrangement
Y rising
Ramp
Y fallingRamp Y scan
Pulse
Y sustain
Pulse
X sustain
Pulse
AddressPulse
A1,2..... Address(=Data) Electrode
X Common & Sustain Electrode
Y1,2.... Scan & Sustain Electrode
Vs 85V Ve 110V
Vset 95V Va 79V
Vscan 85V
Explanation of Function per Pulse
● Y Rising Ramp Pulse
Outside voltage of about 390V~400V is applied to the Y electrode in the Y Rising Ramp zone, and weak
discharge begins if respective gap voltage equals to the discharge beginning voltage.
Negative Wall charges accumulate on the Y electrode and the Positive Wall charges on the X electrode in
the whole while weak discharge is maintained.
● Y Falling Ramp Pulse
Most of Negative Wall charges accumulated on the Y electrode by the X bias of about 200V are used to
remove Positive Wall charges in the Y Falling Ramp zone, and most of Positive charges accumulated on
the (0V) Rising Ramp zone toward the address electrode are maintained, having distribution of wall
charges beneficial for the subsequent address discharge.
Explanation of Function per Pulse
● Y Scan Pulse
Y scan pulse is called as injection pulse, and selects the Y electrode one by one (Line-at-a-time).
In this case, Vscan is called as Scan bias. For the electrode line with the Vscan voltage applied,
voltage of about 70 Volt (Vscan) is applied, and voltage of 0 Volt(GN0) is applied.
However, since Negative Wall charges accumulate on the Y electrode by the application of Ramp pulse
and Positive Wall charges accumulate on the address electrode, voltage of more than the discharge
beginning voltage is applied to the cell where address pulse(70V~75V) is allotted and thus address
discharge occurs. Address time of the PDP is very long since both scan pulse and data pulse must be
applied in line at a time.
● 1st Sustain Pulse
The Sustain Pulse always begins from the Y electrode, it is because Positive Wall charges are formed on
the Y electrode if address discharge occurs. The wall charges formed by the address discharge are less
than those for the sustain discharge, and thus the strength of the initial discharge is weak.
Sustain discharge usually become stable after 5~6 times of discharge depending on structure of electrode
and environment. Therefore, the initial long sustain pulse is intended to form the initial
discharge stable and form the wall charges much as possible as.
1. Y buffer - To check whether there is failure of the Y Main, firstly check normal operation of the Y buffer. - After separating both the Y Main and the Y buffer connector, - Check forward voltage drop of 0.4V ~ 0.5V by diode check between OUTL and OUTH. - In addition, resistance between both ends is also more than several kΩ.
Trouble shooting on Driving Board
OUTLOUTH
OUTH
OUTL
OUTL OUTH
Trouble shooting on Driving Board2. Y Main
- After connecting both the Y Main and the Y buffer, check that output of one of OUT1~8 of the Y buffer
is done as follows in application of power
OUT1 OUT2
OUT4OUT3
OUT6 OUT5
※ You must check 1EA of Scan pulse is output
Trouble shooting on Driving Board 3. X Main
- Check output of the TPOUT on the X board is done as follows in application of power
TPOUT
2-3. 2-3. Operation Explanation of Logic BoardOperation Explanation of Logic Board
LVDS
EP20K400EBC652-1
FPGA
FRONT_XY MEMORY
CONTROLLER
SPS10-MEM
ASIC
64M
SDRAM
64M
SDRAM
EPC2 EPC2 EPC2 RESET
Circuit
28BV256K
Image Signal Logic Power3.3V,5V
Vs StartSignal
Image Signal8 bit per DATA R.G.B1 bit per H,V SYNC
IIC(SCL,SDA)
IIC(SCL,SDA)
Y CONTROL
X CONTROL
8 bit per DATA R.G.B1 bit per H,V SYNC1 bit per DATA_EN,TSC,POL,SEN,SDA,SCLK_nRESET
Vs start60MHz
40MHz
Y CONTROL
X CONTROL
IICVCC(3.3V)GND
e-buffer f-buffer g-buffer
ADRV101~106ADRV201~206ADRV301~306CLK,BLK,POL,STB
ADRV401~406CLK,BLK,POL,STB
ADRV501~506ADRV601~606ADRV701~706CLK,BLK,POL,STB
CLK_XY(20MHz),SV_SYNC
27MHz
nRESET
SW200128.636MHz
OSC
CY2305
CY2305
LA03 CN803
CN101
CN201
CN2002
CN401 CN402 CN403
U2005
U2001U2000
U2014 U2013U2003 U2002
U2011 U2007 U2006
U2004
X2000
X2001
X2002
[Logic Block Diagram]
Definition of Name and Terms on Logic Board①
②
③ ④
⑤
⑥
⑩
⑪
⑦ ⑧ ⑨
⑫
No. Item Explanation
① LVDS connector Connector for receiving RGB, H, V, DATAEN, DCLK encoded in the LVDS from image board.
② LED for operation check LED to show that Sync, clock is normally input into the logic board
③ I2C connector Connector connecting the Key Scan Board that checks and adjusts 256K data
④ 256K Eeprom to save γ table, APC table, driving waveform timing and other option, etc
⑤ Y connector Connector to output control signal of the Y driving board
⑥ X connector Connector to output control signal of the X driving board
⑦ CN401(E-address buffer connector) Connector to output address data, control signal to the E-buffer board
⑧ CN402(F-address buffer connector) Cnnector to output address data, control signal to the F-buffer board
⑨ CN403(G-address buffer] connector) Connector to output address data, control signal to the G-buffer board
⑩ Power connector Connector to receive power 95V] to the logic board
⑪ Power fuse Fuse attached to power [5V] to the logic board
⑫ OPTION S/W Inner/Outer cut-off S/W
M O D E L
LOGIC BOARD
OPTION S/W
STATUS
REMARKS
42" SD
External
: 2,4 On
Internal
: 3 On1 2 3 4
ON
OFF
Explanation of Logic Board
Logic board is composed of a logic main board that generates and outputs the address driver output signal
and the XY driving signal by processing image signal, and a buffer board that buffers the address driver output
signal and delivers it to the address driver IC (COF Module).
Logic Board Function Remarks
Logic Main
- Processes Image signal (W/L, error dispersion, APC)
- Outputs image signal as address driver control signal,
data signal buffer board
- Outputs the XY driving board control signal
Buffer Board
E Buffer board- Delivers data signal and control signal to the
right/right COF
F Buffer boadr- Delivers data signal and control signal to the
middle/lower COF
G Buffer board- Delivers data signal and control signal to the
Right/ Lower COF
2-4. Explanation of Scaler(Image Board) Operation2-4. Explanation of Scaler(Image Board) OperationDIGITAL BOARD IC & SIGNAL BLOCK DIAGRAM ANALOG SignalCRYSTAL DIGITAL Signal CLOCK Signal
SDA6000
DVI
SNI
ASI500
FLI2200
VPC3230
M27V160K4S643232E
AD9883
SiI161A
K4S643232E
K4S643232E
K4S641632E
M27V160
VPC3230K4S643232E
K4S643232E
DS90C385
6M
20.25M
DVI SOUND D-SUB D-SUBSound
S-VIDEO S-VIDEO/VIDEO SoundRS-232
FROM SMPS
FROMCONTROLPCB
74HC4052
14.3181M
20.25M
Z86129
BA7657
TO LOGIC
S-VHS Y/CR/G/B/H/V
CVBS
Y/C
Y/Pb/Pr/H/V
DVI L/R
D-SUB L/R
DVI,D-SUB L/R
S-VHS L/R
Explanation of Scaler(Image Board) OperationExplanation of Scaler(Image Board) OperationANALOG BOARD IC & SIGNAL BLOCK DIAGRAM ANALOG SIGNALCRYSTAL DIGITAL SIGNAL CLOCK SIGNAL
TA1101
TEA6425
BA7657
COMPONENT1 COMPONENT1 SOUNDVODEO COMPONENT2 SOUNDCOMPONENT2 Sub-wooferOutput
CXA2151
4M
MSP3451
18.432M
UPD6408320M
FROM SMPS
Y/Pb/Pr 1 Y/Pb/Pr 2VIDEO-CVBS
S-CVBS
CVBS CVBS
Y/C
Y/Pb/Pr
Y/Pb/Pr/H/V S-VHS L/R
DVI,D-SUB L/R
L/R
SUB WOOPER
SOUND OUTPUT
TUNER 2 TUNER 1
RFINPUT
M-CVBS
CN103
CN102
CN101
CN801
Factory Data per each Mode
1. UPD 64083 (COMB FILTER)
ITEM TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) PC DVI
VAPGAIN 4 4 4 4
VAPINV 16 16 16 16
YPFP 3 3 3 3
YPFG 9 9 9 9
2. VPC 3230(M) : Main VCDITEM TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) PC DVI
CONTRAST 43 43 43 43
BRIGHTNESS 47 47 47 47
PEAKING 5 5 5 5
CORING 0 0 0 0
LUMA DELAY 255 255 255 255
HPLL SPEED 1 1 1 1
YUV CONTRAST 29 29 29 29
YUV BRIGHTNESS 68 68 68 68
YUV SATCB 42 42 42 42
YUV SATCR 42 42 42 42
YUV TINT 3 3 3 3
SATURATION 2000 2000 2000 2000
TINT 32 32 32 32
Factory Data per each Mode
3. VPC 3230(S) : SUB VCD
ITEM TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) PC DVI
PIP CONTRAST 43 43 43 43
PIP BRIGHTNESS 47 47 47 47
YUV CONTRAST 29 29 29 29
YUV BRIGHTNESS 68 68 68 68
LUMA DELAY 255 255 255 255
H POSITION 0 0 0 0
V POSITION 0 0 0 0
4. FLI 2200 (De-Interlacer)
ITEM TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) PC DVI
Y CLAMP 64 64 64 64
C CLAMP 512 512 512 512
Y DELAY 4 4 4 4
C DELAY 11 11 11 11
MOTION DETECT 48 48 48 48
Factory Data per each Mode
5. ASI500 (SCALER MAIN / OSD)ⅠITEM TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) PC DVI
R CONTRAST 32
G CONTRAST 32
B CONTRAST 32
R BRIGHTNESS 0
G BRIGHTNESS 0
B BRIGHTNESS 0
TEXT ALPHA 1
TEXT THRESHOLD 7
FILTER ML 0
FILTER MR 0
FILTER FR 0
FILTER MC 16
FILTER UC 0
FILTER LC 0
FILTER YPASS 0
R GAMMA 32
G GAMMA 32
B GAMMA 32
H POSITION 0
V POSITION 0
H SIZE 0
V SIZE 0
OVERSCAN B 63
OVERSCAN G 63
OVERSCAN R 63
Factory Data per each Mode
6. ASI500 (SCALER PIP)ⅡITEM TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) PC DVI
PIP R CONT 32
PIP G CONT 32
PIP B CONT 32
PIP R BRIGHT 0
PIP G BRIGHT 0
PIP B BRIGHT 0
PIP FILTER LC 0
PIP FILTER ML 0
PIP FILTER MR 0
PIP FILTER UC 0
8. CXA2151HD (COMPONENT MUX)
ITEM TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) PC DVI
GAIN-SEL 1 1 1 1
CR GAIN 7 7 7 7
CB GAIN 7 7 7 7
Y GAIN 7 7 7 7
Factory Data per each Mode
7. DNIe (Picture Enhancer)
ITEM TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) PC DVI
BRIGHT OFFSET 0
CONTRA OFFSET 0
NR SCALE MAX 52
NR SCALE MIN 18
DE GAIN COR 3
DE GAIN CLIP 60
CE UPPER 240
CE CUTOFF 64
CE GAIN 48
WTE Y THRE 230
R CTL 2
SYNC MODE 1
PATT SEL 0
RED CONPENSA 616
BLUE CONPENSA 616
WTE GAIN 58
RAST VSIZE 1023
RAST HSIZE 895
SHARP OFFSET 0
Factory Data per each Mode9. AD 9883 (AD Converter)
ITEM TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) PC DVI
R GAIN 142 142 142 142
G GAIN 142 142 142 142
B GAIN 142 142 142 142
R, CR OFFSET 60 60 54 60
G, Y OFFSET 48 48 54 48
B, CB OFFSET 64 64 54 64
Auto Color
10. Logic (PDP Driver)ITEM TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) PC DVI
R DRIVE 140 140 140 140
G DRIVE 130 130 130 130
B DRIVE 120 120 120 120
R CUTOFF 0 0 0 0
G CUTOFF 0 0 0 0
B CUTOFF 0 0 0 0
GAMMA 1
GTS SET 0
ERD MODE 2
RANDOM NOISE 0
DIFF FILTER 1
APC 1
APC SET 0
APC VALUE 127
ACTIVE VPOS 12
ACTIVE HPOS 19
VSYNC POS 3
HSYNC POS 32
VSYNC WIDTH 2
HSYNC WIDTH 12
Factory Data per each Mode11. TP LOG-ASI : Test Pattern LOGIC/SCALER
ITEM TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) PC DVI
LOG PATTERN 0
LOG HIGH LEVEL 255
LOG LOW LEVEL 0
ASI COLORBAR 0
12. Option
ITEM TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) PC DVI Remark
PIX SHIFT 0 0:OFF 1:ON
SHIFT TEST 0 0:minute 1:second
PIX NUMBER 2 Number of shifted Lines horizontally
SHIFT LINE 1 Number of shifted Lines vertically
SHIFT TIME 4 Time fixed at SHIFT TEST
COUNTRY 0 0:domestic 1:USA 2:Japan
TEMP PROTECT 0
SNI DEMO 0 0:OFF 1:ON
SNI THROUGH 0 0:NOT THROUGH 1:THROUGH
VIDEO MUTE 10 Unit:100msec
IRC AFN 0 0:for customer 1:for military
LANGUAGE 0 0:English 1:French 2:Spanish
CUSTOMER 0 0:CE 1:VMB
TUNER 0 0:1 TUNER 1:2 TUNER
Signal Waveform at AV(Audio & Visual) BoardSignal Waveform at AV(Audio & Visual) BoardInput Signal : 8-Color BarInput Signal : 8-Color Bar
ANALOG BOARD IC103(TEA6425D) PIN6(VIDEO-CVBS) ANALOG BOARD CN102 PIN12(3D_Y_OUT)
ANALOG BOARD CN102 PIN10(3D_C_OUT) DIGITAL BOARD IC101(VPC3230D-C5) PIN57(VPC_VSYNC)
Signal Waveform at AV(Audio & Visual) BoardInput Signal : 8-Color Bar
* Dimensions in mm
DIGITAL BOARD IC101(VPC3230D-C5) PIN56(VPC_HSYNC) DIGITAL BOARD IC101(VPC3230D-C5) PIN28(VPC_CLK)
DIGITAL BOARD IC104(FLI2200) PIN91(FLI_VSYNC) DIGITAL BOARD IC104(FLI2200) PIN92(FLI_HSYNC)
Signal Waveform at AV(Audio & Visual) BoardInput Signal : 8-Color Bar
DIGITAL BOARD IC104(FLI2200) PIN90(FLI_DE) DIGITAL BOARD IC104(FLI2200) PIN117(FLI_CLK)
DIGITAL BOARD RW507(ASI500 OUTPUT) PIN2(MN_IN_V) DIGITAL BOARD RW507(ASI500 OUTPUT) PIN1(MN_IN_H)
Signal Waveform at AV(Audio & Visual) BoardInput Signal : 8-Color Bar
DIGITAL BOARD RW507(ASI500 OUTPUT) PIN4(MN_IN_CLK) DIGITAL BOARD IC601(SNI OUTPUT) PIN9(OUT_VSYNC)
DIGITAL BOARD IC601(SNI OUTPUT) PIN10(OUT_HSYNC) DIGITAL BOARD IC601(SNI OUTPUT) PIN8(OUT_DE)
Signal Waveform at AV(Audio & Visual) BoardInput Signal : 8-Color Bar
DIGITAL BOARD IC601(SNI OUTPUT) PIN12(OUT_CLK) ANALOG BOARD IC101(CXA2151 OUTPUT) PIN27(COMP_Y)
ANALOG BOARD IC101(CXA2151 OUTPUT) PIN26(COMP_PB) ANALOG BOARD IC101(CXA2151 OUTPUT) PIN25(COMP_PR)
Signal Waveform at AV(Audio & Visual) BoardInput Signal : 8-Color Bar
ANALOG BOARD IC101(CXA2151 OUTPUT) PIN23(COMP_V) ANALOG BOARD IC101(CXA2151 OUTPUT) PIN22(COMP_H)
DIGITAL BOARD IC705(AD9883 OUTPUT) PIN64(ASI_SUB_V) DIGITAL BOARD IC705(AD9883 OUTPUT) PIN66(ASI_SUB_H)
Signal Waveform at AV(Audio & Visual) BoardInput Signal : 8-Color Bar
DIGITAL BOARD IC705(AD9883 OUTPUT) PIN65(ASI_SUB_SOG) DIGITAL BOARD IC705(AD9883 OUTPUT) PIN67(ASI_SUB_CLK)
DIGITAL BOARD IC702(SII169CT OUTPUT) PIN47(DVI_VSYNC) DIGITAL BOARD IC702(SII169CT OUTPUT) PIN48(DVI_HSYNC)
Signal Waveform at AV(Audio & Visual) BoardInput Signal : 8-Color Bar
DIGITAL BOARD IC702(SII169CT OUTPUT) PIN46(DVI_DE) DIGITAL BOARD IC702(SII169CT OUTPUT) PIN44(DVI_CLK)
Trouble Shooting for PDP Set
Turn on the set
LED Normal
OK
NO
Check VS_ON(3V)
CN803(SMPS pin2)
NO Change
Logic
Remove all Connectors
from SMPS(except AV) and
Check the protection
or voltages
Protection or
LED problems
Check PS_ON(0V:SMPS CN802 pin4) &
Check stand_by 5V(SMPS CN802 pin2)
OKConnect
X-MainOK
Connect
Address
Buffer
Connect
Y-Main
OK OKCheck
other
Boards
Change
Address
Buffer
NOChange
Y-Main
NOChange
X-MainNO
NO LED
Change
SMPSNO
Check Voltages
on the SMPS
(Vs,Va,Ve,Vset..)
OK Check the
Key-Pad
Remove all Connectors
from SMPS and Check the
voltages on AV Boards
NO OK Change
Digital
Change
SMPSNO
Remove Connectors from
X,Y-Main,Address
Buffers and Check the
voltages on SMPS again
NONO
Change
SMPS
OKOK
NO Voltages
Checkthedamaged
components on
X,Y-Main &
Address Board
Yes Change the
damaged Board
NO Damaged Components
ChecktheFuses on
X,Y-Main Boards
(F4003,F5003)NO
Change the
damaged Board
OK
Change Y-MainNO
Change X-MainNO
Checkwhether
always No Video
about all AV inputsNO, can't see
any Video
Change
Digital NO NO
Check the
LVDS cable
Change
Logic
I can see some Video
ex) TV,Video or etc InputsourceChange
Analog
Almost No
Voltages
on the SMPS?
Only Vs or Va cannot be measured
Comparison with New ModelsProject Alexander (V2) Mozart (V3) Nelson (V3)Design
Brightness 700cd/m2 1000cd/m2 1000cd/m2
Contrast ratio
1200:1 3000:1 3000:1
Tuner 2Tuner 2Tuner 1Tuner
Audio out 10W x 2 15W x 2 15W x 2
Sound Dolby Virtual SRS Tru Surround XT SRS Tru Surround XT
Speaker Not Included Included Not Included
Video input 1Rear 2Rear 1Rear
S-Video input 1Rear 1Rear 1Rear
Component Input
2Rear 2Rear 1Rear
Side Input - CVBS, S-Video -
DVI 1Rear 1Rear 1Rear
Power Consumption
330W 330W 330W
Etc. - Touch Pad, Melody -
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