s. e. thompson eel 6935 today’s subject continue on some basics on single-wall cnt---- chiral...

Post on 03-Jan-2016

216 Views

Category:

Documents

0 Downloads

Preview:

Click to see full reader

TRANSCRIPT

S. E. Thompson EEL 6935

Today’s Subject

Continue on some basics on single-wall CNT----chiral length, angle and band gap;

Other properties of CNT; Device applications; Growth of CNT; Si nanowires; Other nanowires; Growth Challenges.

S. E. Thompson EEL 6935

2

““Roll” Carbon Nanotube from GrapheneRoll” Carbon Nanotube from Graphene

nmmnaCCCL hhh 22

LD

Ch = n a1 + m a2 (n, m); (n, m are integers; 0 m n).

cos = Ch a1 / |Ch||a1|.

S. E. Thompson EEL 6935

3

Nanotube ChiralityNanotube Chirality

S. E. Thompson EEL 6935

4

Examples of Band StructuresExamples of Band Structures

One-dimensional energy dispersion relations for (a) armchair (5, 5), (b) zigzag (9, 0), and (c) zigzag (10, 0) carbon nanotubes.

S. E. Thompson EEL 6935

5

Bandgap of Semiconducting TubeBandgap of Semiconducting Tube

S. E. Thompson EEL 69356

ATM or STM Used to Determine Chirality

(11,7)

S. E. Thompson EEL 6935

Multi-wall CNT

TEM Image

Multi Wall Tubes

S. E. Thompson EEL 6935

8

Material Properties of CNT-continued

S. E. Thompson EEL 6935

Comparison of Other Materials to CNT

Material Young’s Modulus (GPa) (Modulus of Elasticity)

Yield Strength(Gpa)

Concrete, High Strength

30 0.04 ?

Aluminum 69 0.095

Titanium Alloy 105-120 0.73

Si 170 ?

Steel 200 0.69

Diamond 1050-1200 ?

SWCNT/MWCNT 1050/1200 (same as diamond)

~200

Space Elevator

CNT cableSuper strong, light weight

S. E. Thompson EEL 6935

10

Material Properties of CNT-continued

S. E. Thompson EEL 6935

11

Electronic Applications

CNT transistor

S. E. Thompson EEL 6935

Demonstration of CNT Memory Design

http://www.nantero.com/index.html

Applied charge make CNT ribbons bend down to touch the substrate or bend up back to its original state.Ribbon-up gives 'zero' and ribbon-down is 'one'.

S. E. Thompson EEL 6935

Structure13

Fabricated on a silicon wafer, CNT ribbons are suspended 100 nanometers above a carbon substrate layer.

S. E. Thompson EEL 6935

Off-State14

S. E. Thompson EEL 6935

On-State15

S. E. Thompson EEL 6935

Read-Out16

S. E. Thompson EEL 6935

17

Structural and Mechanical Applications

S. E. Thompson EEL 6935

18

CNT interconnect Lines

S. E. Thompson EEL 6935

19

Bottom-up Approach for CNT interconnects

S. E. Thompson EEL 6935

20

Sensors, NEMS Applications

S. E. Thompson EEL 6935

21

CNT-based Bio Sensors

S. E. Thompson EEL 6935

22

S. E. Thompson EEL 6935

23

Carbon Nanotube Growth

S. E. Thompson EEL 6935

24

Three Basic CNT Growth Methods

A: Laser ablation;B: Arc discharge;C: Catalytic chemical vapor deposition (CCVD).

All currently known methods consist of some variant of one of these approaches.

A

B

C

S. E. Thompson EEL 693525

Bottom-up Growth of CNTs

S. E. Thompson EEL 6935

26

CNT Nanoelectrode Array

S. E. Thompson EEL 6935

27

Si Nanowires

A Si nanowire MOSFET

Ultrahigh piezoresistance of Si nanowire: sensor application, actuator, microscope cantilever, etc.

S. E. Thompson EEL 6935

28

Si Nanowire Growth

Vapor-Liquid-Solid mechanism Si nanowire growth.Difference between Si nanowire and CNT: CNT is hollow, but Si nanowire is solid with crystalline core.

S. E. Thompson EEL 693529

Si Nano Wire Transistors

S. E. Thompson EEL 6935

30

Nanowire-based Vertical Gate Transistor

S. E. Thompson EEL 6935

31

ZnO Nanowires

S. E. Thompson EEL 6935

32

Challenges of Nanowire Growth

S. E. Thompson EEL 6935

33

Challenges of Nanowire Growth

S. E. Thompson EEL 693534

Nanoelectronics – Now or Never?" IEDM Evening Panel Discussion, December 14,

Session 26: 8:00 p.m. Continental Ballroom 6-9 Moderator: Mark Lundstrom, Purdue University "Nanoelectronics – Now or Never?" Traditional 'top-down' microelectronics has become nanoelectronics with device dimensions comparable to those being explored in the new field of ëbottom-up' nano- and molecular electronics. We use the terms, top-down and bottom-up, in a very general sense. Top-down refers to a way of thinking and building that begins at the macro (continuum) scale and pushes to the nanoscale. Bottom-up refers to a way of thinking and building that begins at the atomistic level and builds up to the nanoscale. The top-down approach has already delivered silicon MOSFETs with channel lengths of ~ 5nm, but scaling down device dimensions with commensurate increase in device and system performance is increasingly challenging. Bottom-up technology has demonstrated molecular switches, nanotube and nanowire FET's, NDR and single electron devices, and ultra-dense memory prototypes. Is bottom-up nanotechnology ready to address the industry's challenges, or is it still long-term research with essentially unpredictable outcomes? This panel will debate the question of what the intersection of top-down and bottom-up electronics will mean to semiconductor technology of the future.

top related