real-time hdr compressing
Post on 13-Apr-2017
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Real time HDR image compression
Site: http://kanyevsky.kpi.ua
Sergiyenko А.М., d-r of scienceLepekha V.L.
Simonenko A.V.
2. Modern video chips with high dynamic range (HDR)
Output code
К1
К2
ADC maximum
Linear output
Compressed signal
Exposition Т1 Exposition Т2Exposition Т3
Inverse transfer factor
2048 65536 220
400030402048
5. Experimental board Helion HDR-60 programmed as the vision system
Video computing 1280х720 60 Hz, 20 digits per color
Helion HDR-60 Lattice ECP-3 LFE3-70EA
MT9M024
DECOMP
GIST NORM1
COL_FILTR5
MEDIANF_3X3
BW
MUX
HDR_FILTR53
COLOR_REST
TXT_FRAME
TMDS_ENC
U_I2C
HDTV display
SYNCHRO
PCS_IO…
Hardware of FPGA volume available %
CLB slices 8563 33264 25,7
Registers 5694 66528 8,6
MPUs 18х18 34 128 26,6
BlockRAMs 1024х18 56 240 23,3
5. Experimental board Helion HDR-60 programmed as the vision system
Conclusions A simplified HDR-compression algorithm is proposed, which uses the local property analysis function except
the bilateral function
The vision system for the HDR-compression is developed, which compresses the HDR video images from 120 db to 48 db without sharpness losses both in white and in dark areas without artefacts. The system is intended for FPGA implementation, and has small hardware volume.
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