qualis design corporation po box 4444 beaverton, oregon 97075-4444 usa phone: +1-503-670-7200

Industry and Textbook Industry and Textbook OverviewOverview

Qualis Design CorporationPO Box 4444

Beaverton, Oregon 97075-4444 USAPhone: +1-503-670-7200FAX: +1-503-670-0809http://www.qualis.com

Verification ProcessVerification Process Involves

Methods

People

Verification in Design FlowVerification in Design FlowArchitectural

System Design

ComponentSpecifications

Synthesis &Layout

RTL Design& Coding

Verilog, VHDL

SimulationProofs

PhysicalSynthesis

Verification vs TestingVerification vs Testing

Spec HDL

Design

Testbench

Synthesis

EquivalenceChecking

Manufacture

Gates Silicon

TestingFunctionalVerification

People in VerificationPeople in Verification "We do not have the resources to have

dedicated verification engineers"– Amount of work is the same– Slice it differently

Design &Verification

Design

Verification

People in VerificationPeople in Verification "I'm the best hardware designer. Therefore I

know how to write testbenches"– Verification and design have different focus

• Design: meeting performance requirements– Optimism– Coding & design style– Implementation architecture

• Verification: make sure intent has been implemented– Paranoia– Requirement traceability– Controllability & observability

People in VerificationPeople in Verification "I'm the best hardware designer. Therefore I

know how to write testbenches"– Testbench design requires different skills from

hardware design• Design: timing closure

– Scripting– Physical effects– Power, timing

• Verification: software engineering– Configuration management– Abstraction & Objected oriented– Random generation & coverage

People in VerificationPeople in Verification "I want to be a hardware designer when I grow up"

– Hardware design has all the glory• Spread to verification effort

– Properly-designed verification environments require more creativity than design

– More freedom in verification• No subset• No performance constraints• No technology constraints

– All cool, new tools are in verification– Develop verification training &

career paths

People in VerificationPeople in Verification Supply industry aligning with task separation

– P&L business units– Separate sales force– Specialized consultants and AEs– Verification-only companies

• EDA• Services• IP

– Verification curriculum in universities

Manual CheckingManual Checking Unfortunately, very common Use waveform viewer to interpret results

Non reproducible Sensitive to misinterpretations Cannot handle large number of

transactions

Stimulus DUT Vectorfile

Simulator

Viewer

Golden VectorsGolden Vectors Natural extension of DFT & visual check Compare results against known good results

Stimulus Vectorfile

Simulator

Viewer

Vectorfile

Comparator

Compute expected results on-the-fly

Significant effort investment Tolerant of non-functional variations Typical for datacom

On-The-Fly Self-CheckingOn-The-Fly Self-Checking

BFM (Compare)Stimulus DUT

Scoreboard

Transferfunction

Data Structure

Response verified against reference model

Compare function must tolerate non-functional differences

Typical for DSP and CPU– C reference model part of spec

Post-Processing Self-CheckingPost-Processing Self-Checking

Simulator

ComparatorStimulus DUT

Traditional ApproachTraditional Approach Self-checking not a requirement Used with HDLs, or C/C++ Large number of testbenches Progress measured against check-list

Stimulus

Random ApproachRandom Approach Progress measured using functional coverage

metrics

Self-checking, random test environment

development time

Stimulus

Random Vs TraditionalRandom Vs Traditional

Productivitygain

Formal vs Random Vs TraditionalFormal vs Random Vs Traditional

Productivitygain

FormalVerification(Assertions)

PPP Gen

PPP Mon

Testcases

PPP Gen

PPP Mon

PPP Gen

PPP Mon

Ethernet

SPI4.2

Verification IPVerification IP

PPP Gen

PPP Mon

Testcases

PPP Gen

PPP Mon

PPP Gen

PPP Mon

Ethernet

SPI4.2

Verification IPVerification IP

Productivitygain

Verification IPVerification IP Verification IP helps reduce time-to-first-test

Earlier time-to-1st-test

Industry StatusIndustry Status

Laggards Leaders

Self-Checking

Ad-Hoc

Specman,Vera

SpecsCoverage

Driven

FormalVerification

Transactions

VerificationPlan

Verification EngineersCustom Environment

My BookMy Book

Laggards Leaders

Self-Checking

Ad-Hoc

Specman,Vera

SpecsCoverage

Driven

FormalVerification

Transactions

VerificationPlan

Verification EngineersCustom Environment

My BookMy Book

Genesis of the BookGenesis of the Book Self-checking transaction-level testbenches

based on verification plan and behavioral model– Nortel Networks, 1992

Consulting services in verification– Self-employed, 1994

Advanced verification class (3 days)– Qualis Design, 1996

Book started– Dining room table, 1999

Objectives of the BookObjectives of the Book Functional verification is critical There is a process to functional verification Functional verification is different from design Engineers don't know HDLs as well as they

think they do Improve software engineering skills

For Undergrad ClassFor Undergrad Class Chapter 1: What is Verification?

– Why should you care Chapter 2: Verification Tools

– What should you use Chapter 3: Verification Plan

– What should you do Chapter 4: Non-RTL Coding

– There is (better) life beyond RTL– Verilog is not that easy to learn well

For Undergrad ClassFor Undergrad Class Chapter 5: Stimulus and Response

– How should you stimulate– How should you observe– How do you know it's correct

Appendix A: Coding Guidelines– How you should write your code

For Graduate ClassFor Graduate Class Chapter 3: Verification Plan

Chapter 6: Architecting Testbenches– How to minimize your effort– Wrestling with VHDL

Chapter 7: Simulation Management– Actually using the stuff

For Professional ClassFor Professional Class Chapter 3: Verification Plan

Chapter 5: Stimulus and Response– How should you stimulate– How should you observe– How do you know it's correct

For Professional ClassFor Professional Class Chapter 6: Architecting Testbenches

– How to minimize your effort– Wrestling with VHDL

Chapter 7: Simulation Management– Actually using the stuff

For Prelude to HVLsFor Prelude to HVLs Chapter 1: What is Verification?

– Why should you care Chapter 2: Verification Tools

– What should you use Chapter 3: Verification Plan

– What should you do Chapter 5: Stimulus and Response

– How should you stimulate– How should you observe– How do you know it's correct

In Future EditionIn Future Edition Chapter 2: Verification Tools

– Assertions– Formal verification tools– HVLs (Specman, VERA)– Functional Coverage

Chapter 3: Verification Plan– Coverage-driven plan

Chapter 4: Non-RTL Coding– HVLs

In Future EditionIn Future Edition Chapter 5: Stimulus and Response

– Scoreboarding Chapter 6: Architecting Testbenches

– Constrainable Random Generation– Functional Coverage

Chapter 7: Simulation Management– HVLS as reference models– Seed management

Support MaterialSupport Material Quiz

– http://janick.bergeron.com/wtb/quiz.html– 3 questions per chapters– Answers supplied

Verification Project– http://janick.bergeron.com/guild/project.html– 4-port ATM switch– Design specification– Behavioral model (Verilog, VHDL)– Partial solutions provided by contributors

Industry and Textbook Industry and Textbook OverviewOverview

Qualis Design CorporationPO Box 4444

Beaverton, Oregon 97075-4444 USAPhone: +1-503-670-7200FAX: +1-503-670-0809http://www.qualis.com

qualis design corporation po box 4444 beaverton, oregon 97075-4444 usa phone: +1-503-670-7200

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