programmable gain instrumentation amplifier - ti.com · 1 ® pga204/205 a1 a2 a3 12 11 10 25kΩ...
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1
®
PGA204/205
A1
A2
A3
12
11
1025kΩ25kΩ
25kΩ25kΩ
13
7
5
14
16
4VIN
VIN
V+
PGA204 PGA205
Ref
VO
–
+
Over-Voltage Protection
Over-Voltage Protection
Feedback
Digitally Selected Feedback Network
1
VO1
15A1
A0
Digital Ground
6 9 8
VO2 V–VOS Adj
PGA204PGA205
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
Programmable GainINSTRUMENTATION AMPLIFIER
FEATURES DIGITALLY PROGRAMMABLE GAIN:
PGA204: G=1, 10, 100, 1000V/VPGA205: G=1, 2, 4, 8V/V
LOW OFFSET VOLTAGE: 50 µV max
LOW OFFSET VOLTAGE DRIFT: 0.25 µV/°C LOW INPUT BIAS CURRENT: 2nA max
LOW QUIESCENT CURRENT: 5.2mA typ
NO LOGIC SUPPLY REQUIRED
16-PIN PLASTIC DIP, SOL-16 PACKAGES
APPLICATIONS DATA ACQUISITION SYSTEM
GENERAL PURPOSE ANALOG BOARDS
MEDICAL INSTRUMENTATION
DESCRIPTIONThe PGA204 and PGA205 are low cost, general pur-pose programmable-gain instrumentation amplifiersoffering excellent accuracy. Gains are digitally se-lected: PGA204—1, 10, 100, 1000, and PGA205—1,2, 4, 8V/V. The precision and versatility, and low costof the PGA204 and PGA205 make them ideal for awide range of applications.
Gain is selected by two TTL or CMOS-compatibleaddress lines, A0 and A1. Internal input protection canwithstand up to ±40V on the analog inputs withoutdamage.
The PGA204 and PGA205 are laser trimmed for verylow offset voltage (50µV), drift (0.25µV/°C) and highcommon-mode rejection (115dB at G=1000). They op-erate with power supplies as low as ±4.5V, allowing usein battery operated systems. Quiescent current is 5mA.
The PGA204 and PGA205 are available in 16-pinplastic DIP, and SOL-16 surface-mount packages, speci-fied for the –40°C to +85°C temperature range.
®
©1991 Burr-Brown Corporation PDS-1176A Printed in U.S.A. October, 1993
SBOS022
2PGA204/205®
* Specification same as PGA204BP.NOTES: (1) Input-referred noise voltage varies with gain. See typical curves. (2) Output voltage swing is tested for ±10V min on ±11.4V power supplies. (3) Includestime to switch to a new gain.
PGA204BP, BU PGA204AP, AU
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
SPECIFICATIONSELECTRICALAt TA = +25°C, VS = ±15V, and RL = 2kΩ unless otherwise noted.
PGA204 G=1, 10, 100, 1000V/V
INPUTOffset Voltage, RTI TA=+25°C ±10+20/G ±50+100/G ±25+30/G ±125+500/G µV
vs Temperature TA=TMIN to TMAX ±0.1+0.5/G ±0.25+5/G ±0.25+5/G ±1+10/G µV/°Cvs Power Supply VS=±4.5V to ±18V 0.5+2/G 3+10/G * * µV/V
Long-Term Stability ±0.2+0.5/G * µV/moImpedance, Differential 1010||6 * Ω || pF
Common-Mode 1010||6 * Ω || pFInput Common-Mode Range VO=0V (see text) ±10.5 ±12.7 * * VSafe Input Voltage ±40 * VCommon-Mode Rejection VCM=±10V, ∆RS=1kΩ
G=1 80 99 75 90 dBG=10 96 114 90 106 dB
G=100 110 123 106 110 dBG=1000 115 123 106 110 dB
BIAS CURRENT ±0.5 ±2 * ±5 nAvs Temperature ±8 * pA/°C
Offset Current ±0.5 ±2 * * nAvs Temperature ±8 * pA/°C
NOISE, Voltage, RTI(1): f=10Hz G≥100, RS=0Ω 16 * nV/√Hzf=100Hz G≥100, RS=0Ω 13 * nV/√Hzf=1kHz G≥100, RS=0Ω 13 * nV/√Hz
fB=0.1Hz to 10Hz G≥100, RS=0Ω 0.4 * µVp-pNoise Current
f=10Hz 0.4 * pA/√Hzf=1kHz 0.2 * pA/√HzfB=0.1Hz to 10Hz 18 * pAp-p
GAIN, Error G=1 ±0.005 ±0.024 * ±0.05 %G=10 ±0.01 ±0.024 * ±0.05 %
G=100 ±0.01 ±0.024 * ±0.05 %G=1000 ±0.02 ±0.05 * ±0.1 %
Gain vs Temperature G=1 to 1000 ±2.5 ±10 * * ppm/°CNonlinearity G=1 ±0.0004 ±0.001 * ±0.002 % of FSR
G=10 ±0.0004 ±0.002 * ±0.004 % of FSRG=100 ±0.0004 ±0.002 * ±0.004 % of FSRG=1000 ±0.0008 ±0.01 * ±0.02 % of FSR
OUTPUTVoltage, Positive(2) IO=5mA, TMIN to TMAX (V+)–1.5 (V+)–1.3 * * V
Negative(2) IO=–5mA, TMIN to TMAX (V–)+1.5 (V–)+1.3 * * VLoad Capacitance Stability 1000 * pFShort Circuit Current +23/–17 * mA
FREQUENCY RESPONSEBandwidth, –3dB G=1 1 * MHz
G=10 80 * kHzG=100 10 * kHzG=1000 1 * kHz
Slew Rate VO=±10V, G=10 0.3 0.7 * * V/µsSettling Time(3), 0.1% G=1 22 * µs
G=10 23 * µsG=100 100 * µsG=1000 1000 * µs
0.01% G=1 23 * µsG=10 28 * µs
G=100 140 * µsG=1000 1300 * µs
Overload Recovery 50% Overdrive 70 * µs
DIGITAL LOGICDigital Ground Voltage, VDG V– (V+)–4 * * VDigital Low Voltage V– VDG+0.8V * * VDigital Input Current 1 * µADigital High Voltage VDG +2 V+ * * V
POWER SUPPLY, Voltage ±4.5 ±15 ±18 * * * VCurrent VIN=0V +5.2/–4.2 ±6.5 * ±7.5 mA
TEMPERATURE RANGESpecification –40 +85 * * °COperating –40 +125 * * °CθJA 80 * °C/W
3
®
PGA204/205
SPECIFICATIONSELECTRICALAt TA = +25°C, VS = ±15V, and RL = 2kΩ unless otherwise noted.
INPUTOffset Voltage, RTI TA=+25°C ±10+20/G ±50+100/G ±25+30/G ±125+500/G µV
vs Temperature TA=TMIN to TMAX ±0.1+0.5/G ±0.25+5/G ±0.25+5/G ±1+10/G µV/°Cvs Power Supply VS=±4.5V to ±18V 0.5+2/G 3+10/G * * µV/V
Long-Term Stability ±0.2+0.5/G * µV/moImpedance, Differential 1010||6 * Ω||pF
Common-Mode 1010||6 * Ω||pFInput Common-Mode Range VO=0V (see text) ±10.5 ±12.7 * * VSafe Input Voltage ±40 * VCommon-Mode Rejection VCM=±10V, ∆RS=1kΩ
G=1 80 94 75 88 dBG=2 85 100 80 94 dBG=4 90 106 85 100 dBG=8 95 112 89 106 dB
BIAS CURRENT ±0.5 ±2 * ±5 nAvs Temperature ±8 * pA/°C
Offset Current ±0.5 ±2 * * nAvs Temperature ±8 * pA/°C
Noise Voltage, RTI(1): f=10Hz G=8, RS=0Ω 19 * nV/√Hzf=100Hz G=8, RS=0Ω 15 * nV/√Hzf=1kHz G=8, RS=0Ω 15 * nV/√Hz
fB=0.1Hz to 10Hz G=8, RS=0Ω 0.5 * µVp-pNoise Current
f=10Hz 0.4 * pA/√Hzf=1kHz 0.2 * pA/√HzfB=0.1Hz to 10Hz 18 * pAp-p
GAIN, Error G=1 ±0.005 ±0.024 * ±0.05 %G=2 ±0.01 ±0.024 * ±0.05 %G=4 ±0.01 ±0.024 * ±0.05 %G=8 ±0.01 ±0.024 * ±0.05 %
Gain vs Temperature G=1 to 8 ±2.5 ±10 * * ppm/°CNonlinearity G=1 ±0.00024 ±0.001 * ±0.002 % of FSR
G=2 ±0.00024 ±0.002 * ±0.004 % of FSRG=4 ±0.00024 ±0.002 * ±0.004 % of FSRG=8 ±0.00024 ±0.002 * ±0.004 % of FSR
OUTPUTVoltage, Positive(2) IO=5mA, TMIN to TMAX (V+)–1.5 (V+)–1.3 * * V
Negative(2) IO=–5mA, TMIN to TMAX (V–)+1.5 (V–)+1.3 * * VLoad Capacitance Stability 1000 * pFShort Circuit Current +23/–17 * mA
FREQUENCY RESPONSEBandwidth, –3dB G=1 1 * MHz
G=2 400 * kHzG=4 200 * kHzG=8 100 * kHz
Slew Rate VO=±10V, G=8 0.3 0.7 * * V/µsSettling Time(3), 0.1% G=1 22 * µs
G=2 22 * µsG=4 23 * µsG=8 23 * µs
0.01% G=1 23 * µsG=2 23 * µsG=4 25 * µsG=8 28 * µs
Overload Recovery 50% overdrive 70 * µs
DIGITAL LOGIC INPUTSDigital Ground Voltage, VDG V– (V+)–4 * * VDigital Low Voltage V– VDG+0.8V * * VDigital Low Current 1 * µADigital High Voltage VDG+2 V+ * * V
POWER SUPPLY, Voltage ±4.5 ±15 ±18 * * * VCurrent VIN=0V +5.2/–4.2 ±6.5 * ±7.5 mA
TEMPERATURE RANGESpecification –40 +85 * * °COperating –40 +125 * * °CθJA 80 * °C/W
PGA205BP, BU PGA205AP, AU
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
PGA205 G=1, 2, 4, 8V/V
* Specification same as PGA204BP.NOTES: (1) Input-referred noise voltage varies with gain. See typical curves. (2) Output voltage swing is tested for ±10V min on ±11.4V power supplies. (3) Includestime to switch to a new gain.
4PGA204/205®
PACKAGE INFORMATION
PACKAGE DRAWINGMODEL PACKAGE NUMBER (1)
PGA204AP 16-Pin Plastic DIP 180PGA204BP 16-Pin Plastic DIP 180PGA204AU SOL-16 Surface Mount 211PGA204BU SOL-16 Surface Mount 211
PGA205AP 16-Pin Plaseic DIP 180PGA205BP 16-Pin Plastic DIP 180PGA205AU SOL-16 Surface Mount 211PGA205BU SOL-16 Surface Mount 211
NOTE: (1) For detailed drawing and dimension table, please see end of datasheet, or Appendix D of Burr-Brown IC Data Book.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage .................................................................................. ±18VAnalog Input Voltage Range ............................................................. ±40VLogic Input Voltage Range .................................................................. ±VS
Output Short-Circuit (to ground) .............................................. ContinuousOperating Temperature ................................................. –40°C to +125°CStorage Temperature ..................................................... –40°C to +125°CJunction Temperature .................................................................... +150°CLead Temperature (soldering –10s) .............................................. +300°C
MODEL GAINS PACKAGE TEMPERATURE RANGE
PGA204AP 1, 10, 100, 1000V/V 16-Pin Plastic DIP –40 to +85°CPGA204BP 1, 10, 100, 1000V/V 16-Pin Plastic DIP –40 to +85°C
PGA204AU 1, 10, 100, 1000V/V SOL-16 Surface-Mount –40 to +85°CPGA204BU 1, 10, 100, 1000V/V SOL-16 Surface-Mount –40 to +85°C
PGA205AP 1, 2, 4, 8V/V 16-Pin Plastic DIP –40 to +85°CPGA205BP 1, 2, 4, 8V/V 16-Pin Plastic DIP –40 to +85°C
PGA205AU 1, 2, 4, 8V/V SOL-16 Surface-Mount –40 to +85°CPGA205BU 1, 2, 4, 8V/V SOL-16 Surface-Mount –40 to +85°C
ORDERING INFORMATION
5
®
PGA204/205
DICE INFORMATION
PAD FUNCTION
1 VO1
2 —3 —4 V–
IN5 V+
IN
6 VOS Adj7 VOS Adj8 V–
FPO
MECHANICAL INFORMATION
MILS (0.001") MILLIMETERS
Die Size 186 x 130 ±5 4.72 x 3.30 ±0.13Die Thickness 20 ±3 0.51 ±0.08Min. Pad Size 4 x 4 0.1 x 0.1
Backing Gold
Substrate Bias: Internally connected to V– power supply.
PGA204/205 DIE TOPOGRAPHY
PIN CONFIGURATION ELECTROSTATICDISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brownrecommends that all integrated circuits be handled with ap-propriate precautions. Failure to observe proper handling andinstallation procedures can cause damage.
ESD damage can range from subtle performance degradationto complete device failure. Precision integrated circuits maybe more susceptible to damage because very small parametricchanges could cause the device not to meet its publishedspecifications.
NC: No Internal Connection.
VO1
NC
NC
V–IN
V+IN
VOS Adjust
VOS Adjust
V–
A1
A0
Dig. Ground
V+
Feedback
VO
Ref
VO2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Top View
PAD FUNCTION
9 VO2
10 Ref11 VO
12 Feedback13 V+14 Dig. Ground15 A0
16 A1
6PGA204/205®
COMMON-MODE REJECTION vs FREQUENCY
Frequency (Hz)
Com
mon
-Mod
e R
ejec
tion
(dB
)
140
120
100
80
60
4010 100 1k 10k 100k 1M
G = 1k
G = 100
G = 10
G = 1
G = 10
G = 1k,100
“B” Grade G = 1
TYPICAL PERFORMANCE CURVESAt TA = +25°C, and VS = ±15V, unless otherwise noted.
GAIN vs FREQUENCY
Frequency (Hz)
Gai
n (V
/V)
10 100 10k 100k 1M1k
1k
100
10
1
G=1k
G=100
G=10
G=1
INPUT COMMON-MODE VOLTAGE RANGE vs OUTPUT VOLTAGE
Output Voltage (V)
Com
mon
-Mod
e V
olta
ge (
V)
–15 –10 0 5 15–5
15
10
5
0
–5
–10
–1510
Limited by A1
+ Output Swing
A3 – Output Swing Limit
A3 + Output Swing Limit
Limited by A2
– Output SwingLimited by A1
– Output Swing
Limited by A2
+ Output Swing
VD/2–
+–
+
VCM
VO
(Any Gain)
VD/2
POSITIVE POWER SUPPLY REJECTION vs FREQUENCY
Frequency (Hz)
Pow
er S
uppl
y R
ejec
tion
(dB
)
10 100 10k 1M1k
140
120
100
80
60
40
20
0100k
G = 1
G = 10
G = 100
G = 1k
NEGATIVE POWER SUPPLY REJECTION vs FREQUENCY
Frequency (Hz)
Pow
er S
uppl
y R
ejec
tion
(dB
)
10 100 10k 1M1k
140
120
100
80
60
40
20
0100k
G = 1
G = 10
G = 100
G = 1k
INPUT- REFERRED NOISE VOLTAGE vs FREQUENCY
Frequency (Hz)
Inpu
t-R
efer
red
Noi
se V
olta
ge (
nV/√
Hz)
1 10 1k100
1k
100
10
110k
G = 1
G = 10
G = 100, 1k
G = 1k BW Limit
7
®
PGA204/205
TYPICAL PERFORMANCE CURVES (CONT)At TA = +25°C, and VS = ±15V, unless otherwise noted.
INPUT-REFERRED OFFSET VOLTAGE WARM-UP vs TIME
Time from Power Supply Turn-on (s)
Offs
et V
olta
ge C
hang
e (µ
V)
0
6
4
2
0
–2
–4
–615 30 45 60 75 90 105 120
G 100>
INPUT BIAS AND INPUT OFFSET CURRENT vs TEMPERATURE
Temperature (°C)
Inpu
t Bia
s an
d In
put O
ffset
Cur
rent
(nA
)
–75
2
1
0
–1
–2–25 25 75 100 125
±IB
IOS
–50 0 50
INPUT BIAS CURRENT vs DIFFERENTIAL INPUT VOLTAGE
Differential Overload Voltage (V)
Inpu
t Cur
rent
(m
A)
–45
3
2
1
0
–1
–2
–3–30 –15 0 15 30 45
G = 1
G = 10
G = 100, 1k
INPUT BIAS CURRENT vs COMMON-MODE INPUT VOLTAGE
Inpu
t Bia
s C
urre
nt (
mA
)
–45
3
2
1
0
–1
–2
–3–30 –15 0 15 30 45
|Ib1| + |Ib2|
Common-Mode Voltage (V)
Over-Voltage Protection
One Input
Both Inputs
Both Inputs
One Input
Over-Voltage Protection
Normal Operation
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
Out
put V
olta
ge (
Vp-
p)
10
32
28
24
20
16
12
8
4
0100 10k 1M
Frequency (Hz)
100k1k
G ≤ 10
SLEW RATE vs TEMPERATURE
Sle
w R
ate
(V/µ
s)
–75
1.0
0.8
0.6
0.4
0.2
0125
Temperature (°C)
–50 –25 0 25 50 75 100
G=8 or 10
8PGA204/205®
OUTPUT CURRENT LIMIT vs TEMPERATURE
Sho
rt C
ircui
t Cur
rent
(m
A)
–40
30
25
20
15
1085
Temperature (°C)
–15 10 35 60
+|ICL|
–|ICL|
TYPICAL PERFORMANCE CURVES (CONT)At TA = +25°C, and VS = ±15V, unless otherwise noted.
QUIESCENT CURRENT vs TEMPERATURE
Temperature (°C)
Qui
esce
nt C
urre
nt (
mA
)
–75
6.0
5.5
5.0
4.5
4.0–50 –25 0 25 50 75 100 125
QUIESCENT CURRENT vs POWER SUPPLY VOLTAGE
Qui
esce
nt C
urre
nt (
mA
)
0
5.2
5.0
4.5
4.0
3.5
Power Supply Voltage (V)
±5 ±10 ±15 ±20
V–
V+
POSITIVE OUTPUT SWING vs TEMPERATURE
Out
put V
olta
ge (
V)
–75
16
14
12
10
8
6
4
2
0125
Temperature (°C)
–50 –25 0 25 50 75 100
VS = ±15V
VS = 11.4
VS = ±4.5
NEGATIVE OUTPUT SWING vs TEMPERATURE
Out
put V
olta
ge (
V)
–75
–16
–14
–12
–10
–8
–6
–4
–2
0125
Temperature (°C)
–50 –25 0 25 50 75 100
VS = ±15V
VS = 11.4
VS = ±4.5
9
®
PGA204/205
TYPICAL PERFORMANCE CURVES (CONT)At TA = +25°C, and VS = ±15V, unless otherwise noted.
SMALL-SIGNAL RESPONSE, G = 1
+200mV
–200mV
+10V
–10V
+200mV
–200mV
+10V
–10V
+10V
–10V
+200mV
–200mV
LARGE-SIGNAL RESPONSE, G = 1
SMALL-SIGNAL RESPONSE, G = 1000 LARGE-SIGNAL RESPONSE, G = 1000
SMALL-SIGNAL RESPONSE, G = 10 LARGE-SIGNAL RESPONSE, G = 10
10PGA204/205®
TYPICAL PERFORMANCE CURVES (CONT)At TA = +25°C, and VS = ±15V, unless otherwise noted.
NOISE, 0.1 TO 10Hz, G = 1
1s/Div
0.5µV/Div0.2µV/Div
1s/Div
INPUT-REFERRED NOISE,0.1 TO 10Hz, G = 1000
FIGURE 1. Basic Connections.
APPLICATION INFORMATIONFigure 1 shows the basic connections required for operationof the PGA204/205. Applications with noisy or high imped-ance power supplies may require decoupling capacitorsclose to the device pins as shown.The output is referred to the output reference (Ref) terminalwhich is normally grounded. This must be a low-impedanceconnection to assure good common-mode rejection. A resis-tance of 5Ω in series with the Ref pin will cause a typicaldevice to degrade to approximately 80dB CMR (G=1).
The PGA204/205 has an output feedback connection (pin12). Pin 12 must be connected to the output terminal (pin 11)for proper operation. The output Feedback connection can
be used to sense the output voltage directly at the load forbest accuracy.
DIGITAL INPUTS
The digital inputs A0 and A1 select the gain according to thelogic table in Figure 1. Logic “1” is defined as a voltagegreater than 2V above digital ground potential (pin 14).Digital ground can be connected to any potential from theV– power supply to 4V less than V+. Digital ground isnormally connected to ground. The digital inputs interfacedirectly CMOS and TTL logic components.
Approximately 1µA flows out of the digital input pins whena logic “0” is applied. Logic input current is nearly zero witha logic “1” input. A constant current of approximately
A1
A2
A3
12
11
1025kΩ25kΩ
25kΩ25kΩ
7
5
14
16
4VIN
VIN
PGA204 PGA205
VO = G (VIN – VIN)
VO
–
+
Over-Voltage Protection
Over-Voltage Protection
Feedback
Digitally Selected Feedback Network
1
VO1
15
6 9 8
VO2VOS Adj
+15V
1µF
+15V
1µF
+ –
PGA204VIN
VIN
–
+VO
A1 A0
Sometimes shown in simplified form:
A1 A0PGA205PGA204
GAIN
0 0 1 1
0 1 0 1
1 2 4 8
1 10
100 1000
Ref
11
®
PGA204/205
A1
A2
A3
12
11
1025kΩ25kΩ
25kΩ25kΩ
7
PGA204 PGA205
Resistors can be substituted for REF200. Power supply rejection will be degraded.
Feedback
Digitally Selected Feedback Network
6
VO2
V+
VO = G (VIN – VIN) + VREF+ –
OPA177
V+
10kΩ
100Ω
100Ω
V–
VREF
±10mV Adjustment Range
Output Offset Adjustment
5
14
16
4VIN
VIN
–
+
15A1
A0
Digital Ground
200kΩ to 1MΩ
Input Offset Adjustment Trim Range ≈ ±250µV
13
V+
1
VO1
9 8
V–
Over-Voltage Protection
Over-Voltage Protection
100µA 1/2 REF200
100µA 1/2 REF200
1.3mA flows in the digital ground pin. It is good practice toreturn digital ground through a separate connection path sothat analog ground is not affected by the digital groundcurrent.
The digital inputs, A0 and A1, are not latched; a change inlogic inputs immediately selects a new gain. Switching timeof the logic is approximately 1µs. The time to respond togain change is effectively the time it takes the amplifier tosettle to a new output voltage in the newly selected gain (seesettling time specifications).
Many applications use an external logic latch to access gaincontrol data from a high speed data bus (see Figure 7). Usingan external latch isolates the high speed digital bus fromsensitive analog circuitry. Locate the latch circuitry as far aspractical from analog circuitry.
Some applications select gain of the PGA204/205 withswitches or jumpers. Figure 2 shows pull-up resistors con-nected to assure a noise-free logic “1” when the switch,jumper or open-collector logic is open or off. Fixed-gainapplications can connect the logic inputs directly to V+ orV– (or other valid logic level); no resistor is required.
OFFSET VOLTAGE
Voltage offset of the PGA204/205 consists of two compo-nents—input stage offset and output stage offset. Bothcomponents are specified in the specification table in equa-tion form:
VOS = VOSI + VOSO / G (1)
where:VOS total is the combined offset, referred to the input.
VOSI is the offset voltage of the input stage, A1 and A2.
VOSO is the offset voltage of the output differenceamplifier, A3.
VOSI and VOSO do not change with gain. The compositeoffset voltage VOS changes with gain because of the gainterm in equation 1. Input stage offset dominates in high gain(G≥100); both sources of offset may contribute at low gain(G=1 to 10).
OFFSET TRIMMING
Both the input and output stages are laser trimmed for verylow offset voltage and drift. Many applications require noexternal offset adjustment.
Figure 3 shows an optional input offset voltage trim circuit.This circuit should be used to adjust only the input stageoffset voltage of the PGA204/205. Do this by programming
FIGURE 2. Switch or Jumper-Selected Digital Inputs.
A1
A2
7
5
14
16
4
VIN
VIN
–
+
Over-Voltage Protection
Over-Voltage Protection
Digitally Selected Feedback Network15
6 9
VO2VOS Adj
Digital ground can alternatively be connected to V– power supply.
V+
100kΩ100kΩ
Switches, jumpers or open-collector logic output.
FIGURE 3. Optional Offset Voltage Trim Circuit.
12PGA204/205®
it to its highest gain and trimming the output voltage to zerowith the inputs grounded. Drift performance usually im-proves slightly when the input offset is nulled with thisprocedure.
Do not use the input offset adjustment to trim system offsetor offset produced by a sensor. Nulling offset that is notproduced by the input amplifiers will increase temperaturedrift by approximately 3.3µV/°C per 1mV of offset adjust-ment.Many applications that need input stage offset adjustment donot need output stage offset adjustment. Figure 3 also showsa circuit for adjusting output offset voltage. First, adjust theinput offset voltage as discussed above. Then program thedevice for G=1 and adjust the output to zero. Because of theinteraction of these two adjustments at G=8, the PGA205may require iterative adjustment.
The output offset adjustment can be used to trim sensor orsystem offsets without affecting drift. The voltage applied tothe Ref terminal is summed with the output signal. Lowimpedance must be maintained at this node to assure goodcommon-mode rejection. This is achieved by buffering thetrim voltage with an op amp as shown.
NOISE PERFORMANCE
The PGA204/205 provides very low noise in most applica-tions. Low frequency noise is approximately 0.4µVp-p mea-sured from 0.1 to 10Hz. This is approximately one-tenth thenoise of “low noise” chopper-stabilized amplifiers.
INPUT BIAS CURRENT RETURN PATH
The input impedance of the PGA204/205 is extremely high—approximately 1010Ω. However, a path must be provided forthe input bias current of both inputs. This input bias currentis typically less than ±1nA (it can be either polarity due tocancellation circuitry). High input impedance means thatthis input bias current changes very little with varying inputvoltage.
Input circuitry must provide a path for this input bias currentif the PGA204/205 is to operate properly. Figure 4 showsprovisions for an input bias current path. Without a biascurrent return path, the inputs will float to a potential whichexceeds the common-mode range of the PGA204/205 andthe input amplifiers will saturate. If the differential sourceresistance is low, bias current return path can be connectedto one input (see thermocouple example in Figure 4). Withhigher source impedance, using two resistors provides abalanced input with possible advantages of lower inputoffset voltage due bias current and better common-moderejection.
Many sources or sensors inherently provide a path for inputbias current (e.g. the bridge sensor shown in Figure 4).These applications do not require additional resistor(s) forproper operation.
FIGURE 4. Providing an Input Common-Mode CurrentPath.
INPUT COMMON-MODE RANGE
The linear common-mode range of the input op amps of thePGA204/205 is approximately ±12.7V (or 2.3V from thepower supplies). As the output voltage increases, however,the linear input range will be limited by the output voltageswing of the input amplifiers, A1 and A2. The common-mode range is related to the output voltage of the completeamplifier—see performance curve “Input Common-ModeRange vs Output Voltage”.
A combination of common-mode and differential inputvoltage can cause the output of A1 or A2 to saturate. Figure5 shows the output voltage swing of A1 and A2 expressed interms of a common-mode and differential input voltages.Output swing capability of these internal amplifiers is thesame as the output amplifier, A3. For applications whereinput common-mode range must be maximized, limit theoutput voltage swing by selecting a lower gain of thePGA204/205 (see performance curve “Input Common-ModeVoltage Range vs Output Voltage”). If necessary, add gainafter the PGA204/205 to increase the voltage swing.
47kΩ47kΩ
10kΩ
Microphone, Hydrophone
etc.
Thermocouple
Center-tap provides bias current return.
VR
Bridge
Bias current return inherrently provided by source.
PGA204
PGA204
PGA204
PGA204
13
®
PGA204/205
FIGURE 5. Voltage Swing of A1 and A2.
Input-overload often produces an output voltage that appearsnormal. For example, consider an input voltage of +20V onone input and +40V on the other input will obviously exceedthe linear common-mode range of both input amplifiers.Since both input amplifiers are saturated to the nearly thesame output voltage limit, the difference voltage measuredby the output amplifier will be near zero. The output of thePGA204/205 will be near 0V even though both inputs areoverloaded.
INPUT PROTECTION
The inputs of the PGA204/205 are individually protected forvoltages up to ±40V. For example, a condition of –40V onone input and +40V on the other input will not causedamage. Internal circuitry on each input provides low seriesimpedance under normal signal conditions. To provideequivalent protection, series input resistors would contributeexcessive noise. If the input is overloaded, the protectioncircuitry limits the input current to a safe value (approxi-mately 1.5mA). The typical performance curve “Input BiasCurrent vs Common-Mode Input Voltage” shows this inputcurrent limit behavior. The inputs are protected even if nopower supply voltage is present.
FIGURE 6. Switch-Selected PGIA.
A1
A2
A3
12
11
1025kΩ25kΩ
25kΩ25kΩ
13
5
14
16
4
V+
PGA204 PGA205
Ref
VO
Feedback
Digitally Selected Feedback Network
1
VO1
15A1
A0
Digital Ground
9 8
VO2 V–
VD2
VD2
VCM
VCM –G • VD
2
VCM +G • VD
2
Over-Voltage Protection
Over-Voltage Protection
SWITCH POSITION
V+
47kΩ47kΩ
D1, D2: IN4148, IN914, etc.
A0
A1
A
B C
DX
VIN
–
VIN
+
PGA204 PGA205
GAIN
A B C D
1 10
100 1000
1 2 4 8
PGA204 PGA205
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumesno responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to changewithout notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrantany BURR-BROWN product for use in life support devices and/or systems.
14PGA204/205®
GAIN
PGA205 PGA205
1 2 4 8 16 32 64
A3
0 0 1 1 1 1 1
A2
0 1 0 1 1 1 1
A1
0 0 0 0 0 1 1
A0
0 0 0 0 1 0 1
VIN
+
VIN
–
VOAO
A1AO
A1
PGA204 PGA205
VIN–
VIN+
OPA177
20kΩ
Ref
VO
220Ω 20kΩ
VO2
VO1
A0 A1
A1 A0
A1
A2
A3
12
11
1025kΩ25kΩ
25kΩ25kΩ
13
7
5
14
16
4
V+
PGA204 PGA205
Ref
VO
Feedback
Digitally Selected Feedback Network
1
VO1
15
A1
A0
6 9 8
VO2 V–VOSAdj
10
11
12
13
7
6
5
4
8
9
VIN
–
VIN
+
Data Out 74HC574 Data In
3 15 1 16
To Address Decoding Logic
Data Bus
A1A0
HI-509
–15V
+15V
14 2
Over-Voltage Protection
Over-Voltage Protection
CK
FIGURE 7. Multiplexed-Input Programmable Gain IA.
FIGURE 8. Shield Drive Circuit.
FIGURE 9. Binary Gain Steps, G=1 to G=64. FIGURE 10. AC-Coupled PGIA.
PGA204 PGA205
VO
C1 0.1µF
OPA602
Ref R1 1MΩ
f–3dB = 1 2πR1C1
= 1.59Hz
VIN
+
–
A1 A0
PACKAGE OPTION ADDENDUM
www.ti.com 15-Apr-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status(1)
Package Type PackageDrawing
Pins PackageQty
Eco Plan(2)
Lead/Ball Finish(6)
MSL Peak Temp(3)
Op Temp (°C) Device Marking(4/5)
Samples
PGA204AP ACTIVE PDIP N 16 25 Green (RoHS& no Sb/Br)
CU NIPDAU N / A for Pkg Type PGA204AP
PGA204APG4 ACTIVE PDIP N 16 25 Green (RoHS& no Sb/Br)
CU NIPDAU N / A for Pkg Type PGA204AP
PGA204AU ACTIVE SOIC DW 16 40 Green (RoHS& no Sb/Br)
CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA204AU
PGA204AU/1K ACTIVE SOIC DW 16 1000 Green (RoHS& no Sb/Br)
CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA204AU
PGA204AU/1KE4 ACTIVE SOIC DW 16 1000 Green (RoHS& no Sb/Br)
CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA204AU
PGA204AUE4 ACTIVE SOIC DW 16 40 Green (RoHS& no Sb/Br)
CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA204AU
PGA204AUG4 ACTIVE SOIC DW 16 40 Green (RoHS& no Sb/Br)
CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA204AU
PGA204BP ACTIVE PDIP N 16 25 Green (RoHS& no Sb/Br)
CU NIPDAU N / A for Pkg Type PGA204BP
PGA204BPG4 ACTIVE PDIP N 16 25 Green (RoHS& no Sb/Br)
CU NIPDAU N / A for Pkg Type PGA204BP
PGA204BU ACTIVE SOIC DW 16 40 Green (RoHS& no Sb/Br)
CU NIPDAU-DCC Level-3-260C-168 HR PGA204BU
PGA204BU/1K ACTIVE SOIC DW 16 1000 Green (RoHS& no Sb/Br)
CU NIPDAU-DCC Level-3-260C-168 HR PGA204BU
PGA204BUE4 ACTIVE SOIC DW 16 40 Green (RoHS& no Sb/Br)
CU NIPDAU-DCC Level-3-260C-168 HR PGA204BU
PGA205AP ACTIVE PDIP N 16 25 Green (RoHS& no Sb/Br)
CU NIPDAU N / A for Pkg Type -40 to 85 PGA205AP
PGA205APG4 ACTIVE PDIP N 16 25 Green (RoHS& no Sb/Br)
CU NIPDAU N / A for Pkg Type -40 to 85 PGA205AP
PGA205AU ACTIVE SOIC DW 16 40 Green (RoHS& no Sb/Br)
CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA205AU
PGA205AU/1K ACTIVE SOIC DW 16 1000 Green (RoHS& no Sb/Br)
CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA205AU
PGA205AUG4 ACTIVE SOIC DW 16 40 Green (RoHS& no Sb/Br)
CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA205AU
PACKAGE OPTION ADDENDUM
www.ti.com 15-Apr-2017
Addendum-Page 2
Orderable Device Status(1)
Package Type PackageDrawing
Pins PackageQty
Eco Plan(2)
Lead/Ball Finish(6)
MSL Peak Temp(3)
Op Temp (°C) Device Marking(4/5)
Samples
PGA205BP ACTIVE PDIP N 16 25 Green (RoHS& no Sb/Br)
CU NIPDAU N / A for Pkg Type -40 to 85 PGA205BP
PGA205BPG4 ACTIVE PDIP N 16 25 Green (RoHS& no Sb/Br)
CU NIPDAU N / A for Pkg Type -40 to 85 PGA205BP
PGA205BU ACTIVE SOIC DW 16 40 Green (RoHS& no Sb/Br)
CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA205BU
PGA205BUG4 ACTIVE SOIC DW 16 40 Green (RoHS& no Sb/Br)
CU NIPDAU-DCC Level-3-260C-168 HR -40 to 85 PGA205BU
(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 15-Apr-2017
Addendum-Page 3
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device PackageType
PackageDrawing
Pins SPQ ReelDiameter
(mm)
ReelWidth
W1 (mm)
A0(mm)
B0(mm)
K0(mm)
P1(mm)
W(mm)
Pin1Quadrant
PGA204AU/1K SOIC DW 16 1000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PGA204BU/1K SOIC DW 16 1000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PGA205AU/1K SOIC DW 16 1000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PGA204AU/1K SOIC DW 16 1000 367.0 367.0 38.0
PGA204BU/1K SOIC DW 16 1000 367.0 367.0 38.0
PGA205AU/1K SOIC DW 16 1000 367.0 367.0 38.0
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
Pack Materials-Page 2
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