pld

Digital System DesignLecture 4: PLDs

Amir Masoud Gharehbaghiamgh@mehr.sharif.edu

Sharif University of Technology 2

Table of Contents

Simple PLDsComplex PLDsIntroduction to FPGA

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Programmable Logic Devices

Simple PLD (SPLD)

Complex PLD (CPLD)

Field Programmable Gate Array (FPGA)

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SPLD Structure

ANDPlane

ORPlane

Inpu

ts +

Buf

fers

/Inv

erte

rs

Inve

rter

s + O

utpu

ts

Flip

-Flo

ps (o

ptio

nal)

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SPLD Types

ROM (Read Only Memory)Fixed AND planeProgrammable OR plane

PLA (Programmable Logic Array)Programmable AND planeProgrammable OR plane

PAL (Programmable Array Logic)Programmable AND planeFixed OR plane

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Programmablility

For all kinds of SPLDs

One Time Programmable (OTP)Re-Programmable (RP)

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Transistor-Level StructureOR plane

(NOR gates)

AND plane (NOR gates)

x1 x2 x3

P1

P4

P3

P2

f1 f2

Pull-

ups

Pull-ups

21211 xxxxP =+=

Pull-up Network

A B

A+B

312 xxP =

3213 xxxP =

314 xxP =

32131211 xxxxxxxf ++=

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Output Microcell

DQ

Clock

SelectEnable

To AND plane

f

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SPLD Overview

Simple Capacity (~ 200 gates)Interconnection structure prevents high logic capacityPLAs are more flexible than PALs, but they are slowerUsage:

Control CircuitryGlue LogicFSMs

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CPLDs

Multiple PAL like blocksReprogrammableGlobal Interconnects

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CPLD Structure

PAL-likeblock

PAL-likeblock

PAL-likeblock

PAL-likeblock

Interconnection wires

I/O

blo

ckI/

O b

lock

I/O

blo

ckI/

O b

lock

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CPLD Structure (cont.)

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CPLD Overview

Higher Capacity than SPLD~ 5000 gates

Reasonable speedUsage

Simple Systems

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Mask Programmable Gate Array

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Field Programmable Gate Array

Two dimensional structureProgrammableThree elements:

Logic blocksI/O blocksInterconnection wires and switches