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A Low-Energy and High-Performance Voltage Level Shifter
Using Dual-Supply Applications
Dudekula Shashavali1, Sri.K.Raju
2
1M.Tech (VLSI & ES), Department of ECE., G.P.R.E.C, Kurnool, shashabhanu@gmail.com
2Assistant Professor, Department of ECE., G.P.R.E.C, Kurnool, harrisraj99@gmail.com
Abstract— This paper presents a design of
low-energy and high-performance voltage level-
shifting circuit is to capable of shifting low core
voltage to high input-output voltage. The proposed
circuit performance is due to the fact not only
strengthen the pull-up device and slowly reduced
when the pull-down device is pulling output node to
down, but the strength of the pull-down device is also
increases low-power circuit. Simulation results of the
proposed circuit in a 90 nm technology calculate
propagation delay of 7 ns and input frequency of 200
GHz, a static power consumption of 0.12 nW, a total
power per transition of 135 fJ, and, low supply
voltage levels of VDDL=0.9V, and high supply voltage
levels of VDDH=1.8 V.
Index Terms -- Multi supply voltage design,
Level converter, low power sub-threshold operation,
voltage level shifter.
I. INTRODUCTION
Now a days power consumption increases, the
reliability of circuit decreases. There are two types of
power consumption: static power and dynamic power
consumption. The static power dissipation is due to the
leakage current of reverse biased p-n junction diode of
MOSFET. Dynamic power dissipation is mainly due to
the charging and discharging of the load capacitor. The
effective way to lowering the dynamic power and short-
circuits power consumption of a circuit is lowering the
value of the power supply voltage. Lowering the supply
voltage drastically increases the propagation delay of the
circuits. In digital circuits dual-supply voltages are used
in which low voltage(VDDL) is applied for the blocks on
the noncritical paths while a high supply voltage(VDDH) is
applied to the analog and high-speed digital blocks. Level shifter is to be designed with low power
consumption, minimum propagation delay, and silicon
area. Level shifter must be able to convert the low values of VDDL to lower than the threshold voltage of the input
transistors.
II. REVIEW ON EXISTING LEVEL SHIFTERS
Fig.1(a).shows the architecture of conventional
level shifter. The circuit consisting of two cross-coupled
pMOSFETs (MP1 and MP2) and two nMOSFETs (MN1
andMN2) followed by complementary input signals IN
and INB. The circuit has voltage contrast between high
supply voltage VDDH becomes larger than low supply
voltage VDDL.
At the point when the voltages of IN and INB
are Low and High, MN1 and MN2 are Off and On,
respectively. MN2 then pulls Q2 node to down, causing
MP1 to turn On. Because node Q1 then increases to
VDDH, MP2 turns off, and Q1 drops to the GND level.
Note that the voltage at node Q2 is determined by the
drive currents of pull-down transistorMN2 and pull-up
transistor MP2. Therefore, if the drive current of MP2 is
larger than that of MN2, Q2 cannot be discharged.
Consider the case, extremely low-voltage sub-
threshold Level shifter, because the on-current of MN2
becomes low, the drive currents of the nMOSFETs are
significantly smaller than those of the pMOSFETs,
which operate in the strong inversion region. Thus, Q2
node cannot be discharged. As a result, a conventional
level shifter circuit cannot correctly operate in this
situation.
Let us consider, employing week pull-up
devices using high-Vth transistors and/or strong pull-
down networks by using low-Vth transistors. Another way
is to use strong pull-down devices increase in both the
delay and the power consumption and enlarging their
width.
Fig. 1. Schematics of the (a) conventional level-shifter,
(b) level shifter with a SCM, and (c) level shifter with a
DCM (Wilson current mirror).
The last arrangement is to decrease the strength
of the pull-up device when the pull-down device is
pulling down the output node. The structure outlined in
Fig. 1(b) utilizes a semi-static current mirror to confine
the current and strength of the pull-up device (i.e., MP2)
when the pull-down is pulling down the out node. The
semi-static current mirror experiences the static current
coursing through MN1 and MP1 amid the "High" logic
levels of the input signal. With a specific end goal to
diminish the static power utilization, a dynamic current
generator, which turns on just amid the change times, can
be utilized.
The structure shown in Fig. 1(c) employs a
dynamic current generator implemented by MP3. In this
circuit, when the input signal IN goes from “Low” to
“High,” MN1 turns On and MN2 turns Off and pulls the
node QB down. OUT node had been “Low” (before the
transition), during the time interval in which OUT node
is not corresponding to the logic level of the input signal
IN, MP3 will be turned on.
Subsequently, a transition current flows
through MN1, MP3, and MP1. This current is reflected
to MP2 (i.e., IP2) leading to the node OUT up. At last,
when OUT is pulled up to VDDH, MP3 is turned off and
subsequently no static current moves through MN1,
MP3, and MP1.
International Journal of Pure and Applied MathematicsVolume 118 No. 20 2018, 4657-4662ISSN: 1314-3395 (on-line version)url: http://www.ijpam.euSpecial Issue ijpam.eu
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Fig. 2. Level shifter circuit drawn in cadence tool
Fig.[3] shows the Output behaviour of the level
shifter. The plot shows the output node Z,voltages on
input node A and buffered output node. The level shifter
is operated at nominal operating conditions. The input
fall timeand rise times are set to 10 ns, and load
capacitance of 100 fFis connected to the buffered level
shifter output. Output exhibits a rail-to-rail switching
characteristics. The load capacitance only slightly affects
the circuitpropagation delay because of the additional
output buffer.
Fig. 3. Transient behaviour of the Level Shifter.
To decrease the estimation of IP2, another
device, i.e., MP4 in Fig. 3(a) is utilized. For more points
of interest, when MN2 is pulling down the output node,
the gate of MP4 is "High" with the estimation of VDDL
and along these lines the drain– source voltage of MP2 is
diminished. In this manner, as showed up in Fig. 3, the
propagation delay and power dissipation of the circuit
will be decreased. One thing ought to be seen that if the
gate of MP4 and MN2 are driven with a voltage higher
than VDDL, not just the current of the draw up device
(i.e., IP2) is drastically diminished, yet additionally the
strength of pull-up device (i.e., MN2) is expanded.
Consequently, the power and delay are radically reduced.
Besides, the level shifter will have the capacity to work
effectively notwithstanding for subthreshold input
voltages. An assistant circuit (i.e., MP5, MP6, MP7,
MN5, MN6, and MN7) is utilized to turns On just in the high-to-low transition of the input signal to pull up the node QC to an esteem larger than VDDL. At the point when IN changes from "High" to "Low" and OUT isn't at present comparing to the input logic level, MN6, MN7, and MP6 are turned on and MN5 is off. Consequently, a transition current moves through MN6, MN7, MP6, and mirrors to MP7 (i.e., IP7) pulling up the node QC.
Fig. 4. Output waveforms of level shifter
Fig. 5. (a) Principle of the level shifter circuit. (b) Level shifter with auxiliary circuit.
Fig. 6. Simulated waveforms of the level-shifter structures for
low-to-high and high-to-low transitions of the input signal. (a) Voltage of the output node (i.e., VOUT). (b) Voltage of the node
QC. (c) Current of the output branch (i.e., I P2). (d) Entire current of the level shifter supplied by VDDH (i.e., IDDH). (e)
Current of the auxiliary circuit (i.e., IP7 + IP8) of the proposed
structure. The values of VDDH and VDDL are 1.8 V and 0.4 V, respectively.
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Fig. 7. Level shifter schematic drawn in cadence tool
Fig. 8.Output waveforms of level shifter
III. PROPOSED VOLTAGE LEVEL SHIFTER
The proposed Low-Energy and High-
Performance Voltage Level Shifter (LEHP) for dual
supply applications block diagram is shown in the fig. 9
The VDDH and VDDL are the supply voltages of the High
VDD and Low VDD respectively.
The proposed LEHP circuit shown in the fig.
9comprising with 10 no. of MOS transistors, 5 are
PMOSFETs type, namely MP1, MP2, MP3, MP4& MP5
and the remaining 5 are NMOSFETs type, namely MN1,
MN2, MN3, MN4& MP5.The proposed design is totally
different from the conventional level shifters.
Fig. 9. The proposed level shifter drawn in cadence tool
The conventional level up shifter performs
only level up shift and level down shifter performs only
down shift. The proposed level shifter performs both up
shift and down shift with no additional transistors. The
design has configured such that, while level up shift the
VDDH will appears at VDD and while level down shift the
VDDL will appears at VDD. The voltage at VDD
determines the kind of shifting operation.
IV. SIMULATION RESULTS
In this section as a comparative analysis using
90nm Cadence GPDK technology the conventional level
shifter is compared to the dual supply level shifter on the
basis of power consumption and propagation delay. The
availability of high efficiency power supplies and the
availability of a multi-VTH CMOS technology are the
important factors affecting the optimum supply voltages
in a multi-VDD system.
Targeting the minimum power-delay-product
(PDP), all the circuits have been optimally designed to be
functional in all process, voltage, and temperature (PVT)
corners for VDDL = 0.9 V, VDDH = 1.8 V, and the input
frequency of fin=1 MHz.
In the proposed circuit, the transition current
ofIP2must be large enough to reduce the propagation
delay of the low-to-high transition of the output voltage.
The length of MP1 has been selected to be 4μm, whereas
the lengths of the other devices are all chosen of
minimum size (i.e., 0.18 μm). Moreover, the width of
MP2 is also selected to be 1 μm. In addition, since MN2 is
driven by a voltage lower than VDDH, it must be
somewhat strong to be able to pull the output node down.
Hence, the width of this transistor is chosen to be 1 μm,
while the widths of the other transistors are of minimum
size (i.e., 0.4 μm).
Fig. 10. Output waveforms of the proposed level shifter
Simulation results of the proposed circuit for
different values of the input frequency are shown in
Table I. It can be observed that with the reduction of
VDDL, the maximum operating frequency of the circuit is
decreased. The minimum values of VDDL for which the
circuit operates correctly at 100 MHz and 1 GHz are 0.54
V and 0.9 V, respectively.
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Fig. 11. Energy dissipation in level shifter circuit
TABLE I SIMULATION RESULTS OF THE PROPOSED CIRCUIT
(VDDH = 1.8 V)
Fig. 12. Simulated values of (a) the delay and (b) the total
power of the proposed level shifter for different values of
VDDL. The value of VDDH and the input signal frequency are 1.8 V and 1 MHz, respectively.
Fig. 13. (a) Simulated values of the static power dissipation
of the proposed level shifter as a function of VDDL when VDDH = 1.8 V. (b) Total power dissipation and delay of the
proposed structure versus the size of the capacitive load
(VDDL = 0.4 V, VDDH = 1.8 V, and fin = 1 MHz).
Fig. 14. Power consumption of level shifter in
histogram
V. CONCLUSION
In this brief, a Low-energy and High-
performance architecture was proposed which is able to
convert extremely low-input voltages. The efficiency of
the proposed circuit is due to the fact that not only the
current of the pull-up device is significantly reduced
when the pull-down device is pulling down the output
node, but the strength of the pull-down device is also
increased. Post-layout simulation results verified the
efficiency of the proposed circuit compared with other
works, especially from the power consumption
viewpoint.
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FREQUENC
Y (Hz)
VDDL
(V)
VDDH
(V)
POWER
(uW)
DELAY
(ns)
180
nm
5M 0.38 1.8 0.98 45
10 MHZ 0.41 1.8 1.688 24.3
20 MHZ 0.44 1.8 2.77 13.65
50 MHZ 0.49 1.8 5.72 5.81
100 MHZ 0.54 1.8 10.2 2.86
200 MHZ 0.6 1.8 17.66 1.46
500 MHZ 0.72 1 47 0.63
1 GHZ 0.9 1 95 0.34
200 GHZ 1 1 108 0.1
90
nm 500 MHZ 1 1.8 153.6 0.098
International Journal of Pure and Applied Mathematics Special Issue
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I/O voltage,” IEEE Trans. Circuits Syst. I, Reg.
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