multilevel inverter with 12-sided polygonal voltage space vector locations for induction motor...
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Multilevel inverter with 12-sided polygonal voltage space vector
locations for induction motor drive.
BySanjay Lakshminarayanan
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 2
Vdc
A B C
Conventional 2-level inverter
IM
Vr=VA + VB.ej2/3 + VC.ej4/3
Vr= V + j.Vβ
1
2
3
4
5
6
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 3
Hexagonal voltage space vectors
100
110
001
010
011
101
Vr
a-phase
c-phase
b-phase
α
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 4
Topology of a multilevel inverter for generation of 12-side polygonal voltage space vectors for induction motor drives.
A-phase
Pole voltage Level S11 S21 S31
1.366kVdc 3 1 1 0/1
1.0kVdc 2 0 1 0/1
0.366kVdc 1 0/1 0 1
0kVdc 0 0/1 0 0
Table gives voltage levels at A for different switch conditions in that leg.
‘1’=Switch On, ‘0’=Switch Off
‘0/1’=Don’t care
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 5
Some points on the topology
• Consists of three cascaded 2-level inverters
• Asymmetrical DC-links are present
• Induction motor fed from a single side
• Simple structure
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 6
Topology of a multilevel inverter for generation of 12-side polygonal voltage space vectors for induction motor drives.
INV1 and INV3 switches need to have a voltage blocking capacity of 0.366kVdc, while INV2 switches need a blocking voltage of 1.0kVdc.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 7
Generation of voltage space vectors
OQ: (310) implies that leg A is 1.366kVdc, B is at 0.366kVdc and C is zero.OP:(301) implies that leg A is at 1.366kVdc, B is zero, C is 0.366kVdc.OS:(230) implies that leg A is at 1.0kVdc and leg B is at 1.366kVdc and C zero.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 8
The radius(OQ, OP etc.) of the space vector is 1.225kVdc so if we find k that makes the radius= 1Vdc as in a hexagonal space vector we get k=1/1.225=0.816
So now the DC-links of 0.366kVdc=0.299Vdc about 30% of Vdc. The other DC-link of 0.634kVdc= 0.517Vdc about 52% of Vdc.
The total DC-link is 1.366kVdc=1.115Vdc.
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CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 9
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Hexagonal space vectors. 12-sided polygonal space vectors.
100
010
001
110
101
001
Maximum linear range of modulation for hexagonal space vectors: Cos(300).(2/3)Vdc=0.577Vdc
For 12-sided polygonal space vector:
Cos(150).(2/3)Vdc=0.644Vdc
Maximum value of the fundamental for hexagonal space vector: 2/πVdc=0.637Vdc.
For 12-sided polygonal space vector: 0.988.(2/3)Vdc=0.658Vdc.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 10
O P
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J K
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1
234
5
6
7
8
910
11
12
Vr
Vr=VA + VB.ej2/3 + VC.ej4/3
Vr= V + j.Vβ
Generating a reference vector of any amplitude and phase
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 11
0 0 0 01 2. (( 1).30 15 ) . ( .30 15 ) .( )ST V m T V m T V jV
0 0 0 01 2. ( 1).30 . .30 .( ).( 15 15 )ST V m T V m T V jV Cos jSin
0 0 0 01
2. . ( .30 15 ) . ( .30 15 )STT V Sin m V Cos m
V
0 0 0 02
2. . (( 1).30 15 ) . (( 1).30 15 )STT V Sin m V Cos m
V
0 0 0 01
2 3.. . ( .30 15 ) . ( .30 45 )S
B C
TT v Sin m v Cos m
V
0 0 0 02
2 3.. . (( 1).30 15 ) . (( 1).30 45 )S
B C
TT v Sin m v Cos m
V
Volt-sec balance equations
V: radius of polygon, m:sector number, TS is sampling period
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 12
T1 and T2 are found from the reference voltages
A look-up table can speed up calculations
T1 and T2 along with sector number is sufficient to produce the gate signals of the IGBTs in order to operate the inverter
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 13
‘Va’ positive ‘Vb-Vc’ positive: 1st quadrant
‘Va’ negative ‘Vb-Vc’ positive: 2nd quadrant
‘Va’ negative ‘Vb-Vc’ negative: 3rd quadrant
‘Va’ positive ‘Vb-Vc’ negative: 4th quadrant
Sector Identification
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 14
If in quadrant 1:
If |Vb-Vc|<=|Va|.√3.tan150 then sector 1 else
If |Vb-Vc|<=|Va|.√3.tan450 then sector 2 else
If |Vb-Vc|<=|Va|.√3.tan750 then sector 3
else sector 4
If in quadrant 2:If |Vb-Vc|<=|Va|.√3.tan150 then sector 7 elseIf |Vb-Vc|<=|Va|.√3.tan450 then sector 6 elseIf |Vb-Vc|<=|Va|.√3.tan750 then sector 5 else sector 4
Sector Identification
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 15
If in quadrant 3:If |Vb-Vc|<=|Va|.√3.tan150 then sector 7 elseIf |Vb-Vc|<=|Va|.√3.tan450 then sector 8 elseIf |Vb-Vc|<=|Va|.√3.tan750 then sector 9 else sector 10
If in quadrant 4:If |Vb-Vc|<=|Va|.√3.tan150 then sector 1 elseIf |Vb-Vc|<=|Va|.√3.tan450 then sector 12 elseIf |Vb-Vc|<=|Va|.√3.tan750 then sector 11 else sector 10
Sector Identification
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 16
Sampling Strategy for PWM
In order to reduce switching losses the switching frequency is kept low(~1000Hz) using the following sampling sheme:
0<f<=15Hz: 4 samples per sector15<f<=30Hz: 3 samples per sector30<f<=45Hz: 2 samples per sector45<f<=50Hz: 1 sample per sectorWhere f is the frequency of operation in Hz.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 17
V/f control for the drive
This scheme is used to keep the flux in the motor constant irrespective of the speed or frequency of operation.
V/f Control
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 18
Comparison to obtain time durations
Once the time durations T1 and T2 are available and the sector number known, this information is sufficient to synthesize all the switch gate pulses using a PAL using combinational logic.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 19
Simulation results: Pole voltage at 30Hz.
• Voltage levels at 0.366kVdc, 1.0kVdc and 1.366kVdc are observed. • Each leg is clamped to the zero state for 30% of the total period.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 20
Phase voltage at 30Hz.
Simulation results
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 21
Pole voltage at 50Hz. (Simulation)
Voltage between pole A and negative bus of bottom-most DC-link
12-step mode is present, beginning of overmodulation.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 22
Phase voltage at 50Hz.
This shows the twelve step waveform, each space vector is active for 1/12th of the time period before the inverter outputs the next space vector.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 23
Experimental Setup
•The inverter topology was set up using IGBTs with their associated gate drives.
• DC links were produced by rectifying 3-phase transformer outputs.
•A digital signal processor(DSP), TMS320LF2407A produces the requisite PWM at its PWM output port, and also the sector number(4 bits) is an output
• Two PALs synthesize the gate pulses using the output of the DSP.
• Dead band circuits were used to provide adequate dead bands for the top and bottom IGBTs in a leg of the inverter.
• A 1.5KW, 50Hz three phase induction motor was used to test the inverter. The motor parameters are as below:
M: Magnetising inductance: 0.272 H Lrr: Total rotor inductance: 0.28 H Lss: Total stator inductance: 0.28 H Rs: Stator resisitance: 2.08 ohm Rr: Rotor resistance: 4.19 ohm Number of poles: 4
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 24
Fig. 1a: Phase voltage and motor current at 15Hz. (X-axis: 1div=20ms, Y-axis: Upper trace: 1div=50V, lower trace: 1div=1.5A)
Fig. 1b: Pole voltage at 15Hz. (X-axis: 1div=20ms, Y-axis: Upper trace: 1div=50V, lower trace= 1.5A)
Experimental Results
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 25
Fig. 2a: Phase voltage and motor current at 30Hz. (X-axis: 1div=10ms, Y-axis: Upper trace: 1div=50V,Lower trace: 1div= 2A)
Fig. 2b: Pole voltage and motor current at 30Hz.(X-axis: 1div=5ms, Y-axis: Upper trace: 1div=50V, lower trace: 1div=2A)
Experimental results: Phase and Pole voltages
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 26
Fig. 3a: Phase voltage and motor current at 45Hz.(X-axis: 1div=10ms, Y-axis: Upper trace: 1div=100V,Lower trace: 1div=2A)
Fig. 3b: Pole voltage at 45Hz. (X-axis: 1div=10ms, Y-axis: Upper trace: 1div=50V,Lower trace: 1div=2A)
Experimental results: Phase and Pole Voltages
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 27
Fig. 4a: Phase voltage and motor current at 50Hz.(X-axis: 1div=5ms, Y-axis: Upper trace: 1div=100V,Lower trace: 1div=1A)
Fig. 4b: Pole voltage at 50Hz.(X-axis: 1div=5ms, Y-axis: Upper trace: 1div=50V,Lower trace: 1div=2A)
Experimental results
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 28
Harmonics at 15Hz operation. (X-axis: nth harmonic, Y-axis: Relative amplitude)
• Note the absence of 5th and 7th and 6n±1, n=1, 3, 5,.. Harmonics
• 11th and 13th are highly suppressed
• Only 47th is prominent at 10% of fundamental
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 29
Harmonics in 30Hz operation (X-axis: nth harmonic, Y-axis: Relative amplitude)
• Only 35th and 37th and 47th and 49th harmonics can be seen.
• Motor current waveform will not be affected much by these harmonics.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 30
Harmonics in 45Hz operation. (X-axis: nth harmonic, Y-axis: Relative amplitude)
• 11th and 13th highly suppressed
• 23rd, 25th, 35th, 37th, 47th and 49th alone prominent.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 31
Harmonics in 50Hz operation. (X-axis: nth harmonic, Y-axis: Relative amplitude)
• 11th and 13th are about 10%
• 23rd and 25th about 5% others lower
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 32
Harmonics of phase voltage
0
10
20
30
40
50
0 20 40 60
Fundamental frequency of operation
% o
f am
plit
ud
e o
f fu
nd
amen
tal
11th
13th
23rd
25th
35th
37th
47th
49th
Trends in the Harmonics
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 33
Salient features
Complete elimination of the following harmonics:
5, 7 and 6n±1, n=1, 3, 5..
Current control is easier to implement as 5th and 7th are absent.
In the 12-step mode of operation the maximum value of the fundamental component achieved is 0.658Vdc against the value 0.637Vdc achieved in the conventional six-step mode of operation.
Linear range of modulation is 0.644Vdc, higher than 0.577Vdc in hexagonal space vector based inverter.
An inverter leg is switched off for 30% of the period, this reduces switch stress.
No need to open machine neutral, can feed from one side.
Twelve-sided polygonal voltage space vector based multi-level inverter for an
induction motor drive with common-mode voltage elimination
BySanjay Lakshminarayanan
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 35
Schematic of the proposed power circuit of the inverter fed IM drive
• An open-end induction machine is used.
• Two three–level inverters (cascading two two-level inverters) are used on either sides of the induction motor windings.
• Asymmetrical DC-links of the ratio 1:0.366 are required.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 36
Asymmetrical DC-link generation
Since 0.634=√3*0.366, Star-delta transformers may be arranged as shown to obtain the DC-link voltages.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 37
A phase
Pole voltage
Level S11 S21
1.366kVdc 2 1 1
0.366kVdc 1 0 1
0Vdc 0 0/1 0
Upper switches such as S11 and S14 require a voltage blocking capacity of 1.0kVdc while lower switches such as S21, S24 need a blocking capacity of 1.366kVdc.
Switch states and pole voltage levels in a leg
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 38
The “dashed” vectors such as OP, OQ, OE, OF, OI and OJ are from INV-A, the solid line vectors such as OR, OS, OG, OH, OK, OL are from INV-B.
Note: OP=OQ=1.225kVdc
Switching states from INV-A and INV-B and the resultant space phasors.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 39
OA is 1.366kVdc along A-axis, AQ is 0.366kVdc along B-axis and 0 kVdc along C axis, resultant vector is OQ belonging to INV-A.
OB is 1.366kVdc along negative C-axis, BR is 0.366kVdc along negative B-axis, 0 along a-axis, resultant is vector OR which is negative of the INV-B space vector.
Note: OP=OQ=1.225kVdc
Switching states from INV-A and INV-B and the resultant space phasors.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 40
Alternate vectors from INV-A( dashed line) and INV-B( solid line) are taken and added to get the resultant space vectors numbered 1 to 12 above.
Note: OP=OQ=1.225kVdc
• Vectors from INV-A and INV-B are added so that the common-mode voltage on both sides are the same.
Generation of 12-sided polygonal voltage space phasor with common-mode voltage elimination
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 41
12 polygonal space phasors are obtained with zero common-mode voltage variation.
Note: OP=OQ=1.225kVdc
2.OP.cos(300)=OR
OR=√3.OP
Space Vector Location
INV-A Levels
INV-B Levels
Zero Vectors in INV-A
Zero Vectors in INV-B
1 201 0’1’2’ 201 2’0’1’
2 210 1’0’2’ 210 2’1’0’
3 120 0’1’2’ 012 0’1’2’
4 021 1’0’2’ 102 1’0’2’
5 120 2’0’1’ 120 1’2’0’
6 021 2’1’0’ 021 0’2’1’
7 012 2’0’1’ 201 2’0’1’
8 102 2’1’0’ 210 2’1’0’
9 012 1’2’0’ 012 0’1’2’
10 102 0’2’1’ 102 1’0’2’
11 201 1’2’0’ 120 1’2’0’
12 210 0’2’1’ 021 0’2’1’
Generation of 12-sided polygonal voltage space phasor with common-mode voltage elimination
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 42
2.OP.cos(300)=OR
OR=√3.OP
The resultant space vector has magnitude OR=√3.OP, since OP=1.225kVdc we can find ‘k’ to make OR equal to Vdc as in hexagonal space vectors from a 2-level inverter. k=1/(1.225*√3)
k=0.471, so the upper DC-link voltage(1.0kVdc) is 0.471Vdc and the lower DC-link voltage(0.366kVdc) is 0.172Vdc.
This implies that lower voltage devices can be used for a given Vdc than in other schemes for generation of 12-sided polygonal space vectors.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 43
Space Vector Location
INV-A Levels
INV-B Levels
Zero Vectors in INV-A
Zero Vectors in INV-B
1 201 0’1’2’ 201 2’0’1’
2 210 1’0’2’ 210 2’1’0’
3 120 0’1’2’ 012 0’1’2’
4 021 1’0’2’ 102 1’0’2’
5 120 2’0’1’ 120 1’2’0’
6 021 2’1’0’ 021 0’2’1’
7 012 2’0’1’ 201 2’0’1’
8 102 2’1’0’ 210 2’1’0’
9 012 1’2’0’ 012 0’1’2’
10 102 0’2’1’ 102 1’0’2’
11 201 1’2’0’ 120 1’2’0’
12 210 0’2’1’ 021 0’2’1’
Summary of levels required in INV-A and INV-B to achieve the 12 space vectors
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 44
Common-mode voltage elimination
In any of the space vector locations from ‘1’ to ‘12’, the pole voltages in INV-A and INV-B, sum up to the same common-mode voltage
(1.366kVdc+0.366kVdc+0kVdc)/3
=(1.732/3)kVdc
The resultant common-mode voltage in the phase windings is zero
Space Vector Location
INV-A Levels
INV-B Levels
Zero Vectors in INV-A
Zero Vectors in INV-B
1 201 0’1’2’ 201 2’0’1’
2 210 1’0’2’ 210 2’1’0’
3 120 0’1’2’ 012 0’1’2’
4 021 1’0’2’ 102 1’0’2’
5 120 2’0’1’ 120 1’2’0’
6 021 2’1’0’ 021 0’2’1’
7 012 2’0’1’ 201 2’0’1’
8 102 2’1’0’ 210 2’1’0’
9 012 1’2’0’ 012 0’1’2’
10 102 0’2’1’ 102 1’0’2’
11 201 1’2’0’ 120 1’2’0’
12 210 0’2’1’ 021 0’2’1’
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 45
O P
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Hexagonal space vectors. 12-sided polygonal space vectors.
100
010
001
110
101
001
Maximum linear range of modulation for hexagonal space vectors: Cos(300).(2/3)Vdc=0.577Vdc
For 12-sided polygonal space vector:
Cos(150).(2/3)Vdc=0.644Vdc
Maximum value of the fundamental for hexagonal space vector: 2/πVdc=0.637Vdc.
For 12-sided polygonal space vector: 0.988.(2/3)Vdc=0.658Vdc.
Comparison of 12-sided space vector with hexagonal space vector
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 46
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Vr
If we have three sinusoidal reference voltages VA, VB and VC 1200 apart in time the resulting space vector Vr rotates around the origin.
Vr=VA + VB.ej2/3 + VC.ej4/3
Vr= V + j.Vβ
12-sided polygonal space vectors and a reference vector
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 47
0 0 0 01 2. (( 1).30 15 ) . ( .30 15 ) .( )ST V m T V m T V jV
0 0 0 01 2. ( 1).30 . .30 .( ).( 15 15 )ST V m T V m T V jV Cos jSin
0 0 0 01
2. . ( .30 15 ) . ( .30 15 )STT V Sin m V Cos m
V
0 0 0 02
2. . (( 1).30 15 ) . (( 1).30 15 )STT V Sin m V Cos m
V
0 0 0 01
2 3.. . ( .30 15 ) . ( .30 45 )S
B C
TT v Sin m v Cos m
V
0 0 0 02
2 3.. . (( 1).30 15 ) . (( 1).30 45 )S
B C
TT v Sin m v Cos m
V
Volt-sec balance equations
V: radius of polygon, m:sector number, TS is sampling period
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 48
0 01 2. ( 1)30 . 30 .( )ST V m T V m T V jV
0 01
0 02
sin( 30 ) cos( 30 )2
sin(( 1)30 ) cos(( 1)30 )S
VT m mTVT V m m
3 3( )
2 2A B CV v v v
3( )
2 B CV v v
Volt-sec balance equations
For the case when vector 1 is in line with -axis
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 49
Sector-1 Sector-2 Sector-3 Sector-4 Sector-5 Sector-6
T1
T2
Sector-7 Sector-8 Sector-9 Sector-10 Sector-11 Sector-12
T1
T2
3.S B
Tv
V
3.( )S
A B
Tv v
V 3
.S A
Tv
V
3.( )S
A C
Tv v
V
3.S C
Tv
V 3
.( )SB C
Tv v
V
3.( )S
B C
Tv v
V
3.S B
Tv
V3
.( )SB A
Tv v
V
3.S A
Tv
V 3
.( )SC A
Tv v
V
3.S C
Tv
V
3.S B
Tv
V
3.( )S
B A
Tv v
V
3.S A
Tv
V 3
.( )SC A
Tv v
V
3.S C
Tv
V3
.( )SC B
Tv v
V
3.( )S
C B
Tv v
V
3.S B
Tv
V 3
.( )SA B
Tv v
V
3.S A
Tv
V3
.( )SA C
Tv v
V
3.S C
Tv
V
Expressions for T1 and T2 in each sector
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 50
‘vA’ positive, and ‘(vB-vC )’ positive: 1st quadrant.
‘vA’ negative, and ‘(vB-vC)’ positive: 2nd quadrant.
‘vA’ negative, ‘(vB-vC)’ negative: 3rd quadrant.
‘vA’ positive, ‘(vB-vC)’ negative: 4th quadrant.
The quadrant in which the reference vector lies can be Found from the phase voltages as below-
Sector identification
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 51
If in quadrant 1:
If |VB-VC|<=|VA| then sector 1
else
If |VB-VC|<=3|VA| then sector 2
else sector 3 If in quadrant 2:If |VB-VC|<=|VA| then sector 6elseIf |VB-VC|<=3|VA| then sector 5
else sector 4
If in quadrant 3:If |VB-VC|<=|VA| then sector 7elseIf |VB-VC|<=3|VA| then sector 8
else sector 9
If in quadrant 4:If |VB-VC|<=|VA| then sector 12elseIf |VB-VC|<=3|VA| then sector 11
else sector 10
Sector identification
tan3.B C
A
v v
v
This is derived from the relation:
tanV
V
hence
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 52
Sampling Strategy for PWM
In order to reduce switching losses the switching frequency is kept low(~1000Hz) using the following sampling sheme:
0<f<=15Hz: 4 samples per sector15<f<=30Hz: 3 samples per sector30<f<=45Hz: 2 samples per sector45<f<=50Hz: 1 sample per sectorWhere f is the frequency of operation in Hz.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 53
Comparison to obtain time durations
Once the time durations T1 and T2 are available and the sector number known, this information is sufficient to synthesize all the switch gate pulses using a PAL using combinational logic.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 54
Pole voltages from INV-A and INV-B and phase voltage
Left: Pole voltages from INV-A and INV-B
Right : Phase voltage
(Simulation)
From simulation at 15Hz
Note that the upper inverter is on for only 50% duration in a cycle of operation.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 55
Simulation result
Left: Pole voltage from INV-A and INV-B
Right: Phase voltage
Simulation at 30Hz
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 56
Simulation results (45Hz)
Left: Pole voltages from INV-A and INV-B
Right: Phase voltage
Simulation at 45Hz
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 57
Pole voltage A from INV-A and pole voltage A’ from INV-B at 50Hz. (12-step mode of operation)
Phase voltage at 50Hz.
Simulation Results
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 58
Motor current with phase voltage (Simulation)
At 15Hz
At 30Hz
At 45Hz
At 50Hz
A dynamic model of an induction motor in Simulink was used to find the phase current of the motor.
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 59
(a) (b)
(a): INV-A pole voltage with common mode voltage variation, (b): Common mode voltage variation at inverter poles (simulation study)-30Hz
Simulation results
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(a) (b)
(a)-pole voltage variation with zero CMV(b): constant common mode voltage (Zero common mode voltage variation)
Simulation result-30Hz
Simulation results
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(a) (b)
(a):Upper and lower figure shows pole voltages of A and A’ at 30 Hz, (With zero common mode voltage variation). Middle trace-phase voltage obtained by the subtraction of pole voltages.
X-axis: 1div=10ms, y-axis: 1div=100V (experimental result), (b): relative harmonic amplitudes of the pole voltage showing the absence of triplen order at inverter poles
Experimental results
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(a) (b)
(a): Phase voltage, current (no load current) at 15Hz. x-axis: 1div=10ms, y-axis: upper trace: 1div=100V, lower trace: 1div=1A.-experimental result,
(b): Relative harmonic spectrum of phase voltage
Experimental result
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(a) (b)
(a): Phase voltage, current ( no load current) at 30Hz. X-axis: 1div =5ms, y-axis: upper trace: 1div=70V, lower trace: 1div=1A. -experimental result.
(b): Relative harmonic spectrum of phase voltage.
Experimental results
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(a) (b)
(a): Phase voltage, current and ( no load current) at 45Hz. X-axis: 1div =5ms, y-axis: upper trace: 1div=70V, lower trace : 1div=1A-experimental result.
(b): Relative harmonic spectrum of phase voltage
Experimental results
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(a) (b)
(a): Phase voltage and current ( no load current) at 50Hz. X-axis: 1div =5ms, y-axis: upper trace: 1div=70V, lower trace: 1div=1A (experimental result), (b): Relative harmonic spectrum of phase voltage.
Experimental results
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Fundamental and the harmonics for the complete speedRange ( triplen order and 6n ± 1, n= 1, 3, 5.. harmonics are absent)
Fundamental and Harmonics
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Salient features
The inverter topology was set up using IGBTs with their associated gate drives.
DC links were produced by rectifying 3-phase transformer outputs.
Complete elimination of the following harmonics:
5, 7 and 6n±1, n=1, 3, 5..
Current control is easier to implement as 5th and 7th are absent.
In the 12-step mode of operation the maximum value of the fundamental component achieved is 0.658Vdc against the value 0.637Vdc achieved in the conventional six-step mode of operation.
Linear range of modulation is 0.644Vdc, higher than 0.577Vdc in hexagonal space vector based inverter.
No common-mode voltage variation
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Experimental Setup
• A digital signal processor(DSP), TMS320LF2407A produces the requisite PWM at its PWM output port, and also the sector number(4 bits) is an output
• A FPGA synthesizes the gate pulses using the output of the DSP.
• Dead band circuits were used to provide adequate dead bands for the top and bottom IGBTs in a leg of the inverter.
• A 1.5KW, 50Hz three phase induction motor was used to test the inverter.
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Multilevel inverter with 18-sided polygonal voltage space vector locations for an open-end winding induction motor
drive By
SANJAY LAKSHMINARAYANAN
A Presentation
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Power circuit of the proposed inverter and Induction motor drive
When S21 and S31 are on, A’ is connected to 0.395Vdc
When S24 and S31 are on, A’ is connected to 0.258Vdc
When S34 is on, A’ is 0Vdc.
Switches in the same leg are operated complementary to each other
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18-sided polygonal voltage space vectors
Voltage space vectors from the two sides result in the 18 vectors shown above. Components along the A-axis, B-axis and C-axis add to form the vectors.
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Generation of vectors
Vector 1 results from connecting pole A to 0.742Vdc (B and C at 0Vdc), while A’ is 0Vdc and B’ and C’ are connected to 0.258Vdc
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Vector No. Pole A Pole B Pole C Pole A’ Pole B’ Pole C’
1 0.742Vdc 0 0 0 0.258Vdc 0.258Vdc
2 0.742Vdc 0 0 0 0 0.395Vdc
3 0.742Vdc 0.742Vdc 0 0 0.395Vdc 0.395Vdc
4 0.742Vdc 0.742Vdc 0 0 0 0.258Vdc
5 0.742Vdc 0.742Vdc 0 0.395Vdc 0 0.395Vdc
6 0 0.742Vdc 0 0 0 0.395Vdc
7 0 0.742Vdc 0 0.258Vdc 0 0.258Vdc
8 0 0.742Vdc 0 0.395Vdc 0 0
9 0 0.742Vdc 0.742Vdc 0.395Vdc 0 0.395Vdc
10 0 0.742Vdc 0.742Vdc 0.258Vdc 0 0
11 0 0.742Vdc 0.742Vdc 0.395Vdc 0.395Vdc 0
12 0 0 0.742Vdc 0.395Vdc 0 0
13 0 0 0.742Vdc 0.258Vdc 0.258Vdc 0
14 0 0 0.742Vdc 0 0.395Vdc 0
15 0.742Vdc 0 0.742Vdc 0.395Vdc 0.395Vdc 0
16 0.742Vdc 0 0.742Vdc 0 0.258Vdc 0
17 0.742Vdc 0 0.742Vdc 0 0.395Vdc 0.395Vdc
18 0.742Vdc 0 0 0 0.395Vdc 0
Inverter levels for generating 18-sided polygonal voltage space vectors
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Space vectors, sectors and reference space vectors
A reference vector is shown in sector 2, it can be realized by time averaging the vectors OE and OF. The averaging of the reference vector in the mth sector may be done using the formula below:
0 01 2( 1)20 20 ( )STV m T V m T V jV
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0 0 0 01 2.924* 3 * sin ( 20 30 ) cos ( 20 60 )
SB C
TT v m v m
V
0 0 0 0
2 2.924* 3 * sin (( 1) 20 30 ) cos (( 1) 20 60 )SB C
TT v m v m
V
Space vector PWM
The two vectors within which the reference vector lies, are turned on for T1 and T2 durations in one sampling period.
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0<f<=15Hz: 3 samples per sector
15Hz<f<=25Hz: 2 samples per sector
25Hz<f<=50Hz: 1 sample per sector
Sampling scheme
“f” is the operating frequency of the motor
This limits the switching frequency to 900Hz, thus
reducing the switching losses.
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‘Va’ positive, and ‘(Vb-Vc )’ positive: 1st quadrant.‘Va’ negative, and ‘(Vb-Vc)’ positive: 2nd quadrant.‘Va’ negative, ‘(Vb-Vc)’ negative: 3rd quadrant.‘Va’ positive, ‘(Vb-Vc)’ negative: 4th quadrant.If in quadrant 1:
If |Vb-Vc|<=|Va|.√3.tan200 then sector 1, else If |Vb-Vc|<=|Va|.√3.tan400 then sector 2, else If |Vb-Vc|<=|Va|.√3.tan600 then sector 3, elseIf |Vb-Vc|<=|Va|.√3.tan800 then sector 4, else sector 5.
Sector Identification
Similar logic in other quadrants, leads to sector identification
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Phase voltage at 15Hz.
Pole voltage of 3-level inverter (INV2&INV3) at 15Hz.
Motor current (No load) at 15Hz.
Harmonics in the phase voltage at 15Hz
Simulation results
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Phase voltage at 25Hz. Motor current at 25Hz.
Harmonics in the phase voltage at 25Hz.
Simulation results
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Phase voltage at 50 Hz.
Pole voltage of pole-A in INV1 at 50Hz.
Pole voltage of pole-A’, of 3-level inverter (INV2&INV3) at 50Hz.
Motor current at 50Hz.
Harmonics in the phase voltage at 50Hz
Simulation results
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Vector control model for Simulation
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Vector control (Simulation)
Speed response to 100 rad/sec command
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Speed reversal (-70 to +70 rad/sec)
Loading between 3 to 6 seconds
Vector control results
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Observations and Experimental Setup
IGBTs with isolated gate drives were used
DSP platform TMS320LF2407A was used
A 1.5kW open-end winding induction motor was used.
FPGA was used to generate gate pulses
Dead band circuit was used to switch complementary switches.
Harmonics 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 and 13 were seen to be eliminated.
Harmonics seen around switching frequency and multiples only.
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Waveforms at 15Hz. V/div=50V, Current: 1div=1A, t/div=10ms. 1st trace is pole voltage of 3-level inverter (INV2&INV3), 2nd trace is pole voltage of inverter INV1. 3rd trace is phase voltage. 4th trace is motor current.
Experimental verification
CEDT, INDIAN INSTITUTE OF SCIENCE, BANGALORE, INDIA 86
Waveforms at 25Hz. V/div=50V, current: 1div=1A, t/div=10ms. 1st trace is pole voltage of 3-level inverter (INV2&INV3), 2nd trace is pole voltage of inverter INV1. 3rd trace is phase voltage, 4th trace is motor current
Experimental verification
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Waveform at 50Hz. 1st trace: pole voltage of 3-level inverter (INV2&INV3), 2nd trace: pole voltage of inverter INV1, 3rd trace: Phase voltage, 4th trace: Motor current. V/div=50V, I/div=1A, t/div=5ms.
Experimental verification
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Transition to 18-step operation. 45Hz to 50Hz. Upper figure: Phase voltage,lower figure: Motor current. V/div=50V, Current/div=1A. Time/div=20ms.
Experimental results
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Acceleration from 5 Hz. Top waveform: Phase voltage, Bottom waveform: motor current.Time/div=500ms. V/div=50V, Current/div=1A
Deceleration to 5Hz. Upper figure: Phase voltage, lower figure: motor current.V/div=50V, Time/div=500ms, current/div=1A.
Experimental results
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Speed reversal, upper figure: Phase voltage lower figure: motor current. V/div=50V, Time/div=1s, current/div=1A.
Experimental Verification
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Conclusions
• A pole of INV1 is clamped to zero for 50% of the time period of one cycle of operation
• A pole of INV2 & INV3 is clamped to zero for 30% of the time period of one cycle of operation• 5th, 7th, 11th and 13th harmonics are completely eliminated from the phase voltage at any frequency of operation.
• Current waveform is smooth and sinusoidal even at low frequency.
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