mr. daniel perkins battelle memorial institute mr. rob riley air force research laboratory gateware...

Mr. Daniel Perkins

Battelle Memorial Institute

Mr. Rob Riley

Air Force Research Laboratory

Gateware Munitions Interface Processor (GMIP)

22004 MAPLD/116 Perkins and Riley

Outline

• Background & Objectives

• GMIP Architecture

• GMIP CONOPS

• Test & Demonstration

• Weapons Integration Toolkit Fusion

• Summary

32004 MAPLD/116 Perkins and Riley

Background and Objectives

• Background• Aircraft store integration complexity is a primary cost driver in the deployment of new munitions

• Reconfigurable computing provides a potential mitigation method for store integration complexity

• Program Scope/Objectives• Investigate use of FPGAs as a reconfigurable architecture to mitigate store integration complexity

• Provide a demonstration of this capability

42004 MAPLD/116 Perkins and Riley

GMIP Design Requirements

• MMSI & 1553 Intefaces

• Self reconfigurability

• Up to 8 independent FPGA loads

• Nonvolatile storage

• Fast large RAM storage for data intensive operations (DDR DRAM)

• Fast small RAM storage for simple interfacing (ZBT SRAM)

• External interfaces for expandability

• High current power supply for typical applications (6A @ 3.3V and 5V)

• Debug interface for development purposes

• PCI interface for development purposes

52004 MAPLD/116 Perkins and Riley

GMIP Component Design Details

• FPGA Selection

• Virtex II Pro 50 FPGA selected based on evaluation of potential GMIP applications.

• Virtex II Pro 50 Specs

– 23,616 Slices

– 232 Multiplier Blocks

– 232 18-KBit SelectRAM Blocks

– 8 Digital Clock Managers

– 852 IO Pads

– 2 PowerPC Hard-Cores

62004 MAPLD/116 Perkins and Riley

GMIP Component Design Details

• Memory Selection

– 128 MB DDR SDRAM selected based on the need for a large amount of fast, low cost memory storage

– 18 Mb ZBT SRAM selected based on the need for a small, fast, low latency and low cost memory storage that provides a simple interface implementation. ZBT SRAM is used specifically by the Condor 1553/MMSI Cores

– 16 MB Flash Memory selected based on the expected need to store and recall data between missions and FPGA context switches

• System ACE MPM Selection

– Provides an integrated solution for FPGA configuration/reconfiguration.

• MPM contains a Flash Memory for target FPGA bitstream storage, an FPGA for configuration/reconfiguration control and a PROM for the FPGA controller boot-up configuration

– Stores up to 8 FPGA designs that may be loaded at any time during the mission.

– Provides a simple interface for “self reconfiguration”

72004 MAPLD/116 Perkins and Riley

GMIP Component Design Details

• Interfaces

– MMSI

• 4 Independent EBR-1553 Interfaces

• 4 Independent CANBus Interfaces

– 1553

• 2 Independent 1553 Interfaces

– RS-232

• 1 RS-232 COM Port

– 64 Bit PCI Card Edge Interface

– 10/100 Ethernet Interface

– JTAG Interface for FPGA/System ACE Configuration and debug

– Auxiliary IO

• 287 2.5V Discrete IO

• 8 RocketIO Serial Channels

82004 MAPLD/116 Perkins and Riley

GMIP Architecture

Gateware Munitions Interface Processor

SignalBuffers

JTAG

PowerConversion &Distribution

Co

mm

un

ication

s Interface C

on

necto

rJT

AG

Co

nn

ector

FPGAReconfiguration

Controller

Co

nfig

uratio

nC

on

necto

r

FlashMemory

DDRSDRAM

StaticRAM

Xilinx FPGA

MIL-STD-1553XCVR (x2)

EBR-1553XCVR (x4)

CANbusXCVR (x4)

RS-232 XCVR

PCI Transceivers

address control data

PCI Connector

Gen

eral Pu

rpo

se I/O C

on

necto

rs

TX_PAD(2,4-9,11,14,16-21,23)

RX_PAD(2,4-9,11,14,16-21,23)

GEN_IO_C(1-24)

GEN_IO_A(1-119,122-140,143-187)

Power Connector

ReconfigurationClock Osc.

DDR SDRAMClock Osc.

SystemClock Osc.

XFMR

EthernetXCVR

XFMR

EthernetClock Osc.

GEN_IO_B(1-74)

92004 MAPLD/116 Perkins and Riley

GMIP CONOPSCarriage System Electronics

1553BUS

Current: Discrete Component Solution

MicrocontrollerW/

FLASH Mem (448KB)SRAM (26kb)

Two CAN Bus CtrlsTwo UARTsTwo ADCs

UTMC or DDC Mil-Std-1553B

RemoteTerminal

MCE

EBR-1553B

Bus Controller

FPGAA

B

EBR1553BUS

CAN BUS1

4K x 16Dual Port

SRAM

2MBSRAM

CAN BUS2

UART

2MBFlash Mem

PowerPC 405Hard Core

4K x 16Dual Port

SRAM

Ext. Mem Interface

Mil-Std-1553B

RemoteTerminal

IP

EBR-1553B

Bus Controller

IP

CAN ControllerIP

(1K Slices)

Application Specific Functions

A

B

1553BUS

EBR1553BUS

CANBUS

1Mil SystemGates

(5K Slices)

FLASH Memory(2MB)

Xilinx FPGA: XC2VP7-5FG456(456-pin BGA)(-40c to +100c)

SRAM(1MB)

ConfigurationFlash Mem

2MB

Interface

TIMER

INT. Controller

JTA

G

Watch DogTIMER

PL

L

UART IP(284 Slices)

** Shaded blocks are hard

embedded functions

4K x 16Dual Port

SRAM

Prog.ROM

SRAM

Proposed: Single FPGA (Virtex- II Pro) Solution

** Block represents a single Virtex-II Pro FPGA chip

102004 MAPLD/116 Perkins and Riley

GMIP CONOPSAvionics System Integration

Carriage System GMIP

Munition 1

GMIP

Munition n

GMIP

Munition 2

GMIP

* * * * *

Aircraft (host platform)

Fire ControlComputer

StoresManagement

Processor

GMIP

GMIP = Gateware Munition Interface Processor

112004 MAPLD/116 Perkins and Riley

GMIP CONOPSMission-Level Dynamic Reconfiguration

Mission Time

Phase 1 Phase 2 Phase 3

MMSI Remote Terminal Utility Processing

Elements

Control Datalink Image Datalink Utility Processing

Elements

Control Datalink Matched Filtering Utility Processing

Elements

FPGA Slices

FPGA Memory Blocks

External Memory

2400

5

64K SRAM

11779

24

2M SRAM

16054

10

2M SRAM

Reconfigure

Reconfigure

ResourceRequirements

Dynamic Reconfiguration Weapon’s Example

Captive Carry Flight To Target Area Loitering In Target Area

122004 MAPLD/116 Perkins and Riley

Demonstration #1 App X -- MIL-STD-1553B BC/Signal Filter #1

GMIP

Analog InterfaceDaughter Card

SignalGenerator

Oscilloscope

Analog

Analog

A/D

D/A

FPGA

SignalFilter

BusController

Application

1553 IPCore

1553XCVR

1553XFMR

MIL-STD-1553B Bus

F-16Programmable

DisplayProcessor

F-16PDP

Display

RS-232XCVR

Development PC

RS-232

MIL-STD-1553B

Bus Monitor

Analog

JTAG

132004 MAPLD/116 Perkins and Riley

F-16 PDP MIL-STD-1553 Data Bus Configuration

Fire Control Computer is the 1553 bus controller, GMIP is emulating this in demo #1

142004 MAPLD/116 Perkins and Riley

Demonstration #2: EBR-1553 Bus Controller/ Remote Terminal

GMIP #1

Analog InterfaceDaughter Card

SignalGenerator

Oscilloscope

A/D

D/A

FPGA

MMSIBC

Application

MMSIBC

Core

EBR-1553XCVR

RS-232XCVR

RS-232

GMIP #2

Analog InterfaceDaughter Card

A/D

D/A

FPGA

EBR-1553XCVR

RS-232XCVR

Analog

EBR-1553 Bus

JTAG

JTAG

Development PC #1

Development PC #2

RS-232

MMSIRT

Application

MMSIRT

Core

Analog

152004 MAPLD/116 Perkins and Riley

Demonstration #3: Dynamic Reconfiguration

GMIP

FPGA

BitstreamIdentification

Object

RS-232XCVR

Development PC

RS-232

JTAG

RCObject

System ACEMPM Select Map

SYS_RC

BIT_STR_SEL<2:0>

162004 MAPLD/116 Perkins and Riley

Summary

• Reconfigurable Munition Platform Interface Technology Enables Spiral Development

– Faster Fielding of Weapon/Platform Capabilities

– In-Field Upgrading

– Longer System Life

• Common Weapon/Platform Development and Support Environment

– Weapon Platform Integration Tool Kit

– CMBRE

• Next Steps

– New version of the board to

support VME/cPCI forms factors

– Enhanced demonstrations to

include SCA-compliant datalinks

– Research for integration of HighPerformance 1553 standard Gateware Munition Interface Processor (GMIP) board (v1)