microprocessors and microcontrollers · i2c bus protocol inter-integrated ... eg 18-11, write a...

Microprocessors And Microcontrollers

By: Dr. Attiya Baqai

Semester : 4th , 5th (TL, ES) Assistant Professor,

Course Code : ES256 , ES313 Department of

Electronics, MUET.

I2C bus protocol

◉ Inter-Integrated Circuit

◉ I2C or I2C

◉ For low-speed peripherals to motherboard or embedded system over short distance.

◉ Normal mode- 100kbps

◉ Fast mode-400kbps

◉ High Speed Mode-3.4 Mbps

I2C bus protocol

◉ Connection oriented communication with acknowledge

◉ 2 pins for data transfer (SCL & SDA)

◉ Two Wire Serial Interface (TWI)

◉ Master Slave approach with multi master option

◉ Addressing 7 bit or 10 bit unique addressing.

I2C vs SPI

I2C SPI

Requires only two lines Requires minimum four lines

Low speed Higher Speed

Half Duplex Full Duplex

Additional Signal select lines not

required if devices increase

Additional Signal select lines are

required as devices increase

More Power required Less Power required

Multi master can be used easily Multi master is difficult to implement

I2C BUS CONNECTION

I2C BUS CONNECTION

I2C BUS CONNECTION

I2C BUS CONNECTION

SDA

I2C devices modes

◉ Master Transmitter – initiates transfer sends data to slave device;

◉Master Receiver – initiates transfer reads data from slave device;

◉Slave Transmitter – waits for master request and then sends data;

◉Slave Receiver – waits for master transmission and accepts data.

I2C Start and stop conditions

SDA

SCL

SCL=0

SCL=1 SCL=1

I2C data transfer format

◉ START signal;

◉Address packet – seven address bits lead by data direction bit (read or write) + acknowledge bit;

◉Data packet – eight data bits + acknowledge bit;

◉STOP signal.

◉Acknowledge bit

I2C data transfer format

TWI registers

◉ TWBR (TWI Bitrate Register) To TWI Clock Frequency

◉TWSR (TWI Status Register)

◉TWCR (TWI Control Register)

◉TWDR (TWI Data Register)

TWBR (TWI Bitrate Register)

𝑇𝑊𝐵𝑅 =1

2𝑋4𝑇𝑊𝑃𝑆(𝐹𝑜𝑠𝑐

𝑆𝐶𝐿− 16)

◉ TWPS is in TWSR to set Pre-scaler

TWSR (TWI status register)

TWPS1 TWPS0 Decimal

value

Prescalar

value

0 0 0 1

0 1 1 4

1 0 2 16

1 1 3 64

; Prescalar value = 4 TWPS

Example 18-6

TWCR (TWI Control Register)

TWCR

TWDR (TWI Data Register)

◉ in Rx mode, last received byte will be in TWDR.

◉ In Tx mode, write next byte to TWDR to be transmitted.

◉ TWDR can only be accessed when TWIE=1 otherwise collision happens.

◉ TWDR cannot be initialized by user before 1st interrupt occurs.

Programming steps

◉ Set Frequency (TWBR & TWPS →TWSR)

◉ Enable TWI (TWEN→TWCR)

◉ Transmit START condition (TWEN, TWSTA, TWINT←1)

◉ Write Address (TWDR & TWCR)---SLA+R(1) or SLA+W(0)

◉ Address: b0=0// Write Operation;b0=1 // Read Operation

◉ Read/Write Data (TWDR & TWCR)

◉ Transmit STOP condition (TWCR)

To clear TWINT

and initiate

operation of TWI

Eg 18-11, write a program for master to write ob1111000 to a slave with address 0b1101000 at 50Khz Frequency

#include “avr/io.h”

int main(void)

{

TWSR=0x00;

TWBR=0x47;

TWCR=0x04;

TWCR |= (1<<TWSTA) | (1<< TWINT) | (1<<TWEN); // start TWI

TWDR=0xD0; // Address + Write(0)

TWCR |= (1<< TWINT) | (1<<TWEN);

while(TWCR & (1<<TWINT) == 0); // wait till tx completes

E.g 18-11, write a program for master to write ob11110000 to a slave with address 0b1101000 at 50Khz Frequency

TWDR=0xF0; // Data

TWCR |= (1<< TWINT) | (1<<TWEN);

while(TWCR & (1<<TWINT) == 0); // wait till tx completes

TWCR |= (1<< TWINT) | (1<<TWEN) | (1<<TWSTO); // Stop TWI

while(1);

return 0;

}

Eg 18-12, write a program for master to read a byte from slave with address 0b1101000 at 50Khz Frequency and display result at port A

#include “avr/io.h” int main() { DDRA=0xFF; TWSR=0x00; TWBR=0x47; TWCR=0x04; TWCR |= (1<<TWSTA) | (1<< TWINT) | (1<<TWEN);

Eg 18-12, write a program for master to read a byte from slave with address 0b1101000 at 50Khz Frequency and display result at port A

TWDR=0xD1; //Address + Read (1) TWCR |= (1<< TWINT) | (1<<TWEN); while(TWCR & (1<<TWINT) == 0); PORTA=TWDR; TWCR |= (1<< TWINT) | (1<<TWEN) | (1<<TWSTO); while(1); return 0; }

Multi byte Burst mode (Read / Write)

TWI Address Register (TWAR)

Slave operating mode

◉ must initialize TWI

◉ can not transmit START or STOP

◉ should listen to the bus and wait to be addressed by a master device or general call

Slave initialization

Listen to bus

Send Data

Receive Data

Any questions ?

Thanks!