mice data flow

MICE ReadoutMICE ReadoutDFPGADFPGAF’wareF’ware

Bowie K, Galagedera S, Halsall, Hart T, Kaplan D, Mellis M, Long K, Luebke W, C Bowie K, Galagedera S, Halsall, Hart T, Kaplan D, Mellis M, Long K, Luebke W, C Macwaters, Rubinov P & CollaborationMacwaters, Rubinov P & Collaboration

MICE Data Flow

VLPC

VLSB memory bank

AFE IIt board

Tracker

TriP-tPipeline

ADC

AFPGA

DFPGA

Serdes

COLEC

Detailed AFEllt data flow

2 x

DFPGA Interfaces

• Four DFPGAs/ AFEllt

• Four Interfaces

• 18 ns Clock period

DFPGA

D-A FPGA

SERDES

Trip-t

Collector

Disc 0 map

DIGEN0[ U/L/B]

Disc 3 map

16 bit

3 bit

3 bit

16 bit

JTAG

Clock

11 bit

(Disc bit map/ L1-Data readout) x 2

L1-Data readout

Mode2 bit

21 bit

DIGEN3[ U/L/B]

Busy

Trip-t Interface

DIGEN0[ U/L/B]

DIGEN3[ U/L/B]

TxFIFO-D

MapFIFO0LMSB

MapFIFO0UMSB

MapFIFO0ULSB

MapFIFO0LLSB

Disc 0 map 16 bit

MapFIFO3LMSB

MapFIFO3UMSB

MapFIFO3ULSB

MapFIFO3LLSB

MODE CTRL

U/LWrite

Trip-tInterface

D-A FPGAInterface

16 ->1Read

Select

8 bit

MUX

PRE-RST

Disc 3 map 16 bit

Trip-t Interface Timing

DIGENU

PRE-RST162ns

(9x18ns)

162ns(9x18ns)

DIGENL

DIGENB

18ns

18ns

18ns

D-A FPGA Interface

• 8 Bit Bi Directional Data

• 1 Write Enable (TxEF-D) from DFPGA to AFPGA.

• 1 Write Enable (TxEF-A) from AFPGA to DFPGA.

• 1 PRE_RST signal from AFPGA to DFPGA.

TxFIFO-D

RxFIFO-D

RxEF-D

TxFIFO-A

RxFIFO-A

RxEF-A

DFPGA

AFPGA

Disc-Vshare11 Bit

TxEF-D TxEF-A

Idle IdleData3

Datan

Chksum

TxEF-AorD

‘0’

‘1’

Data2

Data1

SERDES Interface

• 21 Bit SerdesFIFO output interfaces to its own Serdes.

• Input to SerdesFIFO come from #2 off RxFIFO-Ds.

• Bit Allocation

• 0 1/7th clock signal

• 1 – 8 Bit 0 to 7 of RxFIFO-D L1-data from AFPGA1

• 9 AFPGA1 L1-data sub-event frame signal

• 10 Free

• 11 - 18 Bit 0 to 7 of RxFIFO-D L1-data from AFPGA2

• 19 AFPGA1 L1-data sub-event frame signal

• 20 L1-data event frame signal to cover both AFPGA1 & AFPGA2

Collector Interface

• DFPGA code follow Run time commands issued by the grey coded 2 bit Collector mode command lines [mode 1:0].

• One Busy flag from DFPGA to Collector.

• The four Collector modes are

– Idle mode [mode 0:0] -Lower Busy

– Active mode [mode 0:1] -Lower Busy

– Digitise mode [mode 1:1] -Raise Busy

– Readout mode [mode 1:0] -Lower Busy

– Next expected valid modes are either the Idle or Active.

DFPGA Schematic (DF->AF single channel)

Dynamic Simulation

Dynamic Simulation- Data in

Dynamic Simulation- Data Out

MICE Readout DFPGA Firmware ProgressMICE Readout DFPGA Firmware Progress

• DoneDone– 2xTrip-t 2xTrip-t DFPGA DFPGA AFPGA (single channel) design simulated correctly with AFPGA (single channel) design simulated correctly with

static data.static data.– 2xTrip-t 2xTrip-t DFPGA DFPGA AFPGA (single channel) design simulated correctly with AFPGA (single channel) design simulated correctly with

dynamic data.dynamic data.– pins configured.pins configured.– 2xTrip-t 2xTrip-t DFPGA DFPGA AFPGA(single channel) back annotated design simulated AFPGA(single channel) back annotated design simulated

correctly with dynamic data.correctly with dynamic data.– Max operating frequency 66 MHz Max operating frequency 66 MHz

• UnderwayUnderway– Communications interfaceCommunications interface

• Next Next – TestTest– Implement L1 Data ReadoutImplement L1 Data Readout