metrics for reconfigurable architectures characterization: remanence and scalability

Metrics for Reconfigurable Architectures Characterization:

Remanence and Scalability

Pascal BENOITG. Sassatelli – L. Torres – D. Demigny M. Robert – G.

CambonName.Surname@lirmm.fr

Outline

Context Remanence Operative Density Case Study: the Systolic Ring Conclusion and perspectives

Context SoC and Customizable Platform Based-

Design

SpecificationsProcessing powerAreaPower consumptionetc.

ReconfigurableHardware

(Coarse Grain)ASIC 1

DSP Reconfigurabl

eHardware

(Fine Grain)

We need metrics to compare !

ASIC 2

ControllerCPU

RAMROM

ControllerCPU

RAMROM

Context Architecture characterization

• Processing power• Power consumption• Flexibility• Parallelism potential• Dynamism• Silicon area• Scalability• …

Metrics• Dehon criterion• Remanence• Operative density

Generalisation toArchitectural model

characterisation and metrics depend on architectural

parameters

« Comparing architectures with a minimum of criteria »

Remanence Definition

NPE: # of processing elements (PE) Nc: # of PE configurable per cycle

Fe: operating frequency Fc configuration frequency

Characterizes the Dynamism # of cycles to (re)configure the whole architecture

Amount of data to compute between 2 configurations

FcNcFeNR PE

Interconnection

PE PE PE PE PE

Configuration Memory

Processing Elements

Routing

Sequencing Unit

…inst3inst2inst1inst0Sequencer

Interconnection

PE PE PE PE PE

Processing Elements

Routing

Sequencing Unit

Remanence Comparisons

Only 1 cycle to (re)configure the DSP Few cycles to (re)configure coarse grain RA (8) Many cycles to (re)configure fine grain RA

NPE Nc RName Type F (MHz)

2304 0.14 16457

24 4 624 4 6

128 16 8

ARDOISE

Systolic RingDART

MorphoSys

TMS320C62

Fine Grain RA

Coarse Grain RA

DSP VLIW 8 8

200130

FcNcFeNR PE

Operative Density Definition

NPE: # of PE A: Core Area (relative unit ²)

Area can be expressed as a function of NPE (architectural model)

Characterizes Fixed NPE

• # of operators per relative area unit

Variable NPE• OD as a function of NPE

A(NPE) = NPE*APE+Ainterconnect(NPE)+Amemory(NPE) Asequencer(NPE)

• OD(NPE) = k A(NPE) =k.NPE the architectural model is scalable

PEPE NA

Interconnection

PE PE PE PE PE

Processing Elements

Routing

Sequencing Unit

Interconnection

PE PE PE PE PE

Processing Elements

Routing

Sequencing Unit

Operative Density Comparisons

DSP: sequencer area ARDOISE : fine granularity Coarse granularity Reconfigurable architectures

• Scalabilty of interconnect resources ?• Generalization to architectural models

)²2/)(()(²)(

µmWµmAMA

PEPE NA

Name Type Area(M²)

ARDOISE Fine Grain RA 26 12300 0.2

Systolic Ring (S=1, C=6, N=2) Coarse Grain RA 24 500 4.8

DART Coarse Grain RA 24 300 8.0

MorphoSys Coarse Grain RA 128 5500 2.3

TMS320C62 DSP VLIW 8 12300 0.1

Name Type NPEArea(M²) OD (NPE)

ARDOISE Fine Grain RA 26 12300 0.2

DART Coarse Grain RA 24 300 8.0

MorphoSys Coarse Grain RA 128 5500 2.3

TMS320C62 DSP VLIW 8 12300 0.1

Interconnection

PE PE PE PE PE

Processing Elements

Routing

Sequencing Unit

Interconnection

PE PE PE PE PE

Processing Elements

Routing

Sequencing Unit

-Architectural Model Characterization -

A Case Study:

The Systolic Ring

Architectural model Characterization The Systolic Ring

Architectural model Based on a coarse-grained

configurable PE

RegisterFile

ALU + MULT

IN 1 IN 2

RegisterFile

ALU + MULT

IN 1 IN 2

configurable PE Circular datapaths

Dnode Dnode

SwitchSwitc

Switch

configurable PE Circular datapaths 3 parameters

• C: # of layers• N: # of Dnodes per layer

Dnode Dnode

SwitchSwitc

Switch

layer 1

layer 2

layer 3

layer 4

# of layers : 4 (C = 4) # of Dnode per layer : 2 (N = 2)

• C: # of layers• N: # of Dnodes per layer

Switch

Dnode Dnode

hDnode

SwitchDnode

Dnode Dnode

Switch

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

hDnode

SwitchDnode

Dnode Dnode

Switch

Dnode Dnode

SwitchSwitchSw

SwitchSwitch

layer 1 layer 2

layer 3

layer 4

layer 5layer 6

layer 7

layer 8

• C: # of layers• N: # of Dnodes per layer• S: # of Rings

Switch

Dnode Dnode

hDnode

SwitchDnode

Dnode Dnode

Switch

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

hDnode

SwitchDnode

Dnode Dnode

Switch

Dnode Dnode

SwitchSwitchSw

SwitchSwitch

1 Systolic Ring (S = 1)

layer 1 layer 2

layer 3

layer 4

layer 5layer 6

layer 7

layer 8

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitc

Switch

Global Bus

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitchSw

SwitchSwitch

Dnode Dnode

SwitchSwitchSw

SwitchSwitch

Dnode Dnode

SwitchSwitchSw

SwitchSwitch

Dnode Dnode

SwitchSwitchSw

SwitchSwitch

Global Bus

4 Systolic Ring (S = 4)

Control Units• Local Dnodes units

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitc

Switch

Global Bus

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitchSw

SwitchSwitch

Dnode Dnode

SwitchSwitchSw

SwitchSwitch

Dnode Dnode

SwitchSwitchSw

SwitchSwitch

Dnode Dnode

SwitchSwitchSw

SwitchSwitch

Global Bus

Dnode Sequencer

Control Units• Local Dnode unit• Local Ring unit

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitc

Switch

Global Bus

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitchSw

SwitchSwitch

Dnode Dnode

SwitchSwitchSw

SwitchSwitch

Dnode Dnode

SwitchSwitchSw

SwitchSwitch

Dnode Dnode

SwitchSwitchSw

SwitchSwitch

Global Bus

Local RingSequencer

Control Units• Local Dnode unit• Local Ring unit• Global unit

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitc

Switch

Global Bus

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitc

Switch

Dnode Dnode

SwitchSwitchSw

SwitchSwitch

Dnode Dnode

SwitchSwitchSw

SwitchSwitch

Dnode Dnode

SwitchSwitchSw

SwitchSwitch

Dnode Dnode

SwitchSwitchSw

SwitchSwitch

Global Bus

Global Sequencer

Local RingSequencer

Architectural model Characterization Remanence

Only one Systolic Ring S=1 NPE = # of Dnodes = N*C*S = N*C

Remanence formalisation

• k= C/N

PEPE NkNR .)(

0 20 40 60 80 100 120 140 160 180 # Dnodes

REMANENCE

k = 2k = 4

0 20 40 60 80 100 120 140 160 180 # Dnodes

REMANENCE

k = 2k = 4

Architectural model Characterization A(NPE) formalisation for OD(NPE)

0.18µ CMOS technology

• C = 4, N = 2, S = 1

• A(8) = 3.3 mm ²

• A(8) = 407M ²

Area formalisation:

• A ( NPE ) = f ( N, C, S )

depends on C / N ratio and S

• NPE = N.C.S

Area formalisation calibrated on these results

Switch 1 Switch 2

Switch 3 Switch 4

N1,1 N1,2

N3,1 N3,2

N2,2N2,1

N4,1 N4,2

BN1 BN3 BN2 BN4

Switch 1 Switch 2

Switch 3 Switch 4

N1,1 N1,2

N3,1 N3,2

N2,2N2,1

N4,1 N4,2

BN1 BN3 BN2 BN4

Systolic Ring layout(C=4, N=2, S=1)

Architectural model Characterization OD(NPE) for 1 Systolic Ring (S=1)

k = C/N = [ 0.25 ; 4 ]

decreasing OD(NPE)

OD(NPE) for several Systolic Ring

k = C/N = 4

multi-ring instanciations increase

scalability

0 50 100 150 200 # Dnodes

Operative Density

C/N=0.5

C/N=0.25

0 50 100 150 200 # Dnodes

Operative Density

C/N=0.5

C/N=0.25

0 50 100 150 200 # Dnodes

Operative Density

1 Systolic Ring

2 Systolic Ring

4 Systolic Ring

8 Systolic Ring

0 50 100 150 200 # Dnodes

Operative Density

1 Systolic Ring

2 Systolic Ring

4 Systolic Ring

8 Systolic Ring

Architectural model Characterization Customisation and design technique

• between 60 and 80 processing elements

0 20 40 60 80 100 120 140

# Dnodes

Remanence

anence

0 20 40 60 80 100 120 140

# Dnodes

Remanence

anence

• between 60 and 80 processing elements

0 20 40 60 80 100 120 140

# Dnodes

Remanence

anence

0 20 40 60 80 100 120 140

# Dnodes

Remanence

anence

0 20 40 60 80 100 120 140

# Dnodes

Remanence

anence

0 20 40 60 80 100 120 140

# Dnodes

Remanence

anence

Design Space

Architectural model Characterization

0 20 40 60 80 100 120 140

# Dnodes

Remanence

anence

0 20 40 60 80 100 120 140

# Dnodes

Remanence

anence

Best OD and remanenceWorst interconnect resources and processing power

Design Space

0 20 40 60 80 100 120 140

# Dnodes

Remanence

anence

0 20 40 60 80 100 120 140

# Dnodes

Remanence

anence

Design Space

Worst OD and remanenceBest interconnect resources and processing power

0 20 40 60 80 100 120 140

# Dnodes

Remanence

anence

0 20 40 60 80 100 120 140

# Dnodes

Remanence

anence

R and OD can be integrated in CAD tools to observe architectural parameters effects and choose best trade-offs in the design space

R1 OD1 R2 OD2 R3 OD3 Rn ODn

Conclusion and perspectives

ControllerCPU

RAMROM

ControllerCPU

RAMROM

IP 2 IP 3 IP n

ControllerCPU

RAMROM

ControllerCPU

RAMROM

IP 2 IP 3 IP n

Architectural models

Comparisons

IP 2 IP 3 IP n

Architectural model

Customisation

ControllerCPU

RAMROM

IP 3N=4 C=8

ControllerCPU

RAMROM

IP 3N=4 C=8

Thank You

metrics for reconfigurable architectures characterization: remanence and scalability

coarse grain ra12876001

coarse grain ra245004

systolic ring s

dartcoarse grain ra243008

systolic ringconclusion

pe configurable

function of npe anpe

3tms320c62dsp vliw8123000

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