meg trigger system this short presentation describes the present status of the trigger algorithms of...

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mux PMT_MUX PMT_MUX cyclic memories PMT_FIFO PMT_FIFO INPMT_BLOCK

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MEG trigger system

This short presentation describes the present status of the trigger algorithms of the MEG experiment implemented on the Xilinx FPGA XCV812E. The project version is Ver.1 Rev.10 .

This project is designed by using the schematic entry of Xilinx software package “Foundation 4.1” .

The design is hierarchical. There are two top level schematics:• MEG2MAIN : it contains the data in/out buses and the

processing MACROs.• MEG2INT : it contains the control and interface signals as

well as the control and readout MACROs.

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