may 17, 20002 platform design considerations jim choate intel corporation
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May 17, 2000 2
Platform Design ConsiderationsPlatform Design Considerations
Jim ChoateJim Choate
Intel CorporationIntel Corporation
May 17, 2000 3
AgendaAgenda
GuidelinesGuidelines Measurement TechniquesMeasurement Techniques Early Testing ResultsEarly Testing Results SummarySummary
May 17, 2000 4
GuidelinesGuidelines
USB 2.0 guidelines will be more systematic, USB 2.0 guidelines will be more systematic, detailed than 1.x whitepapersdetailed than 1.x whitepapers
Proposed guideline areas:Proposed guideline areas:– Attenuation, jitter budgetsAttenuation, jitter budgets– Package/board/chassis designPackage/board/chassis design– EMI/EMC EMI/EMC – Use of test modes and testing for complianceUse of test modes and testing for compliance
May 17, 2000 5
Board DesignBoard Design
4 layer sufficient; trace impedance4 layer sufficient; trace impedancematching is keymatching is key
3 ns + 26 ns + 1 ns3 ns + 26 ns + 1 ns Avoid long runsAvoid long runs Do not cross plane splitsDo not cross plane splits Minimize viasMinimize vias Maximize distance to other tracesMaximize distance to other traces
Motherboard Is theToughest Environment
Motherboard Is theToughest Environment
May 17, 2000 6
Board Design GuidelinesBoard Design Guidelines
Board Stack-up:Board Stack-up:– 4 layer, impedance controlled boards required4 layer, impedance controlled boards required– Impedance targets must be specifiedImpedance targets must be specified– Ask your board vendor what they can achieveAsk your board vendor what they can achieve
Classic four-layer stackClassic four-layer stackSignal 1Signal 1
PrepregPrepreg
VCCVCCCoreCoreGroundGround
PrepregPrepreg
Signal 2Signal 2
Example target impedance:Example target impedance:0.005 in trace at 60+/-15%0.005 in trace at 60+/-15%7.5mil traces with 7.5mil7.5mil traces with 7.5milspacing Zdiffspacing Zdiff 90 90
May 17, 2000 7
Routing GuidelinesRouting Guidelines
Control trace widths to obtain target impedanceControl trace widths to obtain target impedance– Ask your board vendor what they can achieveAsk your board vendor what they can achieve– As always, cost is a considerationAs always, cost is a consideration
Maintain strict trace spacing controlMaintain strict trace spacing control Minimize stubsMinimize stubs
D-D-D-D-
D+D+D+D+
15k15k
15k15kCorrect way to connect to resistorsCorrect way to connect to resistors
May 17, 2000 8
Routing GuidelinesRouting Guidelines
Routing over plane splitsRouting over plane splits Creating stubs with test pointsCreating stubs with test points Violating trace spacing guidelinesViolating trace spacing guidelines
Common Routing MistakesCommon Routing Mistakes
Ground or power planeGround or power plane
tptpDon’t cross plane splitsDon’t cross plane splits
Proper routing technique Proper routing technique maintains spacing guidelinesmaintains spacing guidelines
May 17, 2000 9
Measurement TechniquesMeasurement Techniques
Selecting appropriate test equipmentSelecting appropriate test equipment– Accurate measurement of signal quality requires an Accurate measurement of signal quality requires an
oscope and probes with adequate BW and sample rateoscope and probes with adequate BW and sample rate
– Proper test fixtures are also importantProper test fixtures are also important
Equipment that will workEquipment that will workScope: TDS 694C - 10GS/s, 3GhzScope: TDS 694C - 10GS/s, 3GhzProbe: P6247 Fet Probe - 4Ghz, .4pF typProbe: P6247 Fet Probe - 4Ghz, .4pF typ
9090
Differential ProbeDifferential Probe
May 17, 2000 10
Board TestingBoard Testing
Use TDRs to verify adherence to budgetUse TDRs to verify adherence to budget– Typical TDR measurementTypical TDR measurement
Refer to section 7.1.6.2 of the specification for detailsRefer to section 7.1.6.2 of the specification for details
0.00E+00 2.00E-09 4.00E-09 6.00E-09 8.00E-09 1.00E-08 1.20E-08
time
imp
ed
an
ce
Connector Connector ReferenceReference
TimeTime
May 17, 2000 11
EMIEMI
USB1.X EMI solutions don’t work for USB2USB1.X EMI solutions don’t work for USB2– Low pass filters damage signal qualityLow pass filters damage signal quality
D+
D -
Vcc
USB AConnector
Typical USB 1.1 Termination SchemeTypical USB 1.1 Termination Scheme
May 17, 2000 12
EMIEMI
Proper grounding of chassis is crucialProper grounding of chassis is crucial– Connector shell must connect to green wireConnector shell must connect to green wire
ground early and wellground early and well– IO shield must connect securely to chassisIO shield must connect securely to chassis
and receptacleand receptacle 2 wire common mode choke is preferred2 wire common mode choke is preferred
– Blocks common mode EMI from leaving chassisBlocks common mode EMI from leaving chassis– Differential signal rolloff frequency should be highDifferential signal rolloff frequency should be high
May 17, 2000 13
ESD, EMCESD, EMC
ESD strikes spread out in time by inductanceESD strikes spread out in time by inductanceof cables and hubs in seriesof cables and hubs in series– Bypass/flyback caps on Vbus near connector helpBypass/flyback caps on Vbus near connector help
Hardware ProtectionHardware Protection– Well-grounded shield Well-grounded shield – 4 wire common mode choke4 wire common mode choke– Spark gap arrestorsSpark gap arrestors– Shielded cablesShielded cables
May 17, 2000 14
DP1DP1
DM1DM1
1.5 1.55 1.6 1.65 1.7 1.75 1.8 1.85 1.9
x 10-5
0
0.5
1
1.5
2
2.5
3
3.5
s
V
keyboard glitchkeyboard glitchkeyboard glitchkeyboard glitch
ESD, EMCESD, EMC
Differential squelch/disconnectDifferential squelch/disconnect Pattern matching before connectivityPattern matching before connectivity Sampling over extended times e.g. ChirpSampling over extended times e.g. Chirp
Noise Immunity Built IntoLow-Level Protocol
Noise Immunity Built IntoLow-Level Protocol
May 17, 2000 15
Early Testing ResultsEarly Testing ResultsUSB2 Validation Motherboard USB2 Validation Motherboard
Fron
t Pan
elFr
ont P
anel
Test ChipBack PanelBack Panel
Test ChipTest Chip
May 17, 2000 16
Routing Paths Tested Routing Paths Tested
USB ConnectorUSB Connector
Motherboard
PCI S
LOT
PCI S
LOT
LANLAN
PCI S
LOT
PCI S
LOT
PCI S
LOT
PCI S
LOT
PCI S
LOT
PCI S
LOT
South Bridge
NEC test chip
Long RouteLong Route
Front Panel HeaderFront Panel Header
Early Testing ResultsEarly Testing Results
Motherboard
PC
I S
LOT
LAN
PC
I S
LOT
PC
I S
LOT
PC
I S
LOT
South Bridge
USB ConnectorUSB Connector
Short RouteShort Route
NEC test chip
May 17, 2000 17
TP2 TP3
Early Testing ResultsEarly Testing Results
Back panel eye pattern resultsBack panel eye pattern results– EMI/ESD componentsEMI/ESD components– Both at A-connector (TP2) and at end of USB cable (TP3)Both at A-connector (TP2) and at end of USB cable (TP3)– Three-stack connector on MBThree-stack connector on MB
May 17, 2000 18
MotherboardMotherboard Front PanelDaughter Card
Front PanelDaughter Card
Board DesignBoard Design
Daughtercard at front/side panelDaughtercard at front/side panel– Bypass caps, EMI control components, strain reliefBypass caps, EMI control components, strain relief
Header and cableHeader and cable– Keyed header, cable of limited length andKeyed header, cable of limited length and
matched impedance matched impedance
Front/Side Panel ConnectorsFront/Side Panel Connectors
May 17, 2000 19
18” Shielded, twisted pair
18” ribbon cable
Early Testing ResultsEarly Testing Results
Front Panel Header Cable Options TestedFront Panel Header Cable Options Tested
May 17, 2000 20Shielded Front Panel CableShielded Front Panel Cable Ribbon Front Panel CableRibbon Front Panel Cable
Early Testing ResultsEarly Testing Results
Front-panel cable implementation eye pattern resultsFront-panel cable implementation eye pattern results– 18 inch, twisted pair, shielded front panel cable18 inch, twisted pair, shielded front panel cable– 18 inch unshielded front panel “ribbon” cable18 inch unshielded front panel “ribbon” cable
May 17, 2000 21
Early Testing ResultsEarly Testing Results
Front-panel cable implementation eye pattern resultsFront-panel cable implementation eye pattern results– 18 inch, twisted pair, shielded front panel cable18 inch, twisted pair, shielded front panel cable– 18 inch unshielded front panel “ribbon” cable18 inch unshielded front panel “ribbon” cable
80
72
Con
nect
or re
fere
nce 110
1.4 nsexception window
Shielded, Twisted PairShielded, Twisted PairFront Panel CableFront Panel Cable
114
145
114
RibbonRibbonFront Panel CableFront Panel Cable
Con
nect
or re
fere
nce
May 17, 2000 22
SummarySummary
USB 2.0 design presents new challengesUSB 2.0 design presents new challenges– Board layoutBoard layout– Common mode chokesCommon mode chokes– Chassis groundingChassis grounding– Signal Quality MeasurementSignal Quality Measurement– Compliance TestingCompliance Testing
USBIF will be providing design guidesUSBIF will be providing design guidesin such areasin such areas
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