may 17, 19992 usb semiconductor ip how to integrate usb into your design eric huang insilicon...
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May 17, 1999 2
USBSemiconductor
IPHow to Integrate
USB into Your Design
USBSemiconductor
IPHow to Integrate
USB into Your Design
Eric HuangEric HuanginSilicon CorporationinSilicon Corporation
May 17, 1999 3
Decision ProcessDecision Process
Do you need USB 2.0 functionality?Do you need USB 2.0 functionality? Integration approachesIntegration approaches
– Standard ProductStandard Product– Integrate Core into DesignIntegrate Core into Design
May 17, 1999 4
Implementation ChoicesImplementation Choices
Buy a Standard ProductBuy a Standard Product– An off-the-shelf chip or partAn off-the-shelf chip or part
Make it yourselfMake it yourself– Time & resources to develop USB 2.0Time & resources to develop USB 2.0
Buy a commercial core Buy a commercial core – Source USB 2.0 core from Semiconductor IP vendorSource USB 2.0 core from Semiconductor IP vendor
May 17, 1999 5
Approaches toUSB IntegrationApproaches toUSB Integration1) Buy a Standard Product1) Buy a Standard Product
May 17, 1999 6
USB Standard ChipsBlock DiagramUSB Standard ChipsBlock Diagram
USB Standard ChipUSB Standard ChipUSB Standard ChipUSB Standard ChipYourASICand
ApplicationLogic
YourASICand
ApplicationLogic
PPHHYY
PPHHYY
DMA or DMA or RAMRAM
DMA or DMA or RAMRAM
MCU orMCU orState MachineState Machine
MCU orMCU orState MachineState Machine
Fixed Fixed EndpointsEndpoints
Application
Application
Bus
Bus
May 17, 1999 7
USB Standard ProductAdvantagesUSB Standard ProductAdvantages
Off-the-shelf part for fast implementation Off-the-shelf part for fast implementation Software configurability of USB endpointsSoftware configurability of USB endpoints Basic or sample software includedBasic or sample software included Feature set is programmableFeature set is programmable
May 17, 1999 8
USB Standard Product CostsUSB Standard Product Costs
Not good for high volume productionNot good for high volume production– Several (3x-10x) times the cost of SIPSeveral (3x-10x) times the cost of SIP– Higher pin countHigher pin count– Can not shrink die size for cost reductionCan not shrink die size for cost reduction
May require two microcontrollers in a single designMay require two microcontrollers in a single design– 1 in the standard chip, 1 in the application1 in the standard chip, 1 in the application
Shifts burden to softwareShifts burden to software Basic software may require extensive adaptationBasic software may require extensive adaptation USB 2.0 requires more powerful microcontrollersUSB 2.0 requires more powerful microcontrollers
May 17, 1999 9
Approaches toUSB IntegrationApproaches toUSB Integration
2) Make It Yourself2) Make It Yourself
May 17, 1999 10
The Design is Coded,I’m DoneThe Design is Coded,I’m Done
Doing the design is easy …Doing the design is easy …– … … to guarantee it works in all systemsto guarantee it works in all systems
is 10x harderis 10x harder For risk reduction these factors areFor risk reduction these factors are
more importantmore important– VerificationVerification– ComplianceCompliance– InteroperabilityInteroperability
May 17, 1999 11
The Design is Coded,I’m DoneThe Design is Coded,I’m Done
Internally developed USB SIP may not guarantee Internally developed USB SIP may not guarantee interoperabilityinteroperability– Even implemented in silicon several timesEven implemented in silicon several times
Peripherals in production are the only true Peripherals in production are the only true measurement of interoperabilitymeasurement of interoperability– Millions shipped defines interoperabilityMillions shipped defines interoperability
ContinuedContinued
May 17, 1999 12
Magnitude of EffortMagnitude of Effort
Many components neededMany components needed– CoreCore– Test EnvironmentTest Environment– VerificationVerification– InteroperabilityInteroperability
For ExampleFor Example– USB 1.1 investment 50 man yearsUSB 1.1 investment 50 man years– USB 2.0 investment to date 3+ man yearsUSB 2.0 investment to date 3+ man years
May 17, 1999 13
What Is at Stake?What Is at Stake?
Design delaysDesign delays– Incomplete product, inadequate support,Incomplete product, inadequate support,
poor documentationpoor documentation Product respinsProduct respins
– ASIC mask sets cost over $300KASIC mask sets cost over $300K– Months of delayMonths of delay
System incompatibilitySystem incompatibility– Product returns, reworkProduct returns, rework
Risk market position and profitsRisk market position and profits Millions of dollars at riskMillions of dollars at risk
– High stakes dictate focus on risk reductionHigh stakes dictate focus on risk reduction
May 17, 1999 14
Approaches toUSB IntegrationApproaches toUSB Integration3) Buy a Commercial Core3) Buy a Commercial Core
May 17, 1999 15
What Is USB SIP?What Is USB SIP?
SIP stands for “Semiconductor Intellectual SIP stands for “Semiconductor Intellectual Property”Property”
Digital Synthesizeable design:Digital Synthesizeable design:– RTL Source Code in Verilog or VHDLRTL Source Code in Verilog or VHDL– Process IndependentProcess Independent– Adds the USB functionality to designAdds the USB functionality to design– Easily integrates into ASIC / ASSP / FPGAEasily integrates into ASIC / ASSP / FPGA
May 17, 1999 16
USB Core Block DiagramUSB Core Block Diagram
Your Integrated ASICYour Integrated ASICYour Integrated ASICYour Integrated ASICCoreCore
PPHHYY
PPHHYY
DMADMADMADMA
StateStateMachineMachine
StateStateMachineMachine
Endpoints & AlternatesEndpoints & Alternates
Application B
usA
pplication Bus
YourYourAppApp
LogicLogic
YourYourAppApp
LogicLogic
Your Integrated ASICYour Integrated ASICYour Integrated ASICYour Integrated ASIC
CoreCorePPHHYY
PPHHYY
DMADMADMADMA
StateStateMachineMachine
StateStateMachineMachine
YourYourAppApp
LogicLogic
YourYourAppApp
LogicLogic
May 17, 1999 17
Why USB SIP?Why USB SIP?
High volume, low cost solutionHigh volume, low cost solution Risk reduction with reusable coresRisk reduction with reusable cores Focus your best resources on new features that Focus your best resources on new features that
differentiate your productdifferentiate your product Leverage and use USB SIP from a USB expertLeverage and use USB SIP from a USB expert
– SIP vendors support many customersSIP vendors support many customers– Speed your time to marketSpeed your time to market– Keep pace with evolving USB standardsKeep pace with evolving USB standards– Ensure interoperability in a changing environmentEnsure interoperability in a changing environment
May 17, 1999 18
USB Core AdvantagesUSB Core Advantages
Endpoint ConfigurabilityEndpoint Configurability– Windows programs class drivers to selectWindows programs class drivers to select
endpoint alternatesendpoint alternates– Offers flexibility in the use of the final productOffers flexibility in the use of the final product
Eliminates the need for a microprocessorEliminates the need for a microprocessor PerformancePerformance
– ThroughputThroughput– LatencyLatency
Easier path to cost reduction:Easier path to cost reduction:– Include in a system on a chip designInclude in a system on a chip design– Shrink die size with a USB CoreShrink die size with a USB Core
May 17, 1999 19
USB Core ConcernsUSB Core Concerns
Discipline needed in design processDiscipline needed in design process Can not change endpoints after fabricationCan not change endpoints after fabrication Requires commitment in product featuresRequires commitment in product features Is the core fully asychronous?Is the core fully asychronous? Is the core scannable?Is the core scannable?
May 17, 1999 21
InteroperabilityInteroperability
Component levelComponent level– USB core integrates easily to any on-chip bus USB core integrates easily to any on-chip bus
(proprietary or standard)(proprietary or standard)– USB core connects easily to any standard Phy (UTMI)USB core connects easily to any standard Phy (UTMI)– USB core uses a standard interface for connecting to USB core uses a standard interface for connecting to
any on-chip busany on-chip bus– Independent of process flow or compilation toolsIndependent of process flow or compilation tools
System levelSystem level– USB peripheral will connect to any USB compliant PCUSB peripheral will connect to any USB compliant PC
May 17, 1999 22
Verification and ComplianceVerification and Compliance
Build test vectors for corner casesBuild test vectors for corner cases– Test for abnormal signaling conditionsTest for abnormal signaling conditions– Test for response to non-compliant activityTest for response to non-compliant activity
Build test vectors for complianceBuild test vectors for compliance– USB 1.1USB 1.1– USB 2.0USB 2.0– Test under minimal loadingTest under minimal loading– Test with many different USB configurationsTest with many different USB configurations
Update verification suite as standard evolvesUpdate verification suite as standard evolves
May 17, 1999 23
Market ProvenMarket Proven
Proven in FPGAsProven in FPGAs Proven in SiliconProven in Silicon
– Proven in standard productsProven in standard products– Proven in many processesProven in many processes
USB Plugfest interoperability testedUSB Plugfest interoperability tested Core integrated in many designsCore integrated in many designs
– Cameras, Printers, Scanners, Modems…Cameras, Printers, Scanners, Modems… Systems in volume reductionSystems in volume reduction Leadership and expertise in creating standardsLeadership and expertise in creating standards
– Adapts cores to an evolving standardAdapts cores to an evolving standard– Vendor updates cores as the standard changesVendor updates cores as the standard changes
May 17, 1999 24
ConfigurabilityConfigurability
Device core implemented in many configurationsDevice core implemented in many configurations– Control, Interrupt, Bulk, and Isochronous pipelines Control, Interrupt, Bulk, and Isochronous pipelines
exercised extensivelyexercised extensively– Endpoints implemented in many combinationsEndpoints implemented in many combinations
of interfaces and alternatesof interfaces and alternates– Implemented in different processesImplemented in different processes
Configurable cores save design & test timeConfigurable cores save design & test time Reduces riskReduces risk
May 17, 1999 25
There’s More to USB SIPThan Just Having a CoreThere’s More to USB SIPThan Just Having a Core
Great test environmentGreat test environment Easy, sensible configurabilityEasy, sensible configurability TrainingTraining SupportSupport
– Well-documented CoresWell-documented Cores– Documentation for reuseDocumentation for reuse– Dedicated USB supportDedicated USB support– Experienced USB development engineersExperienced USB development engineers
May 17, 1999 26
Standards ChecklistStandards Checklist
Proven USB 2.0 ComplianceProven USB 2.0 Compliance Proven USB 1.1 ComplianceProven USB 1.1 Compliance Standard interface to USB Transceiver (e.g. UTMI)Standard interface to USB Transceiver (e.g. UTMI)
– UTMI for USB 2.0UTMI for USB 2.0 Standard interface to an on chip bus (e.g. VCI)Standard interface to an on chip bus (e.g. VCI) Tool independenceTool independence
May 17, 1999 27
Questions to AskQuestions to Ask
How many times has your USB SIP productHow many times has your USB SIP productbeen used?been used?
Is USB SIP your main line of business?Is USB SIP your main line of business? Does your USB SIP use standard interfaces?Does your USB SIP use standard interfaces?
– Does your USB 2.0 core have UTMI?Does your USB 2.0 core have UTMI?– Does your USB core have a VC interface (VCI)?Does your USB core have a VC interface (VCI)?
Can your USB core interface to any on-chip bus?Can your USB core interface to any on-chip bus?
May 17, 1999 28
Questions to AskQuestions to Ask
What kind of post-sales support do you have?What kind of post-sales support do you have? Are your USB engineers dedicated to USB SIP?Are your USB engineers dedicated to USB SIP? Did you develop your USB SIP in-house?Did you develop your USB SIP in-house? Do you provide source code?Do you provide source code? What kind of test environment do you provide?What kind of test environment do you provide?
ContinuedContinued
May 17, 1999 29
inSiliconThe USB SIP Market LeaderinSiliconThe USB SIP Market Leader
Proven in Silicon – Over 100 customersProven in Silicon – Over 100 customersand designsand designs
Interoperability – Millions of units shippedInteroperability – Millions of units shipped CompletenessCompleteness
– Test Environment, Core, and SoftwareTest Environment, Core, and Software SupportSupport
– Expert, focused, availableExpert, focused, available– Configurable - RapidscriptConfigurable - Rapidscript
May 17, 1999 30
inSiliconThe USB SIP Market LeaderinSiliconThe USB SIP Market Leader
Verification and ComplianceVerification and Compliance Standards BasedStandards Based
– UTMI for USB 2.0UTMI for USB 2.0– VCI to interface to any bus or applicationVCI to interface to any bus or application– Independent of process, foundry, & toolsIndependent of process, foundry, & tools
ContinuedContinued
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