lpddr3 and lpddr4 - jedec
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LPDDR3 and LPDDR4: How Low-Power DRAM Can Be Used in High-Bandwidth Applicationsin High-Bandwidth Applications
Mobile Forum 2013
Marc Greenberg
Director, Product Marketing
Synopsys
Copyright © 2013 Synopsys
AgendaAgenda
• High-Bandwidth, Low-Power DRAM Today
• Using “Dual Personality” Memories Effectively to Reduce Power Consumption
• System Environment Around LPDDR Devices
• Future Direction
High Bandwidth TodayHigh Bandwidth Today
• Shipping Application Processors
– Up to 4 channel LPDDR2
– 2 channel LPDDR3-1600
• LPDDR3 in mass production per • LPDDR3 in mass production per manufacturer websites
– One and two channel LPDDR3-1600 up to 4 die package with 4Gbit density
• Early access status for LPDDR3-2133 speedsSources: http://www.samsung.com/us/business/oem-solutions/pdfs/PSG_2H_2012.pdfhttp://www.hynix.com/inc/pdfDownload.jsp?path=/datasheet/Databook/Databook_1Q'2013_MobileMemory.pdfhttp://www.samsung.com/global/business/semiconductor/minisite/Exynos/news_19.html
20
30
40
50
60
70 Today’s requirements
Today’s low-powerDRAM devices
GByte/secpeak bandwidth
Potential future low-powerDRAM devices
How Potential Future Devices CompareHow Potential Future Devices Compare
0
10
* No published JEDEC standard exists. Standard publication is dependent on JEDEC process. Specification or performance is subject to change without notice. Part availability dependent on manufacturer.
*
HighHigh--Bandwidth Interface ExamplesBandwidth Interface Examples
• PCI Express Gen3
– 1GB/s (8Gb/s)
• USB3.0
– 0.625GB/s (5Gb/s)
• HDMI 1.4 (4k)
– 1GB/s (8Gb/s)
• LPDDR4
– 4.2Gb/s parallel
– No embedded clock
– 14GB/s/channel
What is Low Power?What is Low Power?
• Laptop with a 90 Watt-hour battery?
• Tablet with a 40 Watt-hour battery?
• Phone with a 5-10 Watt-hour battery?• Phone with a 5-10 Watt-hour battery?
Reducing Power in DRAMReducing Power in DRAM
• DRAM core power usage
– Generally a function of device organization, usage, manufacturing technology
• Standby power• Standby power
– Available features for controlling power
• IO signaling power
– Function of voltage swing, termination, IO capacitance, frequency, load, …
• Power dependent on energy per bit (TBD) and system configuration
Let’s Call Let’s Call IIt “Less Power”t “Less Power”
• 3mW/Gbps (3pJ/bit) is a great figure of merit but…
Energy per Bit
(pJ/bit =
mW/Gbit/sec)
2-channel
LPDDR4
3200
2-channel
LPDDR4
4266
4-channel
LPDDR4
3200
4-Channel
LPDDR4
4266
Not including: Memory core power, address/control bus, PHY power,
memory controller power… or any computation that the target system
might be doing… operating the display… accessing the net… etc.
merit but…mW/Gbit/sec) 3200 4266 3200 4266
1 205mW 273mW 410mW 546mW
2 410mW 546mW 819mW 1.09W
5 1.02W 1.37W 2.05W 2.73W
10 2.05W 2.73W 4.10W 5.46W
Low Power Low Power MMeets High Bandwidtheets High Bandwidth
• “Multiple personality” devices
– Low power, low bandwidth mode
– Extensive standby modes
– Infrequent full bandwidth usage– Infrequent full bandwidth usage
Normal OperationNormal Operation
• Low-speed operation
–< DDR1600, unterminated
–Using all LPDDR power reduction –Using all LPDDR power reduction capabilities when idle
When Can You When Can You GGo o FFull ull SSpeed?peed?
• When plugged in
• During time-bound occasional operations operations
–Boot
–Program launch
– Image/video processing
• Intermittently…
Requirements to run full speedRequirements to run full speed
• Available power
• Sufficient cooling
• Fully Trained interface• Fully Trained interface
• On-Die Termination
• Temperature Monitoring
• Memory controller and PHY in high-speed mode
Termination Termination -- HighHigh--Speed ModeSpeed Mode
510ps620ps 320ps
• 28nm silicon results
– Data eye measured at Write ball
– Wirebond package
– Worst case SSO
LPDDR2-1066
UnterminatedDDR3-1600
Terminated
LPDDR3-1600
Unterminated
Source: Synopsys
Finding the Ideal PCB EnvironmentFinding the Ideal PCB Environment
• PoP provides very short electrical connection forconnection forhigh speed andlow power
– But power dissipation limited
Finding the Ideal PCB EnvironmentFinding the Ideal PCB Environment
• Another option: Clamshell
–Used in Synopsys characterization
–Seen in at least one tablet–Seen in at least one tablet
Top side Bottom side
PCB
Application Processor
DRAM
Schematic side view
Memory Partitioning ConceptMemory Partitioning Concept
Channel 1 Rank 0
High Resolution
Video Processing,
Image Processing,
etc
Channel 0 Rank 0
Modem, OS
Kernel, Running
apps
Maximum
bandwidth
All chips active
Channel 1 Rank 1
High Resolution Video
Processing, Image
Processing, etc
Channel 0 Rank 1
Stalled/Sleeping Apps
Channel 0 Channel 1Application
Processor
Memory Partitioning ConceptMemory Partitioning Concept
Channel 1 Rank 0
High Resolution
Video Processing,
Image Processing,
etc
Channel 0 Rank 0
Modem, OS
Kernel, Running
apps
No video
Running apps
Ch0 active
Channel 1 Rank 1
High Resolution Video
Processing, Image
Processing, etc
Channel 0 Rank 1
Stalled/Sleeping Apps
Channel 0 Channel 1Application
Processor
Memory Partitioning ConceptMemory Partitioning Concept
Channel 0 Rank 0
Modem, OS
Kernel, Running
apps
No video
Low activity
Ch0 R1 active
Channel 1 Rank 0
High Resolution
Video Processing,
Image Processing,
etc
Channel 0 Rank 1
Stalled/Sleeping Apps
Channel 1Application
ProcessorChannel 0
Channel 1 Rank 1
High Resolution Video
Processing, Image
Processing, etc
Memory Partitioning ConceptMemory Partitioning Concept
Channel 0 Rank 0
Modem, OS
Kernel, Running
apps
Basic “keep
alive” AOACLow frequency
Ch0 R1 active
Channel 1 Rank 0
High Resolution
Video Processing,
Image Processing,
etc
Channel 0 Rank 1
Stalled/Sleeping Apps
Channel 0 Channel 1Application
Processor
Channel 1 Rank 1
High Resolution Video
Processing, Image
Processing, etc
Memory Partitioning ConceptMemory Partitioning Concept
Channel 0 Rank 0
Modem, OS
Kernel, Running
apps
Complete standby
Channel 1 Rank 0
High Resolution
Video Processing,
Image Processing,
etc
Channel 0
Channel 0 Rank 1
Stalled/Sleeping Apps
Channel 1
Channel 1 Rank 1
High Resolution Video
Processing, Image
Processing, etc
Application
Processor
Summary of LowSummary of Low--Power DRAM Power DRAM Interface TechniquesInterface Techniques
• Select a low-power DRAM
• Use DRAM low-power features
• Frequency scaling
– Switching termination on/off– Switching termination on/off
• DRAM clock gating
• Partitioning memory into DRAM
• On-chip power control for AP
– Clock gating, power gating (esp. DDR IOs), DVFS
– Etc…
20
30
40
50
60
70 Today’s requirements
Today’s low-powerDRAM devices
GByte/secpeak bandwidth
Potential future low-powerDRAM devices
How Potential Future Devices CompareHow Potential Future Devices Compare
0
10
* No published JEDEC standard exists. Standard publication is dependent on JEDEC process. Specification or performance is subject to change without notice. Part availability dependent on manufacturer.
*
ConclusionsConclusions
• Future DRAM bandwidth will continue to increase
• Power is reduced in LPDDR4, but still proportional to bandwidthproportional to bandwidth
• Use multiple techniques to meet performance and power goals of high-bandwidth low-power DRAM
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