low voltage power supplies i.placement ii.size iii.power consumption iv.cabling v.regulators board...

Low Voltage Power SuppliesI. PlacementII. SizeIII. Power consumptionIV. CablingV. Regulators board blocsVI. Component selectionVII. SchematicsVIII. FirmwareIX. Prototype designX. Schedule

February 2005 – Barcelona

I. Placement

At pannels with less MAPMT.

27 VFE maximum per 2 power supplies. 14 VFE maximum per regulators board.

Regulator board divided in two to reduce power consumption per regulator board, so7 VFE maximum per regulators board.

TOTAL of 16 Regulator Boards to be produced.

II. Size

Power supplies

Max: 476x670mm2

III. Power consumption

Consumption VFE: +1’65A = 1408 mA - 1’65A = 1280 mA +1’65D = 604 mA - 1’65D = 604 mA + 3’3A = 256 mA + 3’3D = 300 mA

With a maximum of 1’5A per regulator the number of regulators per box are;-14 regulators +1’65A (7 per board)-14 regulators –1’65A (7 per board)-7 regulators +1’65D (3 per board)-7 regulators –1’65D (3 per board)-3 regulators +3’3A (1 per board)-3 regulators +3’3D (2 per board)An other regulator for FPGA and electronics consumption.

Maximum voltage drop per regulator of 1’5V.Voltage of power supplies may be of +4’8V, +3’15V, -3’15V. In this conditions and with a current of 1’5A every regulator, the total power consumption is; -31’5W in +1’65 regulators-31’5W in –1’65 regulators-13’5W in +3’3 regulators-TOTAL 76’5W!!! Each box

Monitoring of voltage, current, and board temperature using a ProASIC FPGA with ADC and inputs multiplexed.

IV. Cabling

Using voltages of +4’8V, +3’15V, -3’15V distribution should be:

Power supplies

+3’15 V

4-5 ch

-3’15 V

5 ch

+4’8 V

1-2 ch

REGULATORS

to +1’65V

to -1’65Vto GND

to +3’3V

200 A

50 A

V. Regulator Board Blocs

Positive

Regulators

Negative

Regulators

OpAmp

Amplification

OpAmp

CM change

Current measurement throug FUSE

Voltage measurement

NTC Resistors

Wheatstone Bridge

MUX

Outer temperature sensors

A/D

FPGA

Tra

nsce

iver

s I2CLVDS

Inhibit control

OpAmp

CM change

Vref

Vsub

VI. Component selection

-APA 150 FPGA (TQ100) for its flexibility in design (flash) , easy to solder (not BGA). Not as much radiation hard as Axcelerators.

-AD9203 10bits ADC, 40Msamples/s, 5 level depth pipeline, radiation hard.

-MAX4581 octal analog multiplexers, low resistance, radiation hard.

-DS92LV010 bidirectional CMOS/LVDS transceiver, radiation hard.

-BFT93, PNP high frecuency transistor, radiation hard.

-100mOhms fast fuses being used as Shunt resistors for current monitoring.

-TLV2462 dual package rail-to-rail opamps, radiation hard.

-L4913, L7913, Low Drop Out 3A adjustable voltage regulators, radiation hard.

-Normal crystal oscillator (JCO14-3-B40.0MHz). Radiation hardness?? (Alice tests of comercial oscillators, no problems with 100krad).

VII. Schematics I. Positive regulators

-L4913-Protection diode at output.-Local voltage monitoring.-Fuse used as shunt for current measurement.-Led indicator of inhibit state.

2k5 R13

68'12000

7501.225,1

13

191.

V

R

RVV ADJO

VII. Schematics II. Negative regulators

-L7913-Protection diode at output.-Local voltage monitoring.-Fuse used as shunt for current measurement (at output for a low CM).-Led indicator of inhibit state.

2k5 R13

68'12000

7501.225,1

117

1231.

V

R

RVV ADJO

VII. Schematics III. Positive current sensing

-Differential amplifier.-Gain 20. Over 100mOhms; 1V = 1A.-CM input from GND to 3’3V.-Output max= 2V for ADC.

VII. Schematics IV. Negative current sensing

-Differential amplifier.-Gain 20. Over 100mOhms; 1V = 1A.-CM input from -1’65V to 1’65V.-Output max= 2V for ADC.-Output min= GND.

VII. Schematics V. MUX

- 8 to 1 analog MUX.-If chip not enabled output in High Z mode.-Control via enable and ABC inputs.-ABC in paralel for all MUX.-ADC_IN in paralel for all MUX.

VII. Schematics VI. FPGA

-Hardware RESET.-6 bit I2C selection.-Independent Clock.

VII. Schematics VII. FPGA power start-up delay

-ACTEL notes recommend first power Input core and then output buffers. This is done with a delay in INHIBIT pin of regulators.-Delay dependent with RC constant.-Permits FPGA control of Inhibit.

VII. Schematics VIII. I2C hardware

-Differential I2C with SDA direction control.-By default receiving data (I2C slave).- Double connector for bus calbing.

VIII. Firmware. FPGA Blocs.

Combinational bloc 1

Clock division to ADC.

MUX control.

RAM blocs

Samples

Status registers

Channel limits

ADC samples

Idle until I2C command. R/W registers.

Combinational bloc 2

Check samples

Combinational bloc 3

Inhibit update from Status registers

Tripple voting

Combinational bloc 4

I2C FSM.

IX. Prototype design

-282x85mm2-6 layer pcb, GND, +3’15, -3’15 planes.-1000uF input capacitors.-6 AWG12 cables (per input voltage) -> low losses in long cabling.-12 AWG20 cables for output power and Vref Vbias signals.-JST 3A (XA) and JST 20A(EV) connectors.

X. Schedule

-Prototype tests start MARCH.-Firmware development MARCH-APRIL.-Tests with load and I2C master (emulation of Control Board) APRIL-MAY.-Final revision and start of production JUNE.-Test of production SEPTEMBER.