logic style 1
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Combinational Logic Gates in CMOS
References:
Adapted from: Digital Integrated Circuits: A Design
Perspective, J. Rabaey, Prentice Hall UCBPrinciples of CMOS VLSI Design: A Systems Perspective,
N. H. E. Weste, K. Eshraghian, Addison Wesley
Adapted from: EE216A Lecture Notes by Prof. K. Bult
UCLA
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Combinational vs. Sequential Logic
CombinationalSequential
State
Out = f(In) Out = f(In, State)
State is related to previous inputs
Stored in registers, memory etc
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Overview
Static CMOS
Complementary CMOS
Ratioed Logic
Pass Transistor/Transmission Gate Logic Dynamic CMOS Logic
Domino
np-CMOS
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Static CMOS Circuit
At every point in time (except during the switching
transients) each gate output is connected to either
VDD or VSS via a low-resistive path
The outputs of the gates assume at all times the
value of the Boolean function, implemented by the
circuit
In contrast, a dynamic circuit relies on temporary
storage of signal values on the capacitance of highimpedance circuit nodes
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Digital Gates
Fundamental Parameters
Area and Complexity
Performance
Power Consumption Robustness and Reliability
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What Can Go Wrong in CMOS Logic?
Incorrect or insufficient power supplies
Power supply noise
Noise on gate input Faulty connections between transistors
Clock frequency too high or circuit too slow
Complementary CMOS is pretty
safe against these
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How about Ratioed or Dynamic Logic?
All the previous and
Incorrect ratios in ratioed logic
Charge sharing in dynamic logic Incorrect clocking in dynamic logic
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Complementary CMOS
PUN
PDN
in1in2in3
in1in2in3
VDD
VSS
F = G
NMOS only
PMOS only
PUN and PDN are dual networks
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NMOS Transistors in Series/Parallel Connection
Transistors can be thought as a switch controlled byits gate signal
NMOS switch closes when switch control input is
high
X Y
A B
X = Y if A = 1 and B = 1, i.e., AB = 1
NMOS passes a strong 0 but a weak 1
X Y
A
B X = Y if A = 1 or B = 1, i.e., A + B = 1
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NMOS Transistors in Series/Parallel Connection
Connect Y to GND
X Y
A B
X = 0 if A = 1 and B = 1, i.e., A.B = 1
Implement the complement of PDN
X Y
A
B
X = 0 if A = 1 or B = 1, i.e., A + B = 1
X = A.B
X = A + B
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PMOS Transistors in Series/Parallel Connection
PMOS switch closes when switch control input is low
X Y
A B X = Y if A = 0 and B = 0
or A + B = 1
or A.B = 1
PMOS passes a strong 1 but a weak 0
X Y
A
B X = Y if A = 0 or B = 0
A.B = 1
A + B = 1
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PMOS Transistors in Series/Parallel Connection
Connect Y to VDD
X Y
A B
X = 1 if A = 0 and B = 0
Combine series PDN and parallel PUN or parallel
PDN and series PUN to complete the logic design to
output good 1 and 0
X Y
A
BX = 1 if A = 0 or B = 0
X = A + B = A.B
X = A.B = A + B
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Complementary CMOS Logic Style Construction
PUN is the DUAL of PDN (can be shown usingDeMorgans Theorems)
BABA
BAAB
The complementary gate is inverting
Implements NAND, NOR,
Non-inverting boolean function needs an inverter
,...),,(,...),,( 321321 inininFinininG
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The NAND Circuit
B
A
BA
1 1
1 0
0 1
0
1
A
B
B
Out
A
BA.
,...),,(,...),,( 321321 inininFinininG
BAG .:GNDtoconnectedPDNABBAFVDD :toconnectedPUN
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B
A
1 0
0 0
0 1
0
1
A
B
A B
The NOR Circuit
A + B
A . B
BAOutput
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Example Gate: COMPLEX CMOS GATE
VD D
A
B
C
D
D
A
B C
OUT = D + A (B+C)
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F = ((A.B) + C.(A+B)) = carry
B
C
A
A
output
A
B
B
B
C
A
A
B
B
output
A B
C
A
BA
C
Symmetrical !
Remove
redundancy
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Full Adder Circuit
A
B
B
C
A
B
CB
A A
A B C A
A B C
B
C
C
B
A
-sum-carry
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4-input NAND Gate
In1 In2 In3 In4
VDD
GND
Out
ln2
ln1
ln2
Out
ln1
ln4
ln3
ln4ln3
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Standard Cell Layout Methodology
VDD
VSS
Well
signalsRouting Channel
metal1
polysilicon
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Two Versions of (a+b).c
a c b a b c
xx
GND
VDDVDD
GND
(a) Input order {a c b} (b) Input order {a b c}
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Logic Graph
VDD
c
a
x
b
c
a
b
GND
x
VDDx
c
b a
i
j
i
j
PDN
PUN
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Consistent Euler Path
{a b c}
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Example: x = ab+cd
GND
x
a
b c
d
VDDx
GND
x
a
b c
d
VDDx
(a) Logic graphs for (ab+cd) (b) Euler Paths {a b c d}
a c d
x
VDD
GND
(c) stick diagram for ordering {ab c d}
b
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Properties of Complementary CMOS Gates
High noise margin
VOH and VOL are at VDD and GND, respectively
No static power consumption
In steady state, no direct path between VDD and VSS
Comparable rise and fall times under appropriate
scaling of PMOS and NMOS transistors
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Transistor Sizing
For symmetrical response (dc, ac)
For performance
Input dependent
Focus on worst-case
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Propagation Delay Analysis - The Switch Model
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Analysis of Propagation Delay
Assume CL dominates
Assume Rn = Rp = resistance
of minimum sized NMOS
inverter For tpLH
Worst case when only one
PMOS pulls up the output node
tpLH RpCL
For tpHL Worst case when two NMOS in
series
tpHL 2RnCL
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3-Input NAND Gate
inc out
inb
ina
rise-time: 1 transistor (simple)
fall-time: 3 transistor in series
for linear approximation: take 3xRon
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3-Input NAND Gate
inc out
inb
ina
If n = 3 p
for equal fall and rise time:
Take Wn = Wp
If n = 2 p
for equal fall and rise time:
Take Wn = (3/2)Wp
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Design for Worst Case
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3-input NAND Gate with Parasitic Capacitors
inc
out
inb
ina
Cp+load
Ca
Cb
Cc
P1 P2 P3
N3
N2
N1
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Worst Case Approximation
Using Lumped RC Model
))(()( 321 loadpcbaNNN
pulldownpulldowndf
CCCCRRR
CRt
(We ignore the constant term 0.69 or 1.22)
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Distributed RC Effects
C C C CC
R R R R R
2
.
2
)1( nCnRnnRCtn
Worst case under lumped model: tn = nR.nC
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Comparison
tdf= [RNICa] + [(RN1+RN2)Cb] + [(RN1+RN2+RN3)Cc] +
[(RN1 + RN2 + RN3)Cp+load]
RNC n(n+1)/2 + [(RN1+RN2+RN3)Cp+load]
With RN1 = RN2 = RN3 = RNand Ca = Cb = Cc = C
n transistors in series
RP-Model
Lumped-Model
RNC n2+ [(RN1+RN2+RN3)Cp+load]
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Macro Modeling
td = [RN1Ca] + [(RN1+RN2)Cb] + [(RN1 + RN2 + RN3)Cc] +
[(RN1 + RN2 + RN3)Cp + [(RN1 + RN2 + RN3)Cload]
Internal delay External load
td = Td, internal + x Cload
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Effect of Loading
CL = 0.0pF
CL = 0.5pF
CL = 1.0pF
t
td = td, internal + x Cload
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Effect of Fan-In and Fan-Out
on Delay
ln2
ln1
ln2
Out
ln1
ln4
ln3
ln4ln3
Fan-out: number of gates connected
2 gate capacitance per fan-out
Fan-in: number of inputs to a gate
Quadratic effect due to increasing
resistance and capacitance
FOaFIaFIatd 32
21
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tp as a function of Fan-In
1 3 5 7 9
fan-in
0.0
1.0
2.0
3.0
4.0
tp
(nse
c)
tpHL
tp
tpLHlinear
quadratic
AVOID LARGE FAN-I N GATES! (Typically not more than F I < 4)
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Example
3-Input NAND gate with Parasitic Capacitors
inc
out
inb
ina
Cp+load
Ca
Cb
Cc
P1 P2 P3
Rn=0.5Rp=
Ca=Cb=Cc=Cj=0.05pF
Cp=3Cj=0.15pF
Cload=2Cg=0.20pF
4102
1
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Worst Case Approximation
by Lumped Model
tdr = Rp x (Cc + Cp+load) = 10000 x 0.4 10-12 = 4.0ns
tdf= Rpulldown x Cpulldown
= (RN1 + RN2 + RN3) x (Ca + Cb + (Cc + Cp+load))
= (3 x 5000) x (3 x 0.05 + 0.15 + 0.20) x 10-12
= 7.5ns
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Penfield-Rubenstein Model
tdr = Rp x (Cc + Cp+load) = 10000 x 0.4 10-12 = 4.0ns
tdf = [RN1Ca] + [(RN1 + RN2)Cb] + [(RN1 + RN2 + RN3)(Cc + Cp+load)]
= 5000 x 0.05pF + 10000 x 0.05pF + 15000 x 0.4pF = 6.75ns
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Worst Case Approximation
by Lumped Model
tdr = Rp x (Cc + Cp+load) = 10000 x 0.45 10
-12
= 4.5ns
tdf= Rpulldown x Cpulldown
= (RN1 + RN2 + RN3) x (Ca + Cb + (Cc + Cp+load))
= (3 x 2500) x (3 x 0.10 + 0.15 + 0.20) x 10-12
= 4.875ns
Make Wn = 2Wp
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Rewriting Penfield-Rubenstein Equation
td = RiiCdownstream-i
with: Cdownstream-i = downstream capacitance at node i
Rii = resistance at node i
td = [RN1Ca] + [(RN1 + RN2)Cb] +
[(RN1 + RN2 + RN3)(Cc+ Cp+load)]
td = [RN1(Ca + Cb + Cc + Cp+load)] +
[RN2 ( Cb + Cc + Cp+load)] +
[RN3(Cc+ Cp+load)]
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Progressive Sizing
When parasitic capacitance
is significant (e.g., when fan-
in is large), needs to
consider distributed RCeffect
Increasing the size of M1 has
the largest impact in terms of
delay reduction M1 > M2 > M3 > > MN
ln3
lnN
Out
ln1
ln2
M1
M2
M3
MN
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Delay Optimization by Transistor Ordering
ln3
lnN
Out
ln1
ln2
M1
M2
M3
MN
Critical signal next to supply
Critical path
ln3
lnN
Out
ln1
ln2
M1
M2
M3
MN
Critical signal next to output
Critical path
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