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Electronics PackagingTKK 2009 L 1
James E. MorrisDept of Electrical & Computer
Engineering
TKK 2009 Lecture 1
Portland State University
Tuesday Lecture Friday Lecture
Electronics Packaging
Tuesday Lecture Friday Lecture
April 7: Introduction
April 17: Electrical Package Design
April 21: Package Reliability April 24: Electrically Conductive Adhesives I
April 28: Electrically Conductive Adhesives II
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Download course notes from: http://www.ece.pdx.edu/~jmorris/TKK/UG
e-mail: jmorris@cecs.pdx.edu
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ReferencesR. Ulrich & W.D.Brown (editors)
“Advanced Electronic Packaging, 2nd edition” Wiley/IEEE Press (2005)
Tummala (editor) “Fundamentals of Microsystems Packaging” McGraw Hill (2001)McGraw-Hill (2001)
Pecht et al “Integrated Circuit, Hybrid, & MCM Packaging Design Guidelines” Wiley (1994)J.E. Morris (editor) “Electronics Packaging Forum: Vols 1 & 2” VNR (1990) J.E. Morris (editor) “Electronics Packaging Forum: MCM Issues” IEEE Press (1994)
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IEEE Press (1994)
Johan Liu (editor) “Conductive Adhesives for Electronics Packaging” Electrochemical (1999)
Lecture 1 Introduction
The package roadblock to system performance
What is packaging?
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Packaging technologies
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Borsuk & Coffey, Defense Horizons
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Why is Packaging Important?
Elementary example:
Semiconductor Chip Parametersp1980 1990
Feature size 4 μm 1 μmChip area 0.3 cm2 1.5 cm2
Gates/chip 5,000 100,000
μP clock freq 6 MHz 40 MHz
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μP clock freq 6 MHz 40 MHzPower 2 W 10 W
I/O count 64 1500
Chip density, power, speed
1980 19901980 1990
Ckt size L2 4μ→1μ L2/16
Chip size 0.3cm2 5xArea→ 1.5cm2
Ckts/chip N → 5x16N=80N (20N)
P di n 2 80 2 /4 40 (10 )Pwr dissn 2w I÷4→ 80x2w/4=40w (10w)
Clk freq 6MHz C/16, I/4 24MHz (40MHz)
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ITRS product categoriesProduct category Product description
Low cost <$ 300: consumer products, microcontrollers, disk drivers
Hand-held <$ 1000: battery powered products e.g. mobile and cellular products
Cost/performance <$3000: notebooks, desktop personal computers
High performance >$3000:high-end work stations, servers, avionics,
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supercomputer
Harsh environment Under-the-hood and other hostile environment products
Memory DRAM’s, SRAM’s
ITRS Packaging requirements
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Semi-log Moore's plots of the Road-map data
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Rent’s Rule
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Rent’s rule plot of roadmap data
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Pkg pins ≈ Kp(bits or gates)β
β Kβ Kp
SRAM 0.12 6μP 0.45 0.82Gate array 0.50 1.9Computr:chip 0.63 1.4Computr:syst 0.25 82
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Rent’s Rule
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Example I/O
Package 1980 1990Package 1980 64-pin DIL0.1in pitch3.3x1.0in2
19901500-pin QFP0.01in pitch3.75x3.75in2
Pkg I/O 64 pins Rent’s rule→ 1500 pins
Chip: 0 6x0 5cm2 1 25x1 2cm2Chip: 0.6x0.5cm 1.25x1.2cm
I/O pitch 344 μm 33 μm
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Clock Frequency vs Time
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Bare and packaged chip speeds
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Power dissipation follows clock frequency
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Trend to CSP
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Package functions
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Electronics Packaging is Multi-disciplinary!Electrical
ArchitecturesPower distribution
MaterialsMetallurgyCeramics
EMI/EMC, crosstalk, ΔI & switching noise
MechanicalVibrationsStress
ThermalC d l
PolymersSurface scienceInterfaces/diffusion
ManufacturingInstrumentationProcess control
f b l / T
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Conduction coolingConvection cooling
Manufacturability/ Test
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Packaging Levels
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Lead Pitch/Density: peripheral leads, area array, 3D
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PWB Density
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PWB line width, pitch, & pin-count
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Electronics Packaging
Electronics packaging covers all technologies involved in device manufacture and design from the chip to the board. In modern d i it i ll th k hi h li it t f d devices, it is usually the package which limits system performance, and its cost can greatly exceed the cost of the silicon chip it supports. Packaging engineers are much in demand, therefore, due also to the fact that the field’s inherently multi-disciplinary nature creates a shortage of qualified people. Modern practice calls for chip/package co-design, making an understanding of packaging principles a must for all IC designers
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all IC designers.
Lecture Objectives
Introduce first-level interconnect technologies:wire bond & flip chip wire-bond & flip-chip
Introduce standard SMT & PTH packages(surface mount technology & pin through hole)
Introduce MCM, COB, DCA, CSP, WLP, etc (multi-chip modules, chip on board, direct chip attach, chip-scale package, wafer-level packaging)
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p g p g g
Introduce basic packaging acronyms
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Packaging TechnologiesSingle-chip packages (SCPs)
Multi-chip modules (MCMs)
Encapsulation
Wire Bond
[TAB (tape automated bonding)]
Flip-Chip
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New developments
Single-Chip Packages:
1st level interconnects wire bond TAB FC1st level interconnects: wire-bond, TAB, FC
2nd level interconnects: PTH & SMT
MCMs (multi-chip modules)
DCA (direct chip attach)
CSP (chip scale packages)
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First-level interconnect
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Wirebond TAB Flip-chip(Tape-automated bonding)
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PTH
PGA
SMT:J l dJ-leadGull-wingLeadless
COB/DCAflip-chipTAB
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TAB
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Second-level package attach
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Substrate Vias
PCB (printed circuit board) or PWB (printed wiring board)
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Multi-layer laminate
Drilled, electroplated Cu
Copper paste (ALIVH), silver loaded (ECA) epoxies, etc
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Flip-chip (C4) BGA (C5) MCM-C
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Encapsulation: “Glob-top”
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COB/DCA encapsulation
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Encapsulation: Cavity-fill
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Encapsulation: Transfer molding
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Encapsulation: Underfill
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Dual-in-line (DIL) plastic package (DIP)
Wire-bonding
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Wire sweep
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Wafer bumping
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Solder bumps
As printed →As printed →
Re-flowed →
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WLP & Redistribution
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