lecture 7 amplifier design 1 - university of...

Lecture 7Amplifier Design 1

Trevor Caldwelltrevor.caldwell@awaveip.com

ECE1371 Advanced Analog Circuits

ECE13712

Lecture PlanDate Lecture (Wednesday 2-4pm) Reference Homework

2020-01-07 1 MOD1 & MOD2 PST 2, 3, A 1: Matlab MOD1&22020-01-14 2 MODN + Toolbox PST 4, B

2: Toolbox2020-01-21 3 SC Circuits R 12, CCJM 142020-01-28 4 Comparator & Flash ADC CCJM 10

3: Comparator2020-02-04 5 Example Design 1 PST 7, CCJM 142020-02-11 6 Example Design 2 CCJM 18

4: SC MOD22020-02-18 Reading Week / ISSCC2020-02-25 7 Amplifier Design 1

Project

2020-03-03 8 Amplifier Design 22020-03-10 9 Noise in SC Circuits2020-03-17 10 Nyquist-Rate ADCs CCJM 15, 172020-03-24 11 Mismatch & MM-Shaping PST 62020-03-31 12 Continuous-Time PST 82020-04-07 Exam2020-04-21 Project Presentation (Project Report Due at start of class)

ECE13713

Circuit of the Day: Cascode Current Mirror• How do we bias cascode

transistors to optimize signal swing?

• Standard cascodecurrent mirror wastes too much swing

VX = VEFF + VTVY = 2VEFF + 2VTMinimum VZ is 2VEFF + VT, which is VT larger than necessary

ECE13714

What you will learn…• Choice of VEFF

Several trade-offs with Noise, Bandwidth, Power,…• Amplifier Topology• Amplifier Settling

Dominant Pole, Zero and Non-Dominant Pole• Gain-Boosting

Stability, Pole-Zero Doublet• Delaying vs. Non-Delaying stages

ECE13715

Choice of Effective Voltage• Effective Voltage VEFF = VGS - VT

Assumes square-law modelIn weak-inversion, this relationship will not hold

• What are the trade-offs when choosing an appropriate effective voltage?

Noise PowerBandwidth MatchingLinearity Swing

D DEFF

m n ox

2I 2IV Wg C L

ECE13716

Thermal Noise and VEFF

• Noise Current and Noise Voltage

• Ex. Common Source with transistor loadCS transistor has input referred noise voltage proportional to VEFF

Current source has input referred noise voltage inversely proportional to VEFF

2 4n mI kT g 2 4n

m

kTVg

2,1

42n EFF

D

kTV VI

2,12

,2

42

EFFn

D EFF

VkTVI V

ECE13717

Thermal Noise and VEFF

• Total Noise

Use small VEFF for input transistor, large VEFF for load (current source) transistor

,12,1

,2

4 12

EFFn EFF

D EFF

VkTV VI V

B

IN

n,22

n,12

ECE13718

Bandwidth and VEFF

• Bandwidth dependent on transistor unity gain frequency fT

If CGS dominates capacitance

Small L, large maximizes fTFor a given current, decreasing VEFF increases W, increases CGS, and slows down the transistor

• fT increases with VEFF

2 ( )m

TGS GD

gfC C

21.52

nT EFFf V

L

ECE13719

Linearity and VEFF

• Look at distortion through a CS amplifierCompare amplitude of fundamental and second-order distortion term

• Linearity increases with VEFF

2

4HD A

F EFF

V VV V

2

2

1cos( ) 1 cos(2 )4n ox EFF A n ox A

F HD

W WI C V V t C V tL LV V

21 cos( )2D n ox EFF A

WI C V V tL

IN

OUT

D

ECE137110

Power and VEFF

• Efficiency of a transistor is gm/IDTransconductance for a given current – high efficiency results in lower powerBipolar devices have gm=IC/Vt, while (square-law) MOS devices have gm=2ID/VEFF

• VEFF is inversely proportional to gm/ID

Increasing VEFF reduces efficiency of the transistorBiasing in weak inversion increases efficiency

-0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.50

5

10

15

20

25

30

VGS-VT

g m/I D

ECE137111

Matching and VEFF

• With low VEFF, transistor is in weak inversionWhat happens with mismatch in Vt?

• Use a current-mirror as an example with mismatched threshold voltages

IN OUT

t,1 t,2

ECE137112

Matching and VEFF

• In strong inversion with Vt mismatch there is a quadratic relationship

1mV error in Vt is ~1% error in IOUT (for VEFF~200mV)

• In weak inversion with Vt mismatch there is an exponential relationship

1mV error in Vt is ~4% error in IOUT

2,2

2,1

( )( )

GS tOUT

IN GS t

V VII V V

,1,2 ,1

,2

GS tt tT

T

GS t

T

V VV VnV

nVOUTV V

IN nV

I e eI

e

ECE137113

Swing and VEFF

• Minimum VDS of a transistor to keep it in saturation is VEFF

Usually VDS is VEFF + 50mV or more to keep ro high (keep the transistor in the saturation region)With limited supply voltages, the larger the VEFF, the larger the VDS across the transistor, less room for signal swing

• With large VEFF…Can’t cascode – reduced OTA gainStage gain is smaller – input referred noise is larger (effectively the SNR at the stage output is less)

ECE137114

Speed-Efficiency Product• What is the optimal VEFF using a figure of merit

defined as the product of fT and gm/IDOptimal point at VEFF = 130mV in 0.18m

-0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.50

50

100

150

200

250

300

VGS-VT

g m/I D

*fT

ECE137115

Summary of Trade-Offs• Benefits of larger VEFF

Larger bandwidthHigher linearityBetter device matchingLower noise for current-source transistors

• Benefits of smaller VEFFBetter efficiency – lower powerLarger signal swingsBetter noise performance for input transistors

Good starting point: VEFF ~ VDD/10

ECE137116

Amplifier Design - Topology

Topology Gain Output Swing Speed Power

Dissipation Noise

Telescopic Medium Medium Highest Low Low

Folded-Cascode Medium Medium High Medium Medium

Two-Stage High Highest Low Medium Low

Gain-Boosted High Medium Medium High Medium

From Razavi Ch.9

ECE137117

Amplifier Errors• Two errors: Dynamic and Static

• Static ErrorsLimit the final settling accuracy of the amplifierCapacitor Mismatch (C1/C2 error)Finite OTA gain

1 2 1 2

2

2 1 2

11 ( ) /( ) 1 1/

1 ( ) /

O

I

V C C C C Az AV C zC C C A

ECE137118

Amplifier Errors

• Dynamic Errors: Occurs in the integration phase when a ‘step’ is applied to the OTA

SlewingFinite bandwidthFeedforward pathNon-dominant poles

ECE137119

Static Amplifier Errors• First look at frequency independent response

Static error term 1/A

• Example: 0.1% error at output (Gain = 4)C1 = 4pF, C2 = 1pF, CIN = 1pF

A > 6000 for 0.1% error

1 1

2 2

1 111 1/

O

I

V C CV C A C A

2

1 2 IN

CC C C

64 1O

I

VV A

ECE137120

Dynamic Amplifier Errors

• What is the transfer function of this circuit?By inspection…Gain is -C1/C2Zero when VXsC2 = VXGmPole at Gm/CL,eff where CL,eff = C2(1-) + CL

2

1

,2

1

1O m

L effI

m

sCV C G

sCV CG

ECE137121

Single-Pole Settling Error• Step response of 1st-order (unity-gain) system

Unit step through system

Inverse Laplace transform of

Step response is

Error is

Settles to N-bit accuracy in

1s

11 / unitys

1(1 / )unitys s

1 unityte

unityte

ln2unity

Nt

ECE137122

Pole and Zero Settling Error• Step response, 1st-order with feedforward zero

Unit step through system

Inverse Laplace transform of

Step response is

Error is

Settles to N-bit accuracy in

1 /1 /

z

unity

ss

1s

1 /(1 / )

z

unity

ss s

1 unity unityt tunity

z

e e

unity unityt tunity

z

e e

ln(1 / )ln2 unity z

unity unity

Nt

ECE137123

Effect of Zero on Settling• Zero slows down settling time

Additional settling term

Coefficient a function of feedback factor

• To reduce impact of feedforward zero…Smaller (one of the few advantages of reducing )Larger CL

unitytunity

z

e

, 2

2 2

// (1 )

unity m L eff

z m L

G C CG C C C

ECE137124

Effect of Zero on Settling• Example of settling behaviour

= 1/2, CL = C2/2

0 0.2 0.4 0.6 0.8 1

0

0.2

0.4

0.6

0.8

1

1.2

Time (ns)

Ampl

itude

No Zerow/ Zero

ECE137125

Two-Pole Settling Error• Dominant and non-dominant pole, 2nd-order sys.

(assumes p2 >> p1 = unity/A)

Unit step through system

Step response is dependent on relative values of unityand p2

3 Cases:Overdamped, p2 > 4unityCritically damped, p2 = 4unityUnderdamped, p2 < 4unity

2

2

1

1p unity unity

s s

1s

ECE137126

Two-Pole Settling Error• Closed loop response of the amplifier

(ignoring zero, including 2nd pole)

ECE137127

Two-Pole Settling Error• Overdamped, p2 > 4unity

2nd pole much larger than unity-gain frequencySimilar to 1st-order settling as 2nd pole approaches infinityStep response is

• Critically damped, p2 = 4unityNo overshootStep response is

1 At BtB Ae eB A A B

22 22 4

,2 2

p p unitypA B

2 21 2unity unityt tunitye te

𝝎𝒑𝟐,𝜷𝝎𝒖𝒏𝒊𝒕𝒚

ECE137128

Two-Pole Settling Error• Underdamped, p2 < 4unity

Minimum settling time depending on desired SNR Increasing overshoot as p2 decreasesStep response is

2

2

222

2222

2

2

sin4

1 cos4 4

1

p

p

t punity p

t punity p

unity

p

e t

e t

ECE137129

Two-Pole Settling• Example:

unity/2 = 1GHzp2/2 = 1GHz, 4GHz, 100GHz

0 0.2 0.4 0.6 0.8 10

0.2

0.4

0.6

0.8

1

1.2

Time (ns)

Ampl

itude

Critically DampedOverdampedUnderdamped

ECE137130

Two-Pole Settling• Critically damped system settles faster than

single-pole system

0 1 2 3 4-120

-100

-80

-60

-40

-20

0

Time (ns)

Settl

ing

Erro

r (dB

)

Critically DampedOverdampedUnderdamped

ECE137131

Two-Pole Settling• Underdamped system gives slightly better

settling time depending on the desired SNR

0 0.5 1 1.5 2-140

-120

-100

-80

-60

-40

-20

0

Time (ns)

Settl

ing

Erro

r (dB

)

p2=4unityp2=3.8unityp2=3.6unity

ECE137132

Two-Pole Settling• For a two-pole system, phase margin can be

used equivalently

Critically damped: PM = 76 degreesUnderdamped: PM < 76 degrees

(45 degrees if p2 = unity)Overdamped: PM = 76 to 90 degrees

2118090 tan p

unity

PM

ECE137133

Gain-Boosting• Increase output impedance of cascoded

transistorImpedance boosted by gain of amplifier AVOUT/VIN = -gmROUTROUT ~ Agmro

2

• Trade-offsDoes not require extra headroomAmplifier requires some power, but does not have to be very fast

IN

b

B

OUT

XL

ECE137134

Gain-Boosting• Need to analyze gain-boosting loop to ensure

that it is stableCascade of amplifier A and source follower from node Y to node X

• Load capacitance at node YMay need extra capacitance CCto stabilize loop

IN

b

B

OUT

X

Y

CC

ECE137135

Gain-BoostingAORIG: Original amplifier response without gain-boostingAADD: Frequency response of feedback amplifier AATOT: Gain-boosted amplifier frequency response

ECE137136

Gain-Boosting• Stability of gain-boosted amplifier

For 1st-order roll-off, the unity-gain frequency of the additional amplifier must be greater than the 3dB frequency of the original stage

3dB < UG,A

(if 3dB > UG,A there will be a discontinuity in the 1st order roll-off between UG,A and 3dB)

ECE137137

Gain-Boosting• 2nd pole of feedback loop is equivalent to 2nd

pole of main amplifierSet unity-gain frequency of additional amplifier lower than 2nd pole of main amplifier

UG,A < 2nd

• Only 45 degree phase margin if UG,A = 2ndUG,A ~ 2nd/3 for a phase margin of ~71 degreesUG,A ~ 2nd/4 for a phase margin of 76 degrees

ECE137138

Gain-Boosting• Pole-zero doublet occurs at UG,A

Must ensure that this time constant does not dominate the settling behaviour

• Set 5 (3dB frequency of closed loop amplifier response) below UG,A

Ensures that time constant is dominated by 3dB frequency and not the pole-zero doublet

< UG,A

Final Constraint: 5 < UG,A < 2nd

ECE137139

Pole-Zero DoubletZCL: Load CapacitanceZOUT: gain-boosted output impedance ~ (1+A)gmro

2

ZORIG: cascoded output impedance ~ gmro2

ZTOT: Total Output Impedance

1 2 3dB UG,A 5 2nd

ORIG

OUT

CL

pole-zero

TOT

ECE137140

Pole-Zero Doublet• Why is this a problem?

Doublet introduces a slower settling component in the step responseStep response (where z and p are the doublet pole and zero locations, ~UG,A):

A higher-frequency doublet will always have an impact but will die away quicklyA lower-frequency doublet will not have as large an impact, but it will persist much longer

1 unity zt z p t

unity

e e

ECE137141

Delaying vs. Non-Delaying Stage• Depending on the architecture and stage sizing,

this can be a power concernLarge CL reduces the power efficiency of an amplifierLarger amplifier results in a smaller feedback factor and reduced bandwidth

ECE137142

Delaying Stage• Delaying

Following stage does not load the outputVery little CL on output of the amplifier

• Example:1st stage 4x larger than 2nd stage (C3 = 0 for delaying, C3 = C1/4 for non-delaying)Each stage has gain of 2 (C1/C2 = 2, C3/C4 = 2)

2 1, 3 1 3

1 2

( ) ( )INL eff IN

IN

C C CC C C C CC C C

, 1( ) m m

unity delayL eff IN

g gC C C

delay mP g

ECE137143

Non-Delaying Stage• Non-Delaying

Following stage loads the outputApplicable in pipeline ADCs, sometimes (usually following stages much smaller, depending on OSR)Opamp is wasted during the non-amplifying stage (could power it down to save power)

• Example (continued):

Increase gm by 1.75 CIN increases by 1.75 (approximately the same bandwidth with 1.75x power)

for

, 1( )

1.75 1.5m m

unity non delayL eff IN

g gC C C

1.75non delay mP g ( ) ( )unity non delay unity delay

ECE137144

Amplifier Stability• Both phases are important

Different loading on sampling and amplification phase

• Feedback factor is larger in sampling phase than amplification phase

Amplifier could potentially go unstable if it was originally sized for optimal phase margin in the amplification mode

• Non-Delaying stages are more susceptible to instability in sampling phase since a much smaller load capacitance is present

ECE137145

Amplifier Stability• Example:

C1 = 2pF, C2 = 1pF, CIN = 1pFCL = 0.5pF (load of subsequent stage)

Delaying StageAmplification: unity = gm/3pFSampling: = 1/2, CL,eff = 1pF, unity = gm/2pFPhase Margin: 73 65 (assume same p2)

ECE137146

Amplifier StabilityNon-Delaying Stage

Amplification: = 1/4, CL,eff = 1.25pF, unity = gm/5pFSampling: = 1/2, CL,eff = 0.5pF, unity = gm/1pFPhase Margin: 73 33 (assume same p2)

ECE137147

Circuit of the Day: Cascode Current Mirror

ECE137148

What You Learned Today• Choice of VEFF

Trade-offs with various parameters• Amplifier Topology• Amplifier Step Response• Gain-Boosting• Choice of Delaying/Non-Delaying Stages

Impact on stability of sampling/integrating phases