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[01.2
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Mod. 0805 2017-01 Rev.6
LE910Cx Multi Technology Interface Board TLB - HW User Guide
1VV0301508 Rev. 2 – 2019-03-08
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SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE
NOTICE
While reasonable efforts have been made to assure the accuracy of this document, Telit assumes no liability resulting from any inaccuracies or omissions in this document, or from use of the information obtained herein. The information in this document has been carefully checked and is believed to be reliable. However, no responsibility is assumed for inaccuracies or omissions. Telit reserves the right to make changes to any products described herein and reserves the right to revise this document and to make changes from time to time in content hereof with no obligation to notify any person of revisions or changes. Telit does not assume any liability arising out of the application or use of any product, software, or circuit described herein; neither does it convey license under its patent rights or the rights of others. It is possible that this publication may contain references to, or information about Telit products (machines and programs), programming, or services that are not announced in your country. Such references or information must not be construed to mean that Telit intends to announce such Telit products, programming, or services in your country.
COPYRIGHTS
This instruction manual and the Telit products described in this instruction manual may be, include or describe copyrighted Telit material, such as computer programs stored in semiconductor memories or other media. Laws in the Italy and other countries preserve for Telit and its licensors certain exclusive rights for copyrighted material, including the exclusive right to copy, reproduce in any form, distribute and make derivative works of the copyrighted material. Accordingly, any copyrighted material of Telit and its licensors contained herein or in the Telit products described in this instruction manual may not be copied, reproduced, distributed, merged or modified in any manner without the express written permission of Telit. Furthermore, the purchase of Telit products shall not be deemed to grant either directly or by implication, estoppel, or otherwise, any license under the copyrights, patents or patent applications of Telit, as arises by operation of law in the sale of a product.
COMPUTER SOFTWARE COPYRIGHTS
The Telit and 3rd Party supplied Software (SW) products described in this instruction manual may include copyrighted Telit and other 3rd Party supplied computer programs stored in semiconductor memories or other media. Laws in the Italy and other countries preserve for Telit and other 3rd Party supplied SW certain exclusive rights for copyrighted computer programs, including the exclusive right to copy or reproduce in any form the copyrighted computer program. Accordingly, any copyrighted Telit or other 3rd Party supplied SW computer programs contained in the Telit products described in this instruction manual may not be copied (reverse engineered) or reproduced in any manner without the express written permission of Telit or the 3rd Party SW supplier. Furthermore, the purchase of Telit products shall not be deemed to grant either directly or by implication, estoppel, or otherwise, any license under the copyrights, patents or patent applications of Telit or other 3rd Party supplied SW, except for the normal non-exclusive, royalty free license to use that arises by operation of law in the sale of a product.
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USAGE AND DISCLOSURE RESTRICTIONS
I. License Agreements
The software described in this document is the property of Telit and its licensors. It is furnished by express license agreement only and may be used only in accordance with the terms of such an agreement.
II. Copyrighted Materials
Software and documentation are copyrighted materials. Making unauthorized copies is prohibited by law. No part of the software or documentation may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, without prior written permission of Telit
III. High Risk Materials
Components, units, or third-party products used in the product described herein are NOT fault-tolerant and are NOT designed, manufactured, or intended for use as on-line control equipment in the following hazardous environments requiring fail-safe controls: the operation of Nuclear Facilities, Aircraft Navigation or Aircraft Communication Systems, Air Traffic Control, Life Support, or Weapons Systems (High Risk Activities"). Telit and its supplier(s) specifically disclaim any expressed or implied warranty of fitness for such High Risk Activities.
IV. Trademarks
TELIT and the Stylized T Logo are registered in Trademark Office. All other product or service names are the property of their respective owners.
V. Third Party Rights
The software may include Third Party Right software. In this case you agree to comply with all terms and conditions imposed on you in respect of such separate software. In addition to Third Party Terms, the disclaimer of warranty and limitation of liability provisions in this License shall apply to the Third Party Right software. TELIT HEREBY DISCLAIMS ANY AND ALL WARRANTIES EXPRESS OR IMPLIED FROM ANY THIRD PARTIES REGARDING ANY SEPARATE FILES, ANY THIRD PARTY MATERIALS INCLUDED IN THE SOFTWARE, ANY THIRD PARTY MATERIALS FROM WHICH THE SOFTWARE IS DERIVED (COLLECTIVELY “OTHER CODE”), AND THE USE OF ANY OR ALL THE OTHER CODE IN CONNECTION WITH THE SOFTWARE, INCLUDING (WITHOUT LIMITATION) ANY WARRANTIES OF SATISFACTORY QUALITY OR FITNESS FOR A PARTICULAR PURPOSE. NO THIRD PARTY LICENSORS OF OTHER CODE SHALL HAVE ANY LIABILITY FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND WHETHER MADE UNDER CONTRACT, TORT OR OTHER LEGAL THEORY, ARISING IN ANY WAY OUT OF THE USE OR DISTRIBUTION OF THE OTHER CODE OR THE EXERCISE OF ANY RIGHTS GRANTED UNDER EITHER OR BOTH THIS LICENSE AND THE LEGAL TERMS APPLICABLE TO ANY SEPARATE FILES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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APPLICABILITY TABLE
This documentation applies to the following product families:
Module Name Description
LE910Cx LE910C1-NA, LE910C1-AP, LE910C1-NS, LE910C4-NS, LE910C1-EU
The features described by the present document are provided by the products equipped with the software versions equal or higher than the versions shown in the table.
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Contents
NOTICE….. ....................................................................................................... 2
COPYRIGHTS .................................................................................................. 2
COMPUTER SOFTWARE COPYRIGHTS ....................................................... 2
USAGE AND DISCLOSURE RESTRICTIONS ................................................ 3
APPLICABILITY TABLE .................................................................................. 4
CONTENTS ...................................................................................................... 5
1. INTRODUCTION ............................................................................ 7 Scope ............................................................................................. 7 Contact Information, Support ......................................................... 7 Text Conventions ........................................................................... 8 Related Documents ........................................................................ 9 Document Organization .................................................................. 9
2. GENERAL DESCRIPTION .......................................................... 10 MultiTech Interface Board TLB view............................................. 11
3. FPGA ........................................................................................... 13 Programming the FPGA ............................................................... 13
3.1.1. Prerequisites ................................................................................ 13 FPGA Mode Selection .................................................................. 15
4. 120-PIN BOARD TO BOARD CONNECTORS ........................... 16
5. COMPONENT ASSEMBLY DIAGRAM ....................................... 19
6. SCHEMATICS .............................................................................. 21
7. ACRONYMS ................................................................................ 22
8. DOCUMENT HISTORY ................................................................ 23
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FIGURE LIST Figure 1: MultiTech Interface Board TLB - Top View ........................................................ 11 Figure 2: MultiTech Interface Board TLB - Bottom View ................................................... 12 Figure 3 FPGA Mode Selection Switch ............................................................................. 15 Figure 4: Component Diagram - Top View ....................................................................... 19 Figure 5: Component Diagram - Bottom View .................................................................. 20
TABLE LIST Table 1: FPGA Mode Selection ........................................................................................ 15 Table 2: Board to Board Connector J1 ............................................................................. 16 Table 3: Board to Board Connector J2 ............................................................................. 17 Table 4: Board to Board Connector J3 ............................................................................. 18
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1. INTRODUCTION Scope
The scope of this document is to describe the MultiTech Interface Board TLB which is part of the complete EVB Development Kit (Dev-Kit).
Contact Information, Support For general contact, technical support services, technical questions and report documentation errors contact Telit Technical Support at:
• TS-EMEA@telit.com • TS-AMERICAS@telit.com • TS-APAC@telit.com • TS-SRD@telit.com
Alternatively, use: http://www.telit.com/support For detailed information about where you can buy the Telit modules or for recommendations on accessories and components visit: http://www.telit.com Our aim is to make this guide as helpful as possible. Keep us informed of your comments and suggestions for improvements. Telit appreciates feedback from the users of our information.
mailto:TS-EMEA@telit.commailto:TS-AMERICAS@telit.commailto:TS-APAC@telit.comhttp://www.telit.com/supporthttp://www.telit.com/
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Text Conventions
Danger – This information MUST be followed or catastrophic equipment failure or bodily injury may occur.
Caution or Warning – Alerts the user to important points about integrating the module, if these points are not followed, the module and end user equipment may fail or malfunction.
Tip or Information – Provides advice and suggestions that may be useful when integrating the module.
All dates are in ISO 8601 format, i.e. YYYY-MM-DD.
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Related Documents
Document Title Document Number
LE910C1 HW User Guide 1VV0301298
Generic Evaluation Board Hardware User Guide 1VV0301249
Document Organization Chapter 1: “Introduction” provides a scope for this document, target audience, contact and support information, and text conventions.
Chapter 2: “General description” provides an overview of the document.
Chapter 3: “The FPGA” describes the FPGA component functions.
Chapter 4: “Component assembly diagram” provides layout placement information.
Chapter 5: “120-Pin Board to board connectors” provides B2B pinout.
Chapter 6: “Schematics”.
Chapter 7: “Revision history”
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2. GENERAL DESCRIPTION The MultiTech Interface Board TLB (aka MTB) is custom designed to interface the Telit module variant LE910Cx with the Telit Generic Evaluation Board (EVB) thus forming the complete Development Kit of LE910Cx which allows great flexibility for integrating WIFI, BT and GPS technologies with the LE910Cx.
The MTB provides the mapping of Telit module signals and functions into the generic EVB signals and functions.
The MultiTech Interface Board TLB design includes the following items:
• LE910Cx module • 3x M.2 type mini card slots • Programmable FPGA • RF SMA connectors • Board to Board connectors for interfacing to EVB main board • Module specific circuitry which is not part of the generic circuitry of the EVB.
Power supply and control interface for the cellular module is provided from the EVB via the B2B connectors.
To monitor the temperature, a thermistor is placed on the top GND plane, close to the module which should be representative for the module’s backside temperature.
A programmable FPGA which is included in the MTB provides options for connecting every functional modem pin to the relevant peripheral M.2 cards hence enabling the most flexible way to demo interoperability between the LE910Cx module and peripheral accessories.
A typical example of this capability is in the case where 3x M.2 cards (WIFI module, GNSS module and BT module) are plugged into the M.2 slots while the FPGA is programmed to perform the correct signals mapping between the LE910Cx and the interfaces of each of the M.2 accessories.
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MultiTech Interface Board TLB view The following pictures show the MultiTech Interface Board TLB top and bottom views:
Figure 1: MultiTech Interface Board TLB - Top View
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Figure 2: MultiTech Interface Board TLB - Bottom View
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3. FPGA The FPGA used in this board is a Lattice Semiconductor MACHXO3 family device. More information about this part can be viewed on their web site: http://www.latticesemi.com/en/Products/FPGAandCPLD/MachXO3 The tools to write, compile, place, route, and program the FPGA can be downloaded from Lattice website. The purpose of the FPGA in this board is to provide the maximum flexibility connecting different peripherals of the LE910Cx pins. The board includes a rotary mode selector which is used to select a pre-defined FPGA configuration for mapping the LE910Cx pins to the various peripherals. For each mode, the signals from the module can be muxed to either or all of the M.2 slots or to the main board connectors on the bottom side (for interfacing to the EVB).
Programming the FPGA This section details the steps needed to program/flash the FPGA.
3.1.1. Prerequisites 1. The JEDEC file to be programmed. This is the file uploaded/flashed into the FPGA. 2. Programming tool installed. This “Programmer and Deployment Tool” should be
downloaded from Lattice Semiconductor website: http://www.latticesemi.com/Products/DesignSoftwareAndIP/ProgrammingAndConfigurationSw/Programmer
Perform the following steps to program the FPGA: 1. Power on the module (pressing the ON button on the EVB main board). 2. Launch the “Diamond Programmer” tool. 3. Select “Detect Cable” on the window that pops up:
4. Select Cable and click OK.
5. The main program window will show scanning and searching for the FPGA
component.
http://www.latticesemi.com/en/Products/FPGAandCPLD/MachXO3http://www.latticesemi.com/Products/DesignSoftwareAndIP/ProgrammingAndConfigurationSw/Programmerhttp://www.latticesemi.com/Products/DesignSoftwareAndIP/ProgrammingAndConfigurationSw/Programmer
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6. Press the line below the “File name” and select the JEDEC file location. It is now
recommended to save the programmer window setup. 7. Program the FPGA by selecting the menu icon or by “Design” – “Program”. 8. A successful program sequence should be acknowledged as shown below:
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FPGA Mode Selection As described previously, the board includes a rotary mode selection switch. The switch reference location is SW700. It is a rotary switch with 16 states decoded by the FPGA logic for the different modes needed.
Figure 3 FPGA Mode Selection Switch
The predefined modes currently supported by the FPGA are detailed below: Table 1: FPGA Mode Selection
Mode Switch Selection Functional Mode Description
0 Default 1 Slot1: SDIO, Main UART, WCI UART, DVI
Slot2: SPI 2 Spare 3 Slot1: SDIO
Slot2: Main UART, WCI UART
Slot3: SPI 4 Spare 5 Spare 6 Spare 7 Spare 8 Spare 9 Spare
10 (A) LE910C1: Slot 1 HCI Bluetooth connection to EVB MAIN_UART (for testing only)
11 (B) Spare 12 (C) Spare 13 (D) LE910 V2: SPI, I2C_GPIOs (10-SCL, 8-SDA) AT#I2CWR=8,10,30,4,19 14 (E) LE910 V2: SPI to UART_AUX 15 (F) LE910C1: WIFI SDIO SLOT1 (Normal EVB mode)
Additional modes for supporting new bundling options might be released later
on.
Please contact Telit representative for more information.
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4. 120-PIN BOARD TO BOARD CONNECTORS
1 GND 2 GND 3 4 5 GND 6
7 USB_SS_RX_P 8 GND 9 I2C_SDA 10 TGPIO_06 11 12
13 USB_SS_RX_M 14 GND 15 TGPIO_05 16 I2C_SCL 17 18 GND
19 GND 20 GND 21 VREG_MSME 22 VREG_MSME 23 GND 24
25 USB_SS_TX_P 26 GND 27 28 29 30
31 USB_SS_TX_M 32 GND 33 34 SPI_MOSI 35 36 GND
37 GND 38 39 40 TGPIO_04 41 GND 42
43 SPI_CS 44 TGPIO_02 45 TGPIO_03 46 SPI_MISO 47 48
49 VAUX/PWRMON 50 VAUX/PWRMON 51 52 SPI_CLK 53 54
55 TGPIO_08 56 TGPIO_07 57 TGPIO_01 58 TGPIO_09 59 60
61 62 TGPIO_10 63 64 TGPIO_20 65 66
67 VMMC 68 VMMC 69 MMC_CD 70 MMC_DAT3 71 72
73 MMC_DAT0 74 MMC_DAT2 75 MMC_CLK 76 MMC_DAT1 77 78
79 GND 80 GND 81 C107/DSR 82 MMC_CMD 83 84
85 86 87 88 89 TX_AUX 90
91 92 93 94 95 RX_AUX 96
97 98 99 100 WCI_TX 101 WCI_RX 102
103 C125/RING 104 RFCLK2_QCA 105 WLAN_SLEEP_CLK 106 C105/RTS 107 108
109 C104/RXD 110 C109/DCD 111 C103/TXD 112 C106/CTS 113 C108/DTR 114
115 116 117 118 119 120
Table 2: Board to Board Connector J1
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1 GPS_LNA_BIAS 2 GND 3 GPS_LNA_EN 4 5 GND 6
7 GND 8 GND 9 GND 10 GND 11 GND 12
13 14 15 GND 16 17 18
19 GND 20 GND 21 GND 22 GND 23 GND 24 GND
25 26 27 GND 28 29 30 GND
31 32 33 34 35 36
37 GND 38 GND 39 40 41 GND 42 GND
43 44 GND 45 GND 46 GND 47 GND 48 GND
49 50 GND 51 GND 52 ADC_IN3 53 ADC_IN2 54 ADC_IN1
55 56 57 58 59 60
61 DVI_RX 62 DVI_TX 63 DVI_CLK 64 DVI_WAO 65 REF_CLK 66 GND
67 GND 68 GND 69 GND 70 GND 71 GND 72
73 GND 74 GND 75 GND 76 GND 77 SIMVCC1 78 SIMVCC1
79 HSIC_STB 80 HSIC_DATA 81 SIMCLK1 82 SIMIN1 83 SIMIO1 84 SIMRST1
85 86 VRTC 87 88 89 SIMVCC2 90 SIMVCC2
91 USB_VBUS 92 USB_ID 93 SIMIN2 94 SIMIO2 95 SIMRST2 96 SIMCLK2
97 GND 98 GND 99 100 101 102
103 USB_D+ 104 GND 105 106 107 108
109 USB_D- 110 GND 111 112 113 114
115 GND 116 GND 117 118 119 120
Table 3: Board to Board Connector J2
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1 VBATT 2 VBATT 3 VBATT 4 VBATT_PA 5 VBATT_PA 6 VBATT_PA
7 VBATT 8 VBATT 9 VBATT 10 VBATT_PA 11 VBATT_PA 12 VBATT_PA
13 VBATT 14 VBATT 15 VBATT 16 VBATT_PA 17 VBATT_PA 18 VBATT_PA
19 20 21 22 VBATT_PA 23 VBATT_PA 24 VBATT_PA
25 26 27 28 29 30
31 32 33 34 35 36
37 38 39 40 41 42
43 44 45 46 47 48
49 50 51 52 53 54
55 56 57 58 59 60
61 62 63 64 65 66 D8_THERM_ASTAR
67 68 69 70 71 72
73 74 75 76 77 78
79 GND 80 GND 81 GND 82 GND 83 GND 84 GND
85 GND 86 GND 87 GND 88 GND 89 GND 90 GND
91 RESET 92 ON_OFF 93 STAT_LED 94 95 SW_RDY 96 SHDN
97 GND 98 GND 99 GND 100 GND 101 102
103 GPS_SYNC 104 GPS_RFPAON 105 GPS_CLK 106 GND 107 108
109 GND 110 GND 111 GND 112 GND 113 JTAG_TDI 114 JTAG_PS_HOLD
115 JTAG_TMS 116 JTAG_TDO 117 JTAG_TRST 118 JTAG_TCK 119 JTAG_RTCK 120 JTAG_RESOUT
Table 4: Board to Board Connector J3
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5. COMPONENT ASSEMBLY DIAGRAM
Searchable Layout:
Figure 4: Component Diagram - Top View
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2
1
1
1
22
23
32
33
1
1
1
74
75
14
15
12
13
10
11
8
9
7
5
6
3
4
1
2
2
1
K K
A B
1
1
C D
3222
3323
E F G H
1
KJ
1
1
L M
74
75
N P
1
R
1
1
1
+K
11
+1
1
X400
L401
R403
J401
L400
R707
R708
TP605
C607
R613
R616
R615
M400
J400
SW700
R610
R611
R612
U601
R614 TP604
TP609
TP610
R205
R201
R203
TP606
U200TP607
R204
R202
TP608
X3
X401
L403
R404
J402
L402
C211
C212
C213
Q600
D600
R706
R705
R206
L201
Q601
D601
R619 R620
X300
L301
R311
J301
L300
R600
C703
C701
C700
R602
R700
R701
R702
J300
C603
C602
C601
C702
C606
C605
C600
C710
C709
M300
C707
C708
C706
C705
U100
X2
X301
C811
C810
C808
C100
5C8
05
C806
C804
C100
7
C100
4
C801
C803
C800
L303
R312
J302
L302
C809
R805
R806
C807
C100
3
C100
2
C100
1
C100
0
R803
R804
C802
R801
R800
R304
R305
R307
R308
C100
6
R303
R306
R310
R309
RT200
X500
L501
R502
J501
L500
R807
R101
0
R101
2
R100
3
C101
5
C101
6
C102
2
C101
8R1
002
R101
6
C207
J500
C101
7
R1008R10
11
U1002
L1000
R1013
U100
0
C1021R1017
C204
L200
X1
M500
Q1000
R1005
C101
4
R1014
C101
9
C102
0
R1018
R1015
C203 D201
D1000
R100
9
C200
R215
C205 D202
C201
R213
R214
R216
C202
C208
D200
D204
-
U905
115
P900
1
120
6 120
6
115
1
11
6
1234ABCDEFGHJKLMNPRT
1
1
5678910111213141516
2
1
1
120
115
10
9
C403
C402
J2
R402
C206
D203
C400
C401
R401
R400
C713
R1006
U702
C714
C303C302
TP709TP710
TP711TP712
C712
C711
R209
R210
R211
TP600
TP601
TP602
U600
R709 TP700
TP701
U701
U700
J1
R301
R302
R212
R601
R605
R618
R617
R703
R711
R710
TP705
C914
R704
C915
R604
R609
R607
R606
R300
Y600R603
TP806
TP708
TP702
TP703
TP704
TP706
R208
R207
C301
C300
R608
C604
TP801TP802
TP800
R802
TP805
TP804TP803
TP707
J900
U901
R903R901
R200 R100
4
C1012
C1011
C922 R910
C910 R900
C503
C502
U100
1
C1010
C903
R905
C913
U904
C918
C919
C101
3C1
009
C100
8R1
001
R100
0
C901
C900
L900
U903
C902
R911
R907
R503
C908
R902
R904
R906
C912
R908 R912
U902
C907
C920
C921
L902
C916
R909
R501
R500
C923
J3
L901
U900
R913
C909
Y900
C904
C911
C917
C501
C500
R100
7
C905
C906
CS1868A-SKP
CS1868A-SKS
AishwaryaNaFile Attachment
AishwaryaNaStamp
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Figure 5: Component Diagram - Bottom View
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6. SCHEMATICS
Searchable PDF:
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5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
Block Diagram
1 11
Dror G.
0502LE910C1
CS1868A
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
Block Diagram
1 11
Dror G.
0502LE910C1
CS1868A
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
Block Diagram
1 11
Dror G.
0502LE910C1
CS1868A
-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
AUX UART in LE910 {
VBATT_PA
VBATT
ADC_IN1{3}
RSVD_D3{3}RSVD_E3{3}
RSVD_G3{3}
ADC_IN2{3}
SGMII_RX_M{3}SGMII_RX_P{3}
RSVD_C4{3}RSVD_C5{3}
SGMII_TX_P{3}
USB_VBUS{3}
SGMII_TX_M{3}
RSVD_C6{3}
DVI_RX{8}DVI_TX{8}
ADC_IN3{3}
RSVD_N7 {3}
RSVD_P7 {8}
GPS_LNA_EN {3}DVI_CLK{8}
TGPIO_01{8}
USB_SS_TX_M{3}
RSVD_N8 {3}
DVI_WAO{8}
TGPIO_02{8}
USB_SS_TX_P{3}
I2C_SDA{3,4,5,6,7,8}
TGPIO_03{8}
USB_SS_RX_P{3}
RFCLK2_QCA {3}
VAUX_PWRMON {3,11}
RESET_N{3}
WLAN_SLEEP_CLK {8}
ON_OFF_N{3}
WIFI_SDRST {8}
TGPIO_06{8}
REF_CLK{8}
HSIC_DATA{3}HSIC_STB{3}
I2C_SCL{3,4,5,6,7,8}
TGPIO_04{8}
USB_SS_RX_M{3}
TGPIO_07{8}
VREG_MSME {3,8}
WIFI_SD3 {4}
WIFI_SD0 {4}
WIFI_SD2 {4}
WIFI_SDCLK {4}
WIFI_SD1 {4}
WIFI_SDCMD {4}
SHDN_N{3}
USB_ID{3}
TGPIO_05{8}
VRTC {3}
SPI_CS_N{8}
RTS{8}
DTR{3}DCD{3}
RING{3}
DSR{3}CTS{8}
TXD{8}RXD{8}
TGPIO_09{3,8}TGPIO_08{8}
TGPIO_10{8}
SPI_CLK{8}
SPI_MISO{8}SPI_MOSI{8} USB_DP{3}
USB_DN{3}
RSVD_C3{3}
WCI_TXD {8}WCI_RXD {3,8}
SIMVCC1 {3}SIMCLK1 {3}SIMIN1 {3}SIMIO1 {3}SIMRST1 {3}
SIMVCC2 {3}SIMCLK2 {3}SIMIN2 {3}SIMIO2 {3}SIMRST2 {3}
VMMC {3}
MMC_CLK {3}MMC_CMD {3}
MMC_DATA0 {3}MMC_DATA1 {3}MMC_DATA2 {3}MMC_DATA3 {3}
MMC_CD {3}
ANT {3}
ANT_DIV {3}
ANT_GPS {3}
RSVD_J4 {8}
RSVD_M5 {8}
GPS_SYNC {8}
RSVD_K4{3,8}RSVD_L4{3,8}
RSVD_M7{3}
Drawing Title:
Size PCB Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
CS1868A A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
Modem
2 11
Dror G.
0502LE910C1
Drawing Title:
Size PCB Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
CS1868A A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
Modem
2 11
Dror G.
0502LE910C1
Drawing Title:
Size PCB Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
CS1868A A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
Modem
2 11
Dror G.
0502LE910C1
*LE910C1 onlyLE910C1-AP
U100B
VUSBA13
*USB_SS_TX_PD9
*USB_SS_TX_MD8
*USB_SS_RX_PD10
*USB_SS_RX_MD11
*USB_IDA14
USB_D-C15 USB_D+B15
RSVD_J4J4
ON_OFF_NR12
RSVD_P12/ON_OFFP12
RSVD_C7C7 RSVD_F3F3
RSVD_C5C5
RSVD_E3E3 RSVD_C6C6
RSVD_D3D3
RSVD_G3G3
HW_SHUTDOWN_NR13
RSVD_D12D12
ANT_MAINK1
ANT_GPSR9
ANT_DIVF1
*RFU_R4/ANT_2R4
*ADC_IN3D7 *ADC_IN2H4 ADC_IN1B1
RSVD_P11P11
RSVD_C4C4
RSVD_C3C3
*HSIC_DATAA12 *HSIC_STBA11
RSVD_M5M5
*LE910C1 only
LE910C1-AP
U100A
*WLAN_SLEEP_CLKM11
*WIFI_SDRSTL12
WIFI_SDCMDN13WIFI_SDCLKL13
WIFI_SD3H13WIFI_SD2K13WIFI_SD1M13WIFI_SD0J13
WCI_TXDM8
WCI_RXDM9
*VMMCF13
RSVD_K4K4
RSVD_M7M7 GPIO_10
G15 GPIO_09L15 GPIO_08K15 GPIO_07C13 GPIO_06C12 GPIO_05B14 GPIO_04C11 GPIO_03C10 GPIO_02C9 GPIO_01C8
RSVD_J15/SPI_SRDYJ15 RSVD_H15/SPI_MRDYH15
SPI_MOSI/TX_AUXD15
SPI_MISO/RX_AUXE15
*SPI_CS/GPIO_11H14
SPI_CLKF15
*SIMVCC2D2
SIMVCC1A3
*SIMRST2D1
SIMRST1A7
*SIMIO2C2
SIMIO1A5
*SIMIN2G4
SIMIN1A4
*SIMCLK2C1
SIMCLK1A6
*SGMII_TX_PD5
*SGMII_TX_MD6
*SGMII_RX_PE4
*SGMII_RX_MF4
RSVD_L4L4
*RFCLK2_QCAM10
*SD_MMC_DAT3H12*SD_MMC_DAT2K12*SD_MMC_DAT1G12*SD_MMC_DAT0E12
*SD_MMC_CMDJ12*SD_MMC_CLKF12
*SD_MMC_CDG13
*I2C_SDAB10 *I2C_SCLB11
*GPS_SYNCN9
RSVD_N8N8
GPS_LNA_ENR7
RSVD_N7N7
RSVD_P7P7
RSVD_J14J14
RSVD_K14K14
DVI_WAOB9 DVI_TXB7 DVI_RXB6 DVI_CLKB8
C125/RINGR14 C109/DCDN14 C108/DTRM14 C107/DSRP14 C106/CTSP15 C105/RTSL14 C104/RXDM15 C103/TXDN15
REF_CLKB12
LE910C1-AP
U100E
RSVD_N12N12
RSVD_N11N11
RSVD_N10N10
RSVD_M6M6
RSVD_L3L3
RSVD_K3K3
RSVD_J3J3
RSVD_H3H3
RSVD_G14G14
RSVD_F14F14
RSVD_D14D14
RSVD_D13D13
RSVD_B5B5
RSVD_B4B4
RSVD_B3B3
RSVD_B2B2
RSVD_A9A9
RSVD_A8A8
RSVD_A10A10
*LE910C1 only
LE910C1-AP
U100C
VBATT_PA_P2P2 VBATT_PA_P1P1
VBATT_PA_N2N2 VBATT_PA_N1N1
VBATT_M2M2 VBATT_M1M1
RSVD_C14/VRTCC14
VIO_1V8E13
VAUX/PWRMONR11
LE910C1-AP
U100D
GND_R8R8
GND_R6R6
GND_R5R5
GND_R3R3
GND_R2R2
GND_R10R10
GND_P9P9
GND_P8P8
GND_P6P6
GND_P5P5
GND_P4P4
GND_P3P3
GND_P13P13
GND_P10P10
GND_N6N6
GND_N5N5
GND_N4N4
GND_N3N3
GND_M4M4
GND_M3M3
GND_M12M12
GND_L2L2
GND_L1L1
GND_K2K2
GND_J9J9
GND_J8J8
GND_J7J7
GND_J2J2
GND_J1J1
GND_H9H9
GND_H8H8
GND_H7H7
GND_H2H2
GND_H1H1
GND_G9G9
GND_G8G8
GND_G7G7
GND_G2G2
GND_G1G1
GND_F2F2
GND_E2E2
GND_E14E14
GND_E1E1
GND_D4D4
GND_B13B13
GND_A2A2
-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
To enable OTG power supply feature:Remove R204 and assemble R202
USB OTG Driver
For LE910C1 OTG detection
WIFI_SDCLK
WIFI_SD3WIFI_SD2
WIFI_SD1WIFI_SD0
WIFI_SDCMDWIFI_SDRST
Audio
RGMII
SIM2
SIM1
USB_SS
SGMII PCIe
WIFI MMC
VBATT_PAVBATT
B2B Connector Placement(Top View)
J1
J2 J3
VBATT
VBATT_PA
VBATT
MB_TGPIO_06{7}
MB_TGPIO_05{7}
MB_TGPIO_04{7}
MB_TGPIO_02{7}MB_TGPIO_03{7}
MB_TGPIO_08{3,7}MB_TGPIO_07{7}MB_TGPIO_01{3,7}MB_TGPIO_09{7}
I2C_SDA{2,4,5,6,7,8}
I2C_SCL{2,4,5,6,7,8}
DTR {2}
DCD {2}
MB_TGPIO_10 {7}
MMC_CMD {2}DSR {2}
MMC_DATA1 {2}
MMC_DATA2 {2}MMC_DATA0 {2}
MMC_DATA3 {2}
TGPIO_09 {2,8} MB_DVI_WAO {7}MB_DVI_CLK {7}
USB_VBUS {2}USB_ID {2}
SIMIO2 {2}
USB_DP {2}
USB_DN {2}
SIMIO1 {2}
RSVD_E3 {2}
RSVD_C6 {2}
RSVD_C5 {2}
RSVD_C4 {2}RSVD_D3 {2}
RSVD_C3 {2}
RSVD_N7 {2}RSVD_N8 {2}MB_GPS_PPS {7}
HSIC_DATA {2}HSIC_STB {2}
ANT {2} ANT_DIV {2} ANT_GPS {2}
RSVD_G3 {2}
RSVD_M7 {2}
MB_RSVD_J4 {7}
MB_RSVD_M5 {7}
MB_TGPIO_08 {3,7}
MB_TGPIO_01 {3,7}
RSVD_K4 {2,8}
RSVD_L4 {2,8}
MB_SPI_MOSI{7}
MB_SPI_MISO{7}
MB_SPI_MOSI_AUX {7}
MB_SPI_MISO_AUX {7}
SHDN_N {2}
ON_OFF_N {2}RESET_N {2}
SIMCLK2 {2}SIMRST2 {2}
SIMIN2 {2}
SIMVCC2 {2}
VRTC {2}
SIMRST1 {2}
SIMIN1 {2}SIMCLK1 {2}
SIMVCC1 {2}
MB_REF_CLK {7}
MB_DVI_TX {7}MB_DVI_RX {7}
ADC_IN3{2}ADC_IN2{2}ADC_IN1{2}
GPS_LNA_BIAS
GPS_LNA_EN{2}
MB_TXD {7}
MB_RXD {7}
MB_CTS {7}
MB_RTS {7}MB_WLAN_SLEEP_CLK {7}RFCLK2_QCA {2}RING {2}
WCI_RXD {2,8}
MB_WCI_TXD {7}MB_WCI_RXD {7}
MMC_CLK {2}
MMC_CD {2}
VMMC {2}
MB_SPI_CLK{7}
VAUX_PWRMON{2,11}
MB_SPI_CS_N{7}
VREG_MSME{2,8}
USB_SS_TX_P{2}
USB_SS_TX_M{2}
USB_SS_RX_M{2}
USB_SS_RX_P{2}
SGMII_TX_M{2}
SGMII_RX_M{2}
SGMII_RX_P{2}
SGMII_TX_P{2}
Drawing Title:
Size PCB Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
CS1868A A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
Board to Board Connectors
3 11
Dror G.
0502LE910C1
Drawing Title:
Size PCB Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
CS1868A A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
Board to Board Connectors
3 11
Dror G.
0502LE910C1
Drawing Title:
Size PCB Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
CS1868A A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
Board to Board Connectors
3 11
Dror G.
0502LE910C1
R207 0DNP
FID1FIDUCIAL
C2131nF
040250V
R211 0DNP
L2014.7uH2016
20%1.1A
J3
SEAM-20-09.0-L-06-2-A-K
120120
119119
118118
117117
116116
115115
114114
113113
112112
111111
110110
109109
108108
107107
106106
105105
104104
103103
102102
101101
100100
9999
9898
9797
9696
9595
9494
9393
9292
9191
9090
8989
8888
8787
8686
8585
8484
8383
8282
8181
8080
7979
7878
7777
7676
7575
7474
7373
7272
7171
7070
6969
6868
6767
6666
6565
6464
6363
6262
6161
11
22
33
44
55
66
77
88
99
1010
1111
1212
1313
1414
1515
1616
1717
1818
1919
2020
2121
2222
2323
2424
2525
2626
2727
2828
2929
3030
3131
3232
3333
3434
3535
3636
3737
3838
3939
4040
4141
4242
4343
4444
4545
4646
4747
4848
4949
5050
5151
5252
5353
5454
5555
5656
5757
5858
5959
6060
X1SMA
1
2 3 4 5
C2061nF
040250V
R203 00402
DNP
C2021nF
040250V
FID2FIDUCIAL
C20733pF
0402
50V
R215 0DNP
t
RT20010K
04021%
J1
SEAM-20-09.0-L-06-2-A-K
120120
119119
118118
117117
116116
115115
114114
113113
112112
111111
110110
109109
108108
107107
106106
105105
104104
103103
102102
101101
100100
9999
9898
9797
9696
9595
9494
9393
9292
9191
9090
8989
8888
8787
8686
8585
8484
8383
8282
8181
8080
7979
7878
7777
7676
7575
7474
7373
7272
7171
7070
6969
6868
6767
6666
6565
6464
6363
6262
6161
11
22
33
44
55
66
77
88
99
1010
1111
1212
1313
1414
1515
1616
1717
1818
1919
2020
2121
2222
2323
2424
2525
2626
2727
2828
2929
3030
3131
3232
3333
3434
3535
3636
3737
3838
3939
4040
4141
4242
4343
4444
4545
4646
4747
4848
4949
5050
5151
5252
5353
5454
5555
5656
5757
5858
5959
6060
+ C200470uF10VCONT-E
U200
LTC3529EDCB
VIN8
RESET7 SNSGND
6
EPAD9
SW2
SHDN3
FAULT5
VOUT1
PGND4
D20450pF040230%
FID3FIDUCIAL
R209 0DNP
J2
SEAM-20-09.0-L-06-2-A-K
120120
119119
118118
117117
116116
115115
114114
113113
112112
111111
110110
109109
108108
107107
106106
105105
104104
103103
102102
101101
100100
9999
9898
9797
9696
9595
9494
9393
9292
9191
9090
8989
8888
8787
8686
8585
8484
8383
8282
8181
8080
7979
7878
7777
7676
7575
7474
7373
7272
7171
7070
6969
6868
6767
6666
6565
6464
6363
6262
6161
11
22
33
44
55
66
77
88
99
1010
1111
1212
1313
1414
1515
1616
1717
1818
1919
2020
2121
2222
2323
2424
2525
2626
2727
2828
2929
3030
3131
3232
3333
3434
3535
3636
3737
3838
3939
4040
4141
4242
4343
4444
4545
4646
4747
4848
4949
5050
5151
5252
5353
5454
5555
5656
5757
5858
5959
6060
R20400402
R213 0DNP
R208 0
C2081nF
040250V
DNP
R201100K
04021%
DNP
D20150pF040230%
R206 00402
DNP
R20500402
D20250pF040230%
R216 0
L20047nH 0402
5% 210mA
R202 00402
DNP
R200 0DNP
X2SMA
1
2 3 4 5
R212 0
C20427pF 0402
50V
FID4FIDUCIAL
R210 0
C21210uF
060310V
C2031nF
040250V
C2051nF
040250V
D20350pF040230%
X3SMA
1
2 3 4 5
R214 0
D20050pF040230%
C211 4.7uF040210V
+ C201470uF10VCONT-E
TX_AUX
RX_AUX SW_RDY
STAT_LED
GPS_LNA_BIAS
THERM_ASTAR
SHDN_N
RESET_N
ON_OFF_N
RSVD_C3
VREG_MSME
ADC_IN1 USB_ID
MB_TGPIO_04MB_TGPIO_10
VREG_MSME
USB_VBUS
SW_RDY
STAT_LED
-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
M.2 Slot #1 (Key E)
SLT1_3.3V
SLT1_3.3V
VCCIO3
SLT1_SUSCLK_32K{9}
SLT1_WCI_TX{9}
SLT1_WCI_RX{9}
SLT1_COEX3{9}
SLT1_PRSNT_N{7}
SLT1_RTS{9}
SLT1_CTS{9}
SLT1_TXD{9}
SLT1_WIFI_SDRST {9}SLT1_RXD{9}
SLT1_WIFI_HOST_WAKE_N {9}
WIFI_SD3 {2}
WIFI_SD2 {2}
WIFI_SD1 {2}SLT1_DVI_TX{9}
WIFI_SD0 {2}SLT1_DVI_RX{9}
WIFI_SDCMD {2}SLT1_DVI_WAO{9}
WIFI_SDCLK {2}SLT1_DVI_CLK{9}
SLT1_LED1_N{9}
SLT1_LED2_N{9}
SLT1_RST_N{9}
SLT1_ALERT_N{9}
SLT1_WDIS1_N{9}
SLT1_WDIS2_N{9}
I2C_SDA{2,3,5,6,7,8}
I2C_SCL{2,3,5,6,7,8}
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
M.2 Slot #1 Key "E"
4 11
Dror G.
0502LE910C1
CS1868A
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
M.2 Slot #1 Key "E"
4 11
Dror G.
0502LE910C1
CS1868A
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
M.2 Slot #1 Key "E"
4 11
Dror G.
0502LE910C1
CS1868A
L30047nH
04025%
DNP
R310 0
M.2(NGFF) KEY "E"
J3002199230-4
GND13.3 V
23.3 V
4 USB_D-5LED_1# (I)(OD)
6 GND7PCM_CLK/I2S SCK (I/O)(0/1.8V)
8 SDIO CLK/SYSCLK (O)(0/1.8V)9PCM_SYNC/I2S WS (I/O)(0/1.8V)
10 SDIO CMD(I/O)(0/1.8V)11PCM_IN/I2S SD_IN (I)(0/1.8V)
12 SDIO DATA0(I/O)(0/1.8V)13PCM_OUT/I2S SD_OUT (O)(0/1.8V)
14 SDIO DATA1(I/O)(0/1.8V)15LED_2# (I)(OD)
16 SDIO DATA2(I/O)(0/1.8V)17GND
18 SDIO DATA3(I/O)(0/1.8V)19UART WAKE# (I)(0/3.3V)
20 SDIO WAKE# (I)(0/1.8V)21UART RXD (I)(0/1.8V)
22 SDIO RESET#/TX_BLANKING (O)(0/1.8V)23
UART TXD (O)(0/1.8V)32 GND
33UART CTS (I)(0/1.8V)34 PETp0
35UART RTS (O)(0/1.8V)36 PETn0
37VENDOR DEFINED38 GND
39VENDOR DEFINED40 PERp0
41VENDOR DEFINED42 PERn0
43COEX3 (I/O)(0/1.8V)44 GND
45COEX_RXD (I)(0/1.8V)46 REFCLKp0
47COEX_TXD (O)(0/1.8V)48 REFCLKn0
49SUSCLK(32kHz) (O)(0/3.3V)50 GND
51PERST0# (O)(0/3.3V)52 CLKREQ0# (I/O)(0/3.3V)
53W_DISABLE2# (O)(0/3.3V)54 PEWAKE0# (I/O)(0/3.3V)
55W_DISABLE1# (O)(0/3.3V)56 GND
57I2C_DATA (I/O)(0/1.8 V)58 RESERVED/PETp1
59I2C_CLK (O)(0/1.8 V)60 RESERVED/PETn1
61ALERT# (I)(0/1.8 V)62 GND
63RESERVED64 RESERVED/PERp1
65UIM_SWP/PERST1#66 RESERVED/PERn1
67UIM_POWER_SNK/CLKREQ1#68 GND
69UIM_POWER_SRC/GPIO_1/PEWAKE1#70 RESERVED/REFCLKp1
713.3 V72 RESERVED/REFCLKn1
733.3 V74 GND
75
USB_D+3
MECH176
MECH277
R305 0
M300STANDOFF
C30010uF
060310V
R303 0
C301100nF
040225V
X300
SMA_VERT_TH
1
2345
R308 0
R312 00402
X301
SMA_VERT_TH
1
2345
R306 0
C30210uF
060310V
R300 0
R309 0
R304 0
R302 0
J3011
1
2
2
3
3
R301 0
L30247nH
04025%
DNP
R311 00402
J3021
1
2
2
3
3
R307 0
L30147nH
04025%
DNPL30347nH
04025%
DNP
C303100nF
040225V
SLT1_SMA_ANT1 SLT1_SMA_ANT2
SLT1_I2C_SCL
SLT1_I2C_SDA
SLT1_VDDIO_WLAN
SLT1_WIFI_SD3
SLT1_WIFI_SD2
SLT1_WIFI_SD1
SLT1_WIFI_SD0
SLT1_WIFI_SDCMD
SLT1_WIFI_SDCLK
-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
M.2 Slot #2 (Key E)
SLT2_3.3V
SLT2_3.3V
VCCIO2
SLT2_SPI_CS_N {8}
SLT2_SUSCLK_32K{8}
SLT2_WCI_TX{8}
SLT2_WCI_RX{8}
SLT2_COEX3{8}
SLT2_PRSNT_N{7}
SLT2_RTS{8}
SLT2_CTS{8}
SLT2_TXD{8}
SLT2_WIFI_SDRST {8}SLT2_RXD{8}
SLT2_HOST_IRQ_N {8}
SLT2_SPI_CLK {8}
SLT2_SPI_MISO {8}SLT2_DVI_TX{8}
SLT2_DVI_RX{8}
SLT2_DVI_WAO{8}
SLT2_DVI_CLK{8}
SLT2_SPI_MOSI {8}
SLT2_LED1_N{8}
SLT2_LED2_N{8}
SLT2_RST_N{8}
SLT2_ALERT_N{8}
SLT2_WDIS1_N{8}
SLT2_WDIS2_N{8}
I2C_SCL{2,3,4,6,7,8}
I2C_SDA{2,3,4,6,7,8}
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
M.2 Slot #2 Key "E"
5 11
Dror G.
0502LE910C1
CS1868A
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
M.2 Slot #2 Key "E"
5 11
Dror G.
0502LE910C1
CS1868A
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
M.2 Slot #2 Key "E"
5 11
Dror G.
0502LE910C1
CS1868A
X400
SMA_VERT_TH
1
2345
M400STANDOFF
X401
SMA_VERT_TH
1
2345
J4021
1
2
2
3
3L40147nH
04025%
DNP
J4011
1
2
2
3
3
R402 0
L40047nH
04025%
DNP
R404 00402
R400 0
C40210uF
060310V
L40247nH
04025%
DNP
M.2(NGFF) KEY "E"
J4002199230-4
GND13.3 V
23.3 V
4 USB_D-5LED_1# (I)(OD)
6 GND7PCM_CLK/I2S SCK (I/O)(0/1.8V)
8 SDIO CLK/SYSCLK (O)(0/1.8V)9PCM_SYNC/I2S WS (I/O)(0/1.8V)
10 SDIO CMD(I/O)(0/1.8V)11PCM_IN/I2S SD_IN (I)(0/1.8V)
12 SDIO DATA0(I/O)(0/1.8V)13PCM_OUT/I2S SD_OUT (O)(0/1.8V)
14 SDIO DATA1(I/O)(0/1.8V)15LED_2# (I)(OD)
16 SDIO DATA2(I/O)(0/1.8V)17GND
18 SDIO DATA3(I/O)(0/1.8V)19UART WAKE# (I)(0/3.3V)
20 SDIO WAKE# (I)(0/1.8V)21UART RXD (I)(0/1.8V)
22 SDIO RESET#/TX_BLANKING (O)(0/1.8V)23
UART TXD (O)(0/1.8V)32 GND
33UART CTS (I)(0/1.8V)34 PETp0
35UART RTS (O)(0/1.8V)36 PETn0
37VENDOR DEFINED38 GND
39VENDOR DEFINED40 PERp0
41VENDOR DEFINED42 PERn0
43COEX3 (I/O)(0/1.8V)44 GND
45COEX_RXD (I)(0/1.8V)46 REFCLKp0
47COEX_TXD (O)(0/1.8V)48 REFCLKn0
49SUSCLK(32kHz) (O)(0/3.3V)50 GND
51PERST0# (O)(0/3.3V)52 CLKREQ0# (I/O)(0/3.3V)
53W_DISABLE2# (O)(0/3.3V)54 PEWAKE0# (I/O)(0/3.3V)
55W_DISABLE1# (O)(0/3.3V)56 GND
57I2C_DATA (I/O)(0/1.8 V)58 RESERVED/PETp1
59I2C_CLK (O)(0/1.8 V)60 RESERVED/PETn1
61ALERT# (I)(0/1.8 V)62 GND
63RESERVED64 RESERVED/PERp1
65UIM_SWP/PERST1#66 RESERVED/PERn1
67UIM_POWER_SNK/CLKREQ1#68 GND
69UIM_POWER_SRC/GPIO_1/PEWAKE1#70 RESERVED/REFCLKp1
713.3 V72 RESERVED/REFCLKn1
733.3 V74 GND
75
USB_D+3
MECH176
MECH277
C400100nF
040225V
R401 0
L40347nH
04025%
DNP
C403100nF
040225V
C40110uF
060310V
R403 00402
SLT2_SMA_ANT1 SLT2_SMA_ANT2
SLT2_VDDIO_WLAN
SLT2_I2C_SCL
SLT2_I2C_SDA
-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
M.2 Slot #3 (Key B)
{Active as AUX UART in LE910
SLT3_3.3V
SLT3_3.3V
VCCIO5 SLT3_PRSNT_N{7}
SLT3_LED1_N{9}
SLT3_WDIS1_N{9}
SLT3_OFF_N{9}
SLT3_IRQ_N{9}
SLT3_TX_BLANK{9}
SLT3_SPI_CS_N{9}
SLT3_SPI_MISO{9}
SLT3_SPI_MOSI{9}
SLT3_SPI_CLK{9}
SLT3_RXD{9}
SLT3_TXD{9}
SLT3_BOOT{9}
SLT3_SUSCLK_32K{9}
SLT3_RST_N {9}
I2C_SCL{2,3,4,5,7,8}
I2C_SDA{2,3,4,5,7,8}
SLT3_SYNC{9}
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
M.2 Slot #3 Key "B"
6 11
Dror G.
0502LE910C1
CS1868A
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
M.2 Slot #3 Key "B"
6 11
Dror G.
0502LE910C1
CS1868A
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
M.2 Slot #3 Key "B"
6 11
Dror G.
0502LE910C1
CS1868A
R503 0
L50047nH
04025%
DNP
R502 00402
M500STANDOFF
J5011
1
2
2
3
3
R501 0
C50210uF
060310V
L50147nH
04025%
DNP
C503100nF
040225V
R500 0
X500
SMA_VERT_TH
1
2345
C50010uF
060310V
C501100nF
040225V
M.2(NGFF) KEY "B"
J5002199230-5
CONFIG_313.3V
23.3V
4 GND5FULL_CARD_POWER_OFF# (O)(0/1.8V or 3.3V)
6 USB_D+7W_DISABLE1# (O)(0/3.3V)
8 USB_D-9GPIO_9/DAS/DSS# (I/O)/LED1#(I)(0/3.3V)
10 GND11
GPIO_5 (I/O)(0/1.8V)20
GPIO_6 (I/O)(0/1.8V)22
CONFIG_021
GPIO_7 (I/O) (0/1.8V)24
GPIO_11 (I/O) (0/1.8V)23
GPIO_10 (I/O) (0/1.8V)26
DPR (O) (0/1.8V)25
GPIO_8 (I/O) (0/1.8V)28
GND27
UIM-RESET (I)30
PERn1/USB3.1-Rx-/SSIC-RxN29
UIM-CLK (I)32
PERp1/USB3.1-Rx+/SSIC-RxP31
UIM-DATA (I/O)34
GND33
UIM-PWR (I)36
PETn1/USB3.1-Tx-/SSIC-TxN35
DEVSLP (O)38
PETp1/USB3.1-Tx+/SSIC-TxP37
GPIO_0 (I/O)/SMB_CLK (I/O)/(0/1.8V)40
GND39
GPIO_1 (I/O)/SMB_DATA (I/O)/(0/1.8V)42
PERn0/SATA-B+41
GPIO_2 (I/O)/ALERT# (I)/(0/1.8V)44
PERp0/SATA-B-43
GPIO_3 (I/O)(0/1.8V)46
GND45
GPIO_4 (I/O)(0/1.8V)48
PETn0/SATA-A-47
PERST# (O)(0/3.3V)50
PETp0/SATA-A+49
CLKREQ# (I/O)(0/3.3V)52
GND51
PEWAKE# (I/O)(0/3.3V)54
REFCLKn53
NC_5656
REFCLKp55
NC_5858
GND57
COEX3 (I/O)(0/1.8V)60
ANTCTL0 (I)(0/1.8V)59
COEX_TXD (O)(0/1.8V)62
ANTCTL1 (I)(0/1.8V)61
COEX_RXD (I)(0/1.8V)64
ANTCTL2 (I)(0/1.8V)63
SIM DETECT (O)66
ANTCTL3 (I)(0/1.8V)65
SUSCLK(32kHz) (O)(0/3.3V)68
RESET# (O)(0/1.8V)67
3.3V70
CONFIG_169
3.3V72
GND71
3.3V74
GND73
GND3
CONFIG_275
MECH277
MECH176
SLT2_SMA_ANT2
SLT3_I2C_SCL
SLT3_I2C_SDA
SLT3_VDDIO
-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
To/From MAIN BOARD
LED2
Status LEDs
LED1I2C I/O Expanderfor slot card detectionDoes not exist in LE910,
Add analog mux to GPIO to act as I2C
VCCIO0
VCCIO01.8V
3.3V
1.8V
VCCIO0
VCCIO0
VBATTVBATT
FPGA_TMS {10}FPGA_TDI {10}
FPGA_TCK {10}
FPGA_TDO {10}
SLT1_PRSNT_N {4}SLT2_PRSNT_N {5}SLT3_PRSNT_N {6}
I2C_SCL{2,3,4,5,6,8}I2C_SDA{2,3,4,5,6,8}
MB_TGPIO_06 {3}MB_TGPIO_05 {3}
MB_SPI_MOSI {3}
MB_TGPIO_04 {3}
MB_SPI_CS_N {3}
MB_TGPIO_02 {3}MB_TGPIO_03 {3}
MB_SPI_MISO {3}MB_SPI_CLK {3}
MB_TGPIO_08 {3}MB_TGPIO_07 {3}
MB_TGPIO_01 {3}
MB_TGPIO_09 {3}
MB_CTS {3}
MB_TXD {3}MB_RXD {3}
MB_RTS {3}
MB_WLAN_SLEEP_CLK {3}
MB_WCI_RXD {3}MB_WCI_TXD {3}
MB_REF_CLK {3}MB_DVI_WAO {3}MB_DVI_CLK {3}MB_DVI_TX {3}MB_DVI_RX {3}
MB_TGPIO_10 {3}
MB_GPS_PPS {3}
MB_RSVD_J4 {3}MB_RSVD_M5 {3}
MB_SPI_MOSI_AUX {3}MB_SPI_MISO_AUX {3}
FPGA_DONE {10}
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
FPGA Bank 0
7 11
Dror G.
0502LE910C1
CS1868A
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
FPGA Bank 0
7 11
Dror G.
0502LE910C1
CS1868A
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
FPGA Bank 0
7 11
Dror G.
0502LE910C1
CS1868A
R61300402
R600 00603
U601
PCAL6408ABS
P02
P13
P24
P35
P47
P58
P69
VDD(P)14
ADDR16
RESET1
P710
INT11
SDA13
VSS6
SCL12
VDD(I2C)15
PAD17
C601100nF
040216V
TP600
R607 0
Y600
6MHzGND
2OUT
3
VCC4
EN1
R616 0DNP
R615 0
D601YELLOW
R619330
04025%
R612100K
04021%
TP605
R602 00603
DNP
R609 0
TP610
D600YELLOW
R1
R2
Q601BCR135W
1 B
2
E
3
CC607100nF
040216V
C602100nF
040216V
TP604
R603 2204025%
R6012.2K
04025%
C605100nF
040216V
R611100K
04021%
TP606
R606 0
C60310nF
040225V
TP607
C60610nF
040225V
R1
R2
Q600BCR135W
1 B
2
E
3
C
R60400402
DNP
C600100nF
040216V
R610100K
04021%
R617 0
BANK0
LCMXO3LF-1300E-5MG256C
U600A
VCCIO0F6
VCCIO0F7
VCCIO0F8
VCCIO0F9
PT24AA3
PT23AA4
PT21CA5
PT21AA6
PT19DA7
PT18C/SCL/PCLKT0_0A8
PT17B/PCLKC0_1A9
PT16BA10
PT13CA11
PT13BA12
PT11AA13
PT9AA14
PT9CA15
PT24BB3
PT23BB4
PT21DB5
PT21BB6
PT19CB7
PT18D/SDA/PCLKC0_0B8
PT17A/PCLKT0_1B9
PT16AB10
PT13DB11
PT13AB12
PT11BB13
PT9BB14
PT24C/INITNC4
PT22BC5
PT20D/PROGRAMNC6
PT20C/JTAGENBC7
PT18BC8
PT18AC9
PT16C/TCKC10
PT16D/TMSC11
PT12D/TDIC12
PT11CC13
PT24D/DONED5
PT22AD6
PT20AD7
PT19AD8
PT17DD9
PT12BD10
PT12C/TDOD11
PT11DD12
PT22DE5
PT22CE6
PT20BE7
PT19BE8
PT17CE9
PT12AE10
PT10BE11
PT10AE12
TP608
R614 0
TP602
C604100nF
040216V
R608 0
R6052.2K
04025%
R620330
04025%
TP609
TP601
R618 0FPGA_I2C_SDA
FPGA_I2C_SCL
JTAGENPROGRAMN
INITN
FPGA_CLK_IN
I2C_SDA
I2C_SCLFPGA_DBG_LED2FPGA_DBG_LED1
-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
To/From MODEM
To/From SLOT2
FPGA MODE SELECTOR
DIR:H A->BDIR:L B->A
VCCIO2
VCCIO11.8V
1.8V
3.3V
3.3V
3.3V
VCCIO1 3.3V
VCCIO2
SLT2_WCI_TX{5}SLT2_WCI_RX{5}
SLT2_ALERT_N{5}SLT2_WDIS1_N{5}SLT2_WDIS2_N{5}SLT2_RST_N{5}
SLT2_COEX3{5}
SLT2_DVI_CLK {5}SLT2_DVI_TX {5}SLT2_DVI_RX {5}SLT2_DVI_WAO {5}SLT2_LED1_N {5}SLT2_LED2_N {5}
SLT2_RTS {5}SLT2_CTS {5}SLT2_TXD {5}SLT2_RXD {5}
SLT2_SUSCLK_32K{5}
SLT2_SPI_MISO {5}SLT2_SPI_MOSI {5}SLT2_SPI_CLK {5}
SLT2_SPI_CS_N {5}
SLT2_WIFI_SDRST {5}SLT2_HOST_IRQ_N {5}
TGPIO_01{2}TGPIO_02{2}TGPIO_03{2}TGPIO_04{2}TGPIO_05{2}TGPIO_06{2}TGPIO_07{2}TGPIO_08{2}TGPIO_09{2,3}TGPIO_10{2}
TXD {2}
RTS {2}
DVI_RX {2}
SPI_MISO {2}
RXD {2}
CTS {2}
REF_CLK {2}
DVI_CLK {2}
DVI_TX {2}DVI_WAO {2}
SPI_MOSI {2}
SPI_CS_N {2}
SPI_CLK {2}
WCI_TXD {2}WCI_RXD {2,3}
WLAN_SLEEP_CLK {2}
RSVD_L4{2,3}RSVD_K4{2,3}
RSVD_J4{2}RSVD_M5{2}
I2C_SCL{2,3,4,5,6,7}
I2C_SDA{2,3,4,5,6,7}
WIFI_SDRST {2}RSVD_P7 {2}GPS_SYNC {2}
VREG_MSME {2,3}
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
FPGA Bank 1&2
8 11
Dror G.
0502LE910C1
CS1868A
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
FPGA Bank 1&2
8 11
Dror G.
0502LE910C1
CS1868A
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
FPGA Bank 1&2
8 11
Dror G.
0502LE910C1
CS1868A
U700
SN74CB3Q3251PWR
VCC16
B14
B23
B32
B41
B515
B614
B713
B812
NC6
A5
S011
S110
S29
OE7
GND8
R70410K
04025%
TP702
TP709
BANK1
LCMXO3LF-1300E-5MG256C
U600B
VCCIO1G6
VCCIO1H5
VCCIO1J5
PR1AA2
PR2AB1
PR1BB2
PR3BC1
PR2BC2
PR2DC3
PR4AD1
PR3AD2
PR2CD3
PR1CD4
PR5CE1
PR4BE2
PR4DE3
PR1DE4
PR6BF1
PR5DF2
PR4CF3
PR3CF4
PR7B/PCLKC1_0G1
PR6AG2
PR5BG3
PR5AG4
PR3DG5
PR7CH1
PR7A/PCLKT1_0H2
PR6DH3
PR6CH4
PR9AJ1
PR7DJ2
PR9DJ3
PR9CJ4
PR9BK1
PR10AK2
PR10DK3
PR11CK4
PR10BL1
PR10CL2
PR12CL3
PR12DL4
PR11DL5
PR11AM1
PR11BM2
PR13AM3
PR14BM4
PR12AN1
PR13BN2
PR14AN3
PR14DN4
PR12BP1
PR13DP2
PR14CP3
PR13CR1
TP712
R70510K
04025%
C701100nF
040216V
TP701
C705100nF
040216V
TP706
R7100
0603
TP708
C714100nF
040216V
0
4
8
C
F 213
56
7A
9B
ED
SW700
RTE1600G44
1
C
4
8
2
C70210nF
040225V
BANK2
LCMXO3LF-1300E-5MG256C
U600C
VCCIO2L7
VCCIO2L8
VCCIO2L9
VCCIO2L10
PB25A/SNM5
PB22AM6
PB21BM7
PB18BM8
PB12BM9
PB9BM10
PB6AM11
PB3DM12
PB25B/SI/SISPIN5
PB22BN6
PB21AN7
PB18AN8
PB12AN9
PB9AN10
PB6BN11
PB3CN12
PB25DP4
PB25CP5
PB19DP6
PB19CP7
PB12DP8
PB12CP9
PB9CP10
PB8DP11
PB6CP12
PB3AP13
PB24AR2
PB22CR3
PB21DR4
PB19BR5
PB18DR6
PB16B/PCLKC2_1R7
PB16CR8
PB11B/PCLKC2_0R9
PB9DR10
PB8B/SO/SPISOR11
PB8CR12
PB6DR13
PB3BR14
PB24BT2
PB22DT3
PB21CT4
PB19AT5
PB18CT6
PB16A/PCLKT2_1T7
PB16DT8
PB11A/PCLKT2_0T9
PB11DT10
PB11CT11
PB8A/MCLK/CCLKT12
PB5A/CSSPINT13
PB5BT14
C70810nF
040225V
TP710R70610K
04025%
TP707
C700100nF
040216V
C709100nF
040216V
TP703
R702 00603
DNP
C710100nF
040216V
U701
SN74CB3Q3251PWR
VCC16
B14
B23
B32
B41
B515
B614
B713
B812
NC6
A5
S011
S110
S29
OE7
GND8
R70710K
04025%
C703100nF
040216V
C706100nF
040216V
R711 33004025%
C70710nF
040225V R703 22
04025%
U702
SN74AVC4T245DR
VCCA1
1DIR2
2DIR3
1A14
1A25
2A16
2A27
GND_88
GND_99
2B210
2B111
1B212
1B113
2OE14
1OE15
VCCB16
TP700
TP704
R70810K
04025%
C711100nF
040216VR700 0
0603
R70910K
04025%
TP711
C713100nF
040216V
R701 00603
C712100nF
040216V
TP705
FPGA_SPI_CS_N
FPGA_SPI_MOSI
FPGA_SPI_MISO
FPGA_SPI_CLKFPGA_SPI_MCS_N
MODE_SEL1MODE_SEL4MODE_SEL2MODE_SEL8
TGPIO_02TGPIO_03TGPIO_04TGPIO_05TGPIO_06TGPIO_07TGPIO_08TGPIO_10
TGPIO_03TGPIO_02TGPIO_05TGPIO_04TGPIO_07TGPIO_06TGPIO_10TGPIO_08
3.3V_I2C_SEL03.3V_I2C_SEL13.3V_I2C_SEL2
I2C_SEL_OE_N
I2C_SEL_OE_N
I2C_SEL2
I2C_SEL1
I2C_SEL0 3.3V_I2C_SEL0
3.3V_I2C_SEL1
3.3V_I2C_SEL2
3.3V_I2C_SEL_OE_N
I2C_SEL0I2C_SEL1I2C_SEL2I2C_SEL_OE_N
FPGA_EXT_OSC_SEL
FPGA_RST_N
FPGA_EXT_OSC_SEL
SLT2_SPARE1
SLT2_SPARE2SLT2_SPARE3SLT2_SPARE4
SPARE1SPARE2
SPARE3SPARE4
-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
To/From SLOT1
To/From SLOT1
To/From SLOT3
VCCIO3
VCCIO4
VCCIO5
1.8V
3.3V
1.8V
3.3V
1.8V
3.3V
SLT1_SUSCLK_32K {4}
SLT1_WIFI_HOST_WAKE_N {4}
SLT1_DVI_CLK {4}SLT1_DVI_TX {4}SLT1_DVI_RX {4}SLT1_DVI_WAO {4}SLT1_LED1_N {4}SLT1_LED2_N {4}
SLT1_RTS {4}SLT1_CTS {4}SLT1_TXD {4}SLT1_RXD {4}
SLT1_WCI_TX {4}SLT1_WCI_RX {4}
SLT1_ALERT_N {4}SLT1_WDIS1_N {4}SLT1_WDIS2_N {4}SLT1_RST_N {4}
SLT1_COEX3 {4}
SLT3_RST_N {6}
SLT3_TXD {6}
SLT3_BOOT {6}
SLT3_SUSCLK_32K {6}
SLT3_SPI_CS_N {6}
SLT3_SPI_MOSI {6}SLT3_SPI_CLK {6}
SLT3_WDIS1_N {6}SLT3_OFF_N {6}
SLT3_LED1_N {6}
SLT3_SPI_MISO {6}
SLT3_RXD {6}
SLT3_IRQ_N {6}SLT3_TX_BLANK {6}
SLT3_SYNC {6}
SLT1_WIFI_SDRST {4}
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
FPGA Bank 3&4
9 11
Dror G.
0502LE910C1
CS1868A
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
FPGA Bank 3&4
9 11
Dror G.
0502LE910C1
CS1868A
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
FPGA Bank 3&4
9 11
Dror G.
0502LE910C1
CS1868A
R8020
0603
R800 00603
C800100nF
040216V
C80510nF
040225V
C810100nF
040216V
R803 00603
DNP
TP803
R805 00603
BANK4
LCMXO3LF-1300E-5MG256C
U600E
VCCIO4H12
VCCIO4J12 PL6A
G15
PL6BG16
PL6CH13
PL6DH14
PL7AH15
PL7BH16
PL9CJ13
PL9DJ14
PL7D/PCLKC4_0J15
PL7C/PCLKT4_0J16
PL10DK14
PL9BK15
PL9AK16
PL10BL15
PL10CL16
PL10AM16
C81110nF
040225V
C803100nF
040216V
TP804
C806100nF
040216V
TP800
TP805
R801 00603
DNP
C80110nF
040225V
R804 00603
DNP
C804100nF
040216V
C808100nF
040216V
TP801
R806 00603
DNP
TP806
TP802
BANK3
LCMXO3LF-1300E-5MG256C
U600D
VCCIO3L11
VCCIO3L12 PL11C
K13
PL12DL13
PL11DL14
PL14AM13
PL12CM14
PL11BM15
PL14BN13
PL14CN14
PL12B/PCLKC3_0N15
PL11AN16
PL14DP14
PL13CP15
PL12A/PCLKT2_0P16
PL13AR15
PL13DR16
PL13BT15
C802100nF
040216V
R807 2204025%
C807100nF
040216V
C809100nF
040216V
BANK5
LCMXO3LF-1300E-5MG256C
U600F
VCCIO5F11
VCCIO5G12 PL1A/L_GPLLT_FB
B15
PL1B/L_GPLLC_FBB16
PL1DC14
PL2A/L_GPLLT_INC15
PL2B/L_GPLLC_INC16
PL1CD13
PL2CD14
PL3A/PCLKT5_0D15
PL3B/PCLKC5_0D16
PL2DE13
PL4DE14
PL4CE15
PL5CE16
PL3DF12
PL3CF13
PL5AF14
PL5BF15
PL5DF16
PL4AG13
PL4BG14
SLT3_SPARE1SLT3_SPARE2
SLT3_SPARE3
SLT1_SPARE1SLT1_SPARE2
SLT1_SPARE3SLT1_SPARE4
-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DIR:H A->BDIR:L B->A
OptionalBackup JTAG
FPGA Programming port
FT_3.3V
FT_3.3V
FT_3.3V
FT_3.3V
FT_3.3V
FT_1.8V
FT_1.8VFT_3.3V
FT_3.3V
FT_3.3V
VCCIO0
VCCIO0
FT_3.3V VCCIO0
VCCIO0
VCCIO0
FPGA_TCK {7}
FPGA_TDI {7}
FPGA_TMS {7}
FPGA_TDO {7}
FPGA_DONE{7}
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
FPGA Programmer
10 11
Dror G.
0502LE910C1
CS1868A
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
FPGA Programmer
10 11
Dror G.
0502LE910C1
CS1868A
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
FPGA Programmer
10 11
Dror G.
0502LE910C1
CS1868A
C909100nF
040216V
R91110K
04025%
U904
SN74AVC1T45DBVR
VCCA1
GND2
A3
VCCB6
DIR5
B4
C9164.7uF
040210V
C9074.7uF
040210V
R904 00402
C904100nF
040216V
R9014.7K
04025%
5V
D-
D+
ID
G
USB_MINI-BP900
1
2
3
4
S2
5
S1 S3S4
C9064.7uF
040210V
U900
MIC5319-3.3YD5
VOUT5
VIN1
EN3
GND2
BYP4
C919100nF
040216V
C915100nF
040216V
R90910K
04025%
C92210nF
040225V
DNP
C908100nF
040216V
R91310K
04025%
R902 00402
R9032.2K
04025%
C910100nF
040216V
FT2232HLU903
VREGIN50
VREGOUT49
DM7
DP8
REF6
RESET#14
EECS63
EECLK62
EEDATA61
OSCI2
OSCO3
TEST13
ADBUS016
ADBUS117
ADBUS218
ADBUS319
VPH
Y4
VPLL
9
VCO
RE
12
VCO
RE
37
VCO
RE
64
VCC
IO20
VCC
IO31
VCC
IO42
VCC
IO56
AGN
D10
GN
D1
GN
D5
GN
D11
GN
D15
GN
D25
GN
D35
GN
D47
GN
D51
PWREN#60
SUSPEND#36
ADBUS421
ADBUS522
ADBUS623
ADBUS724
ACBUS026
ACBUS127
ACBUS228
ACBUS329
ACBUS430
ACBUS532
ACBUS633
ACBUS734
BDBUS038
BDBUS139
BDBUS240
BDBUS341
BDBUS443
BDBUS544
BDBUS645
BDBUS746
BCBUS048
BCBUS152
BCBUS253
BCBUS354
BCBUS455
BCBUS557
BCBUS658
BCBUS759
U905
93LC56B
CS1
CLK2
DI3
DO4
VSS5 NC_66
VCC8
NC_77
C9051uF
060325V
U901
SN74AVC4T245DR
VCCA1
1DIR2
2DIR3
1A14
1A25
2A16
2A27
GND_88
GND_99
2B210
2B111
1B212
1B113
2OE14
1OE15
VCCB16
C912100nF
040216V
R910330
04025%
DNP
R90810K
04025%
L901
120R@100MHz040225%
C9004.7uF
040210V
U902
SN65220
NC_11
GND2
NC_33
A6
B4
GND5
C917100nF
040216V
Y900
12MHz
1
42
3
C911100nF
040216V
L902
120R@100MHz040225%
R9004.7K
04025%
R906 12K04021%
J900
SHF-105-01-L-D-SM-K
DNP
1 23 4
657 89 10
L900
120R@100MHz040225%
C902100nF
040216V
R9074.7K
04025%
C913100nF
040216V
R9122.2K0402
5%
R905 2.2K04025%
C918100nF
040216V
C9218pF
040250V
C923100nF
040216V
C9208pF
040250V
C901100nF
040216V
C914100nF
040216V
C903100nF
040216V
FT_XTIN
FT_XTOUT
FT_E
EDAT
CO
N_F
T_VB
US
CON_FT_USBDMFT_USBDM
CON_FT_USBDP FT_USBDP
FT_VPHY_3.3V
FT_VPLL_3.3V
FT_E
ECS
FT_E
ECLK
FT_VBUS
FT_TCKFT_TDIFT_TDOFT_TMS
FPGA_TDOFPGA_TDIFPGA_TMSFPGA_TCK
-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1.8V I/O Power regulator
Power Good
LCMXO3LF-1300C-5BG256C part is 3.3V VCC capableLCMXO3LF-1300E-5MG256C part is 1.2V VCC
3.3V Slots Power regulator
1.2V FPGA Core Power regulator
VBATT 1.8V
VBATT
3.3VSLT1_3.3V
SLT2_3.3V
SLT3_3.3V
VBATT
FPGA_VCC_1.2V
FPGA_VCC_1.2V
VBATT
1.8V
VAUX_PWRMON{2,3}
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
Power Regulators
11 11
Dror G.
0502LE910C1
CS1868A
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
Power Regulators
11 11
Dror G.
0502LE910C1
CS1868A
Drawing Title:
Size Schematic Number Rev
Date: Sheet of
Page Title:
Designer:
Project: Project Number:
A
MultiTech IF TLB
A3
Wednesday, February 14, 2018
Power Regulators
11 11
Dror G.
0502LE910C1
CS1868A
C1020470nF
040210V
C1004100nF
040216V
C101010uF
060310V
R1004 00603
R1001 4.7K04025%
DNP
C101422uF
06036.3V
C1009100nF
040216V
C101510uF
060310V
C101910uF
060310V
C1021100nF
040216V
DNP
C1003100nF
040216V
C1016470nF
040210V
C10001uF
04026.3V
C1017100nF
040216V
DNP
R1007 00603
C100610uF
060310V
R1013100K
04021%
C101210nF
040225V
U1002TLV62084
GND2
SW7
GND3
FB4EN
1 VOS5VIN
8
PG6
EP9
R1012 4.7K04025%
DNP
R1
R2
Q1000BCR135W
1 B
2
E
3
C
R10020
0603
R10170
0402
DNP
C1001100nF
040216V
C101810uF
060310V
C1013100nF
040216V
DNP
D1000YELLOW
R100300402
DNP
L1000 1uH
2016 20%2.2A
R10116.8K
04021%
LCMXO3LF-1300E-5MG256C
U600G
VCCH7
VCCH8
VCCH9
VCCH10
VCCJ7
VCCJ8
VCCJ9
VCCJ10
GNDA1
GNDA16
GNDF5
GNDF10
GNDG7
GNDG8
GNDG9
GNDG10
GNDG11
GNDH6
GNDH11
GNDJ6
GNDJ11
GNDK5
GNDK6
GNDK7
GNDK8
GNDK9
GNDK10
GNDK11
GNDK12
GNDL6
GNDT1
GNDT16
C100510nF
040225V
R10050
0402
U1001
TPS73618DBVR
IN1
GND2
EN3
OUT5
NR/FB4
C1007100nF
040216V
C1022100nF
040216V
C100810uF
060310V
R100000402
R10140
0603
C1011100nF
040216V
R1018 4.7K04025%
DNP
R1009330
04025%
R1006 00603
U1000
TPS73601DBVR
IN1
GND2
EN3
OUT5
NR/FB4
R100843K
04021%
C1002100nF
040216V
R101500402
R10160
0402
R1010 4.7K04025%
VREG_1.8V_EN
VREG_3.3V_IN
VREG_3.3V_FB
VREG_1.2V_IN
PG_L
ED_K
VREG_3.3V_PG
VREG_3.3V_EN
VREG_1.2V_FB
VREG_1.2V_EN
AishwaryaNaFile Attachment
AishwaryaNaStamp
-
LE910Cx Multi Technology Interface Board TLB - HW User Guide
1VV0301508 Rev. 2 Page 22 of 24 2019-03-08
7. ACRONYMS
EVB Evaluation Board
IFBD Interface Board
GPIO General Purpose Input Output
SD Secure Digital
UART Universal Asynchronous Receiver Transmitter
UMTS Universal Mobile Telecommunication System
USB Universal Serial Bus
USIF Universal Serial Interface
FPGA Field Programmable Array
-
LE910Cx Multi Technology Interface Board TLB - HW User Guide
1VV0301508 Rev. 2 Page 23 of 24 2019-03-08
8. DOCUMENT HISTORY
Revision Date Changes
1 2018-02-27 Intial Version
2 2019-03-08 Updated Table 1: FPGA Mode Selection.
-
[01.2
017]
Mod. 0805 2017-01 Rev.6
NoticeCopyrightsComputer Software CopyrightsUsage and Disclosure RestrictionsApplicability TableContents1. Introduction1.1. Scope1.2. Contact Information, Support1.3. Text Conventions1.4. Related Documents1.5. Document Organization
2. General Description2.1. MultiTech Interface Board TLB view
3. FPGA3.1. Programming the FPGA3.1.1. Prerequisites
3.2. FPGA Mode Selection
4. 120-Pin Board to Board Connectors5. Component Assembly Diagram6. Schematics7. Acronyms8. Document History
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