jianhui gu the ohio state university

1J. Gu, FNAL, Nov. 19-21, 2008

Jianhui Gu

The Ohio State University

A Digital CFEB for CSC upgrade

2J. Gu, FNAL, Nov. 19-21, 2008

Current CFEB design• Production version: Nov. 2001• Functional diagram:

CH1-16Layer 1

BUCKEYE

SCH1-16

TCH1-16

HS_CH1-8

ADC

COMPARATOR

SCA

12+1bitOUT1

CH1-16Layer 6

12+1bit6:1mux

6.7 MHz

21:3 CL

2:1muxHS_CH1-8

LVDSconverter

24

DMB

TMB

• Bottleneck: * SCA single output channel to ADC

20s per event for eight time sample (400ns) readout, Constraint on the LCT/L1A latencies (<3.2s) & SCA depth

* Channel linkSkewClear Cable, limited to ~17 meter (ME1/1 on border)

280Mbps

40MHz

3J. Gu, FNAL, Nov. 19-21, 2008

MGT

Proposed Digital CFEB* Technology Development: Serial Links, FPGA:

Multi-channel ADC in a small package (Analog Devices: AD9222)Multi-gigabit Transceiver, high speed serial link on FPGALarge memory inside FPGA

* Functional diagram:

CH1-16Layer 1

BUCKEYE

SCH1-16

TCH1-16

HS_CH1-8

COMPARATOR

CH1-16Layer 6

2:1muxHS_CH1-8

LVDSconverter

24 TMB

20MHz8-ch 12-bit ADC

20MHz8-ch 12-bit ADC

8Memories@240Mbps / 2 as DDR

DMB

FPGA

LCT

L1A

8

MGT

Three layers of memories: Before LCT, between LCT and L1A, after L1A

No dead time for LCT&L1A matching (readout) rate of ~50KHz

4J. Gu, FNAL, Nov. 19-21, 2008

Digital CFEBTo current DMB/TMB:

OK: FPGA firmware control, possibility of slower data rate for longer cables for DAQ.

To ‘new’ DMB/TMB with fiber link: Better: FPGA firmware control, Fit more CFEBs per DMB/TMB

7.5”

5J. Gu, FNAL, Nov. 19-21, 2008

Digital CFEB• Power Consumption comparison:

+6 V +5 V +3.3 V +1.8 V

Current CFEB ~0.5 A ~1 A ~0.5 A 0 A

Digital CFEB ~0.5 A ~0 A ~1 A ~ 5 AAmplifier SCA, FPGA I/O, Comp ADC, FPGA

Current CFEB: ~ 10 W

Digital CFEB: ~ 15-20 W

• Cost: Digital CFEB ~$1400, (compatible with current CFEB)

6J. Gu, FNAL, Nov. 19-21, 2008

Digital CFEBOption 1: Build Digital CFEBs for ME1/1 (move Current

CFEBs to ME4/2)Total Digital CFEB: 72*5*(1+15%) = 414

Option 2: Build Digital CFEBs for full readout of ME1/1(A)Total CFEB: 72*7*(1+15%) = 580

Question 1: Plan for new LVDB?Lower voltage, higher current (esp. +1.8V)

Question 2: New DMB/TMB schedule? Digital CFEB IO interface

Question 3: Size of the Digital CFEB? The width stays the same (determined by chamber input

cables), the length can be reduced. Most likely keeping the current size

7J. Gu, FNAL, Nov. 19-21, 2008

BACKUP slideCost estimate (from Feb. 2008)

8J. Gu, FNAL, Nov. 19-21, 2008

Digital CFEBCost Estimate:

ASIC ADC FPGA Misc PCB Assem.

Current CFEB

$460 $90 $60 $233 $206 $76

Digital CFEB

~ $600 $300 $200 $200 $100

~$1400 per new CFEB

•ADC: Analog Device: AD9252 ($50 more)/AD9222 ($100 less)•FPGA: Xilinx, Virtex-4? ~350 IO, 1 Mb RAM, 2 MGT

9J. Gu, FNAL, Nov. 19-21, 2008

Digital CFEBTotal Cost:

Option 1: ME4/2 addition (ME1/1 swapping)Total CFEB: 72*5*(1+15%) = 414Total cost: $1400*414 = $580K + spare parts + R/D + labor

Option 2: ME4/2 addition and ME1/1/A full readoutTotal CFEB: 72*7*(1+15%) = 580Total cost: $1400*580 = $812K + spare parts + R/D + labor

* In both cases, The SLHC issue is dealt with assuming that the ME1/1 has the highest data rate (much higher than other chambers)

* The new DMB design cost (if there will be a new design, the ME1/1A full readout requires new DMB) can be balanced by replacing the costly skew-clear cables